WO2002078188A1

WO2002078188A1 - Apparatus for generating spread spectrum frequency-modulated clock pulses having reduced electromagnetic interference (emi)

Info

Publication number: WO2002078188A1
Application number: PCT/KR2002/000488
Authority: WO
Inventors: In Ho Song
Original assignee: Neomicros, Inc.
Priority date: 2001-03-23
Filing date: 2002-03-23
Publication date: 2002-10-03
Also published as: KR20020074980A

Abstract

A spread spectrum clock generator comprises an oscillator for generating a reference clock pulse, a first clock generator responsive to the reference clock pulse for generating a first clock pulse having a first frequency, a second clock generator responsive to the first clock pulse for generating a second clock pulse having a second frequency, and a processing device for distributing electromagnetic interference (EMI) spectral components of the first and second clock pulses into a predetermined frequency to generate the spread spectrum frequency-modulated clock pulse which reduces a spectral amplitude of the EMI spectral component.

Description

APPARATUS FOR GENERATING SPREAD SPECTRUM

FREQUENCY-MODULATED CLOCK PULSES HAVING REDUCED

ELECTROMAGNETIC INTERFERENCE (EMI)

TECHNICAL FIELD

The present invention relates to a spread spectrum clock generator. More particularly, it relates to an apparatus for generating spread spectrum frequency- modulated clock pulses which reduces a spectral amplitude of an electromagnetic interference (EMI) component from a reference clock pulse and maintains a constant spreading ratio .

BACKGROUND ART

In general, it is desirable to raise the processing speed of a central processing unit (CPU) to improve efficiency of a computer system by increasing the operating clock frequency of the CPU. If the clock frequency is increased, the operating frequency of the computer system increases and peripheral devices (for example, memory, graphic card, etc.) can also be operated at a higher frequency. However, as the clock frequency becomes higher, more electromagnetic energy is emitted along the signal paths synchronized with the higher frequency clock, and the system suffers from increased EMI. As a result, a conventional system cannot freely increase the clock frequency due to such EMI problems.

For EMI, a method for generating a spread spectrum clock was developed, which reduces the EMI by modulating an output frequency in response to a predetermined frequency modulation profile, thus allowing the clock frequency to be increased. Fig. 1 shows a spectral energy distribution for pulses from a known clock. Specifically, Fig. 1 shows a spectral energy distribution of the clock pulses in frequency domain before/after using the spread spectrum clock (SSC) technique. As shown in Fig. 1, a magnitude Δ of the EMI reduction is determined by a modulated amount δ and the shape of the spectral energy distribution of spread spectrum clock pulses.

Fig. 2 shows a Hersheykiss profile among a plurality of frequency modulation profiles used in the spread spectrum clock generation technique. In case of a down- spreading, the spread spectrum clock is modulated between a normalized frequency f_nom and the down-spreading frequency (l-δ)f_nom by the profile depicted in Fig. 2, and, this profile determines the shape of the spectral energy distribution of spread spectrum clocks. This spread spectrum clock generation technique is practical as it basically prevents the EMI emission by modulating a frequency of the clock. Fig. 3 is a block diagram showing a conventional spread spectrum clock generator using a prescaler. Referring to Fig. 3, the conventional spread spectrum clock generator 100 connects an oscillator 101 for generating a reference clock to a first prescaler 102, connects a voltage-controlled oscillator (VCO) 105 for generating a voltage-controlled clock to a second prescaler 106, and uses a phase-locked loop (PLL) for comparing an output signal of the first prescaler 102 with an output signal of the second prescaler 106. In this case, the spread spectrum clock generator 100 generates a spread spectrum clock by controlling the two prescalers 102 and 106 with LUT (Look-Up Table) 107 included in a modulation frequency generator 10. The LUT 107 is referred by a reversible counter 108 synchronized to a reference clock. The modulation frequency generator 10 further includes a serial link 109, and a programmable counter 110. The serial link 109, which is not required for operation, may be used to program different values in the prescalers 102 and 106 or look-up table 107 to modify modulation characteristics. The programmable counter 110 divides the signal from the oscillator 101 by a predetermined integer number.

In the conventional spread spectrum clock generator 100, LUT 107 should be consulted at least twice within one modulation period with square modulation case, and in order to allow a prescaler' s value modified by the LUT consultation to modify a frequency of the VCO 105 of the phase-locked loop. At least one operation of a phase frequency detector 103 every LUT consultation is necessary.

With reference to Fig. 3, as the timing of the phase frequency detection is not synchronized to the timing of the LUT 107' s consultation, at least two operations of the phase frequency detector 103 per a LUT consultation are required. As a result, if we assume the spread spectrum frequency modulation period is more than 30kHz, the frequency of the input signal of the phase frequency detector 103 should be more than 120kHz. When using an improved method such as a conventional Hersheykiss modulation profile shown in Fig. 2, a minimum frequency of the input signal of the phase frequency detector 103 may be single or tens of MHz because many LUT consultations per one period of the spread spectrum frequency modulation are necessary. Based on the aforementioned conclusion, a VCO 105' s frequency range and a reference clock frequency, a maximum value of the prescaler, which is generally tens or hundreds of the values, is determined. It is impossible for this prescaler to implement a linear or Hersheykiss modulation profile while satisfying a spread spectrum modulation ratio of 0.6%, which is defined in the CK98 specification manufactured by the Intel Corporation. Besides the apparatus shown in Fig. 3, a plurality of spread spectrum clock generators using analog modulation are well known to those skilled in the art. There are two kinds of spread spectrum clock generators, namely, a spread spectrum clock generator for modulating a control voltage of the VCO, and a spread spectrum clock generator for modulating a reference clock. However, for modulating the control voltage, the modulation linearity of the VCO becomes a major issue to cover wide operating frequency range, which is very sensitive to the variations of process, voltage and temperature. It is also difficult for modulating the reference clock to maintain a constant modulation ratio on the process, voltage and temperature variations, and they cannot support various frequencies.

DISCLOSURE OF THE INVENTION

It is, therefore, an object of the present invention to provide a spread spectrum clock generator which reduces EMI spectral amplitude measured over a wide frequency bandwidth in a reference clock, maintains a constant spreading ratio, and useful for digital circuits operated at a high frequency.

In accordance with one aspect of the present invention, an apparatus for generating a spread spectrum frequency-modulated clock pulse comprises an oscillator for generating a reference clock pulse; a first clock generator for receiving the reference clock pulse, and generating a first clock pulse having a first frequency; a second clock generator for receiving the first clock signal, and generating a second clock pulse having a second frequency; and a means for distributing an electromagnetic interference (EMI) spectral component of the first and second clock pulses into a predetermined frequency to generate the spread spectrum frequency-modulated clock pulse which reduces a spectral amplitude of the EMI spectral component .

BRIEF DESCRIPTIONS OF THE DRAWINGS

The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments in conjunction with the accompanying drawings, in which Fig. 1 shows a spectral energy distribution of a clock pulse;

Fig. 2 shows Hersheykiss frequency modulation profile;

Fig. 3 is a block diagram showing a conventional spread spectrum clock generator using a prescaler; and

Fig. 4 is a block diagram for the spread spectrum clock generator using two phase-locked loops (PLLs) in accordance with the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention will now be described in detail with reference to the accompanying drawings . A spread spectrum clock generator according to the present invention comprises a clock pulse generator for generating successive clock pulses, and a spread spectrum frequency modulator for distributing an EMI spectral component of the clock pulses from the clock pulse generator into a wide frequency range, and minimizing a peak amplitude of the EMI spectral component. The clock pulse generator can be implemented with two cascaded phase- locked loops (PLLs) including a prescaler. The spread spectrum frequency modulator functions as a prescaler controller for modulating a frequency of the clock pulse, periodically modulates the frequency of the clock pulse according to a predetermined modulation period and a frequency modulation profile.

Fig. 4 is a block diagram illustrating a spread spectrum clock generator in accordance with a preferred embodiment of the present invention.

Referring to Fig. 4, the spread spectrum clock generator 200 includes an oscillator 601, a prescaler controller 602 connected to the oscillator 601 and a serial link (not shown) , the cascaded first and second phase- locked loops (PLLs) 603 and 604 connected to the oscillator 601 and the prescaler controller 602, an output sealer 605 connected to the second phase-locked loop (PLL) 604, and a clock buffer 606 connected to an output sealer 605. The oscillator 601 generates a reference clock signal and transmits the reference clock signal to the prescaler controller 602 and the first phase-locked loop 603.

The first phase-locked loop 603 includes a first reference input divider 610 connected with the oscillator 601 and the prescaler controller 602, a first feedback divider 611 connected with the prescaler controller 602, a first phase frequency detector 612 connected with the first reference input divider 610 and the first feedback divider 611, the first charge pump and loop filter 613 connected with the first phase frequency detector 612, and the first voltage-controlled oscillator (VCO) 614 connected with the first charge pump and loop filter 613.

The second phase-locked loop 604 includes a second reference input divider 620 connected with the first voltage-controlled oscillator 614 of the first phase-locked loop 603 and the prescaler controller 602, a second feedback divider 621 connected with the prescaler controller 602, a second phase frequency detector 622 connected with the second reference input divider 620 and the second feedback divider 621, a second charge pump and loop filter 623 connected with the second phase frequency detector 622, and a second voltage-controlled oscillator 624.

The first reference input divider 610 receives Rl output signal of the prescaler controller 602, generates a clock pulse having the 1/R1 frequency of the reference clock pulse frequency received from the oscillator 601, and transmits the generated clock pulse to the first phase frequency detector 612. The first feedback divider 611 receives VI output signal of the prescaler controller 602, generates a clock pulse having the 1/V1 frequency of VCK1 output clock pulse frequency of the first voltage-controlled oscillator 614, and transmits the generated clock pulse to the first phase frequency detector 612.

The first phase frequency detector 612 compares a phase and a frequency of the output clock pulse of the first reference input divider 610 with a phase and a frequency of the output clock pulse of the first feedback divider 611, generates a voltage corresponding to a difference between them, and transmits the compared result to the first charge pump and loop filter 613.

The first charge pump and loop filter 613 performs an analog-to-digital conversion (ADC) and a low-pass filtering (LPF) operation about the output voltage of the first phase frequency detector 612, converts the 612' s output voltage to another output voltage having a predetermined dynamic characteristic, and then transmits the converted output voltage to the first voltage-controlled oscillator 614. The first voltage-controlled oscillator 614 generates VCK1 clock pulse of the frequency corresponding to the output voltage of the first charge pump and loop filter 613, and transmits the VCK1 clock pulse to the first feedback divider 611 and the second reference input divider 620 of the second phase-locked loop 604. The second reference input divider 620 receives R2 output signal of the prescaler controller 602, generates a clock pulse having 1/R2 frequency of the VCK1 clock pulse frequency of the first voltage-controlled oscillator 614, and then transmits the clock pulse to the second phase frequency detector 622.

The second feedback divider 621 receives V2 output signal of the prescaler controller 602, generates a clock pulse having 1/V2 frequency of the VCK2 output pulse frequency of the second voltage-controlled oscillator 624, and then transmits the clock pulse to the second phase frequency detector 622.

The second frequency detector 622 compares a phase and a frequency of the output clock pulses of the second reference input divider 620 with a phase and a frequency of the second feedback divider 621, generates a voltage corresponding to a difference between them, and transmits the generated voltage to the second charge pump and loop filter 623. The second charge pump and loop filter 623 performs an analog-to-digital conversion (ADC) and a low-pass filtering (LPF) operation about the output voltage signal generated from the second phase frequency detector 622, converts the 622' s output voltage to an another output voltage having a predetermined dynamic characteristic, and then the converted output voltage to the second voltage- controlled oscillator 624.

The second voltage-controlled oscillator 624 generates VCK2 clock pulse of the frequency corresponding to the output voltage of the second charge pump and loop filter 623, and transmits the VCK2 clock pulse to the second feedback divider 621 and the output sealer 605.

The prescaler controller 602 receives the reference clock signal from the oscillator 601, is programmed by a control signal generated from the serial link (not shown) , generates a plurality of output signals Rl, VI, R2, and V2, transmits the output signals Rl and VI to the first PLL 603, transmits the output signals R2 and V2 to the second PLL 604. In other words, the prescaler controller 602 determines the period of the spread spectrum modulation synchronized to the reference clock signal of the oscillator 601 according to the reference clock signal of the oscillator 601 and the serial link control signal, determines the values of Rl, VI, R2, and V2 to modulate the VCKl and VCK2 output clock pulse of the second phase-locked loop 604 every period according to the spread spectrum modulation profile, and then transmits the determined values of Rl, VI, R2, and V2 to the programmable divider 610, 611, 620, and 621, respectively. The output sealer 605 appropriately scales the VCK2 clock pulse of the second voltage-controlled oscillator 624 of the second phase-locked loop 604, generates the resultant clock pulse signal having a required frequency, and outputs a final output clock pulse through the output buffer 606.

The operation of two cascaded phase-locked loops 603 and 604 and a spread spectrum frequency modulation algorithm based on the PLLs 603 and 604 will now be described. First, assuming that the initial divider values of the first and second reference input dividers 610 and 620 and the first and second feedback dividers 611 and 621 are set to Rl, R2, VI, and V2, respectively, and the frequency of the reference clock signal of the oscillator 601 is set to Fx, the initial frequency Fcore of the output clock pulse of the spread spectrum clock generator 200 is as follows :

Fcore = vi vi Fx Eq. (1)

R1 R2 In Eq. (1), a desired initial frequency Fcore can be obtained by the variation of Rl, R2, VI, and V2. Assuming that Fx, which is the frequency of the reference clock signal, is set to a fixed value and the values of Rl and R2 are set to a fixed value, Fcore is as follows:

VI V2 VI V2

Fcore = Fx = c — , c = Fx = const. Eq. (2)

R1R2 R2 Rl

If a period of the spread spectrum frequency modulation is divided into many periods of 2n (where n is an integer), the output frequency, Fcore_! (i=l, 2,...,2n), of the clock pulse of the spread spectrum clock generator 200 for generating spread spectrum clocks is as follows: First, in case of a down-spreading in the state of V1>R2, Fcorei is defined by the following Eq. (3) :

Eq. (3!

A down-spreading in the state of VKR2 is defined by the following Eq. (4) :

V\-i Fcore, = ^c ^— » ^z' = ¹=² _'

Eq. (4;

F nrp-c , i = n+l,n + 2,...,2n r υre, _R2-2n + i

For the down-spreading of V1>R2 shown in the Eq. (3) , the prescaler controller 602 fixes the Rl value of the first reference input divider 610 and the V2 value of the second feedback divider 621, respectively counts up the R2 of the second reference input divider 620 and the VI of the first feedback divider 611 during the half period of the spread spectrum frequency modulation, and then respectively counts down the values of R2 and VI during the other half period. Under this condition, the generated output frequency is defined as Fcorei shown in the Eq. (3) . In this case, the programmed initial value VI of the first feedback divider 611 should be higher than another programmed initial value R2 of the second reference input divider 620 so that the Fcorei follows the down-spreading frequency modulation profile in proportion to the increase of i .

For the down-spreading of VKR2 shown in Eq. (4), the prescaler controller 602 fixes the Rl value of the first reference input divider 610 and the V2 value of the second feedback divider 621, respectively counts down the R2 of the second reference input divider 620 and the VI of the first feedback divider 611 during the half period of the spread spectrum frequency modulation, and then respectively counts up the values of R2 and VI during the other half period. Under this condition, the generated output frequency is defined as Fcorei shown in the Eq. (4) . In this case, the programmed initial value VI of the first feedback divider 611 should be smaller than another programmed initial value R2 of the second reference input divider 620 so that the Fcorei follows the down-spreading frequency modulation profile in proportion to the increase of i .

The first and the second cases of the Eq. (3) are based on the following principle, when m and n are both integers .

n -1 , n . n +1 -<—< if m>n m —1 m m + 1

Eq. (5) W - 1 . 7J 71 + 1 ) — ) i f m<n m -\ m m +\

In other words, if a denominator and numerator of a fraction are changed with the same magnitude and the denominator is larger than the numerator, the magnitude of the entire fraction is proportional to the magnitude of the numerator because the variation of the numerator becomes relatively larger as compared with the variation of the same numerator and denominator. On the other hand, if the numerator becomes larger than the denominator, the magnitude of the entire fraction is inversely proportional to the magnitude of the numerator because the variation of denominator becomes relatively larger as compared with the variation of the same numerator and denominator. Accordingly, as Fcore_x, the frequency of the output clock signal of the spread spectrum clock generator, is expressed as a fraction, the denominator and numerator are properly set to a predetermined value. Then, each divider for determining the values of the denominator and numerator in response to the magnitude of the denominator and numerator performs a counting-up or counting-down operation, thereby modulating the spread spectrum frequency.

While the invention has been described with reference to its preferred embodiments, it will be apparent to those skilled in the art that variations and modifications are possible without deviating from the broad principles and teachings of the present invention. All such adaptations are considered within the scope and spirit of the present invention, which is defined by the claims appended hereto.

INDUSTRIAL APPLICABILITY

As shown above, the spread spectrum clock generator according to the present invention reduces EMI spectral amplitude measured over a wide frequency bandwidth in a reference clock, maintains a constant spreading ratio, and is used for a digital circuit operated at a high frequency. Furthermore, the modulation method of the present invention controls the initial value of each divider as well as an increase/decrease magnitude every period of each divider, and thus provides an effective spread spectrum clock generation value having various spread magnitudes.

Claims

1. A clock generator for generating a spread spectrum frequency-modulated clock, comprising: an oscillator for generating a reference clock pulse; a first clock generator responsive to the reference clock pulse for generating a first clock pulse having a first frequency; a second clock generator responsive to the first clock pulse for generating a second clock pulse having a second frequency; and means for distributing electromagnetic interference

(EMI) spectral components of the first and second clock pulses into a predetermined frequency to generate the spread spectrum frequency-modulated clock pulse which reduces a spectral amplitude of the EMI spectral component.

2. The clock generator of claim 1, wherein the first and second clock generators include first and second phase- locked loops, respectively.

3. The clock generator of claim 2, wherein said first phase-locked loop includes: a first divider for dividing a frequency of the reference clock pulse by a first divider value to generate a intermediate clock pulse; a second divider for dividing a frequency of the first clock pulse by a second divider value to generate a second intermediate clock pulse; a first phase frequency detector for comparing a phase and frequency of the first intermediate clock pulse from said first divider with a phase and frequency of the second intermediate clock pulse of said second divider to generate a first output voltage corresponding to a difference therebetween; a first filter for performing analog-to-digital conversion (ADC) and low-pass filtering (LPF) operation upon the first output voltage from the first phase frequency detector to generate a second output voltage having predetermined dynamic characteristics; and a first voltage-controlled oscillator for generating the first clock pulse having the first frequency corresponding to the second output voltage from said first filter, the first clock pulse being fed to said second divider and said second phase-locked loop for a next dividing and phase-locked loop operation.

4. The clock generator of claim 3, wherein said second phase-locked loop includes: a third divider for dividing a frequency of the first clock pulse by a third divider value to generate a third intermediate clock pulse; a fourth divider for dividing a frequency of the second clock pulse by a fourth divider value to generate a fourth intermediate clock pulse; a second phase frequency detector for comparing a phase and frequency of the third intermediate clock pulse from said third divider with a phase and frequency of the fourth intermediate clock pulse from said fourth divider to generate a third output voltage corresponding to a difference therebetween; a second filter for performing analog-to-digital conversion (ADC) and low-pass filtering (LPF) operation upon the third output voltage from the second phase frequency detector and for generating a fourth output voltage having predetermined dynamic characteristics; and a second voltage-controlled oscillator for generating the second clock pulse having the second frequency corresponding to the fourth output voltage from said second filter, the second clock pulse being fed to said fourth divider for a next dividing operation.

5. The clock generator of claim 4, wherein said means includes a controller which fixes the first and fourth divider values, divides a spread spectrum frequency modulation period into 2xn periods (where n is an integer number) , and controls the second and third divider values such that: when V1>R2 (VI and V2 are initial values of the second and third divider values, respectively) , the second and third divider values are set to Vl+i and Rl+i, respectively within the ith period (i=l, 2, 3, ..., n) , and set to Vl+2n-j and

Rl+2n-j, respectively within the jth period (j=n+l, n+2, ..., 2n) .

6. The clock generator of claim 4, wherein said means includes a controller which fixes the first and fourth divider values, divides a spread spectrum frequency modulation period into 2xn periods (where n is an integer number) , and controls the second and third divider values such that: when VKR2 (VI and R2 are initial values of the second and third divider values, respectively) , the second and third divider values are set to Vl-i and Rl-i, respectively within the ith period (i=l, 2, ..., n) , and set to Vl-2n+j and Rl-2n+j, respectively in the jth period (j=n+l, n+2, ..., 2n) .