JP2001014056A - Semiconductor integrated circuit and spread spectrum clock oscillator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce EMI by properly using a spread spectrum clock signal with a simple structure in a semiconductor integrated circuit device with a central processing part, a memory and a peripheral circuit part. SOLUTION: A first clock signal with fixed cycle is generated by a clock oscillator 17. The first clock signal is supplied to a timer/counter 15 and a communicating part 16 by the clock oscillator 17. The first clock signal generated by the clock oscillator 17 is supplied to a spread spectrum clock oscillator 18 as well. A second clock signal with fluctuating cycle is generated by the spread spectrum clock oscillator 18. The second clock signal as a spread spectrum clock signal is supplied to the memory 11, the central processing part 12, a general purpose port.A/D converting part.others 13 and an interruption controller 14 by the spread spectrum clock oscillator 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device having a central processing unit, a memory, and a peripheral circuit unit, and more particularly to a semiconductor integrated circuit device and a spread spectrum clock oscillator capable of effectively preventing electromagnetic interference.

[0002]

2. Description of the Related Art In recent years, by dispersing the energy of a harmonic spectrum using a spread spectrum clock generator (SSCG), an electromagnetic interference (EMI) in a circuit device has been developed.
Techniques for reducing magnetic interference (hereinafter referred to as "EMI") have been reported.

[0003] In the first place, EMI is caused by the fact that a power supply current flows in synchronization with a main clock driving a system, and harmonics of the power supply radiate and diffuse. The reason for synchronizing with the main clock is that the signal flow is usually restricted in synchronization with the clock, so that many gates in the circuit device operate in synchronization with the main clock, and as a result, the power supply current Is modulated by the main clock.

[0004] A spread spectrum clock oscillator is described in, for example, Japanese Patent Application Laid-Open No. 9-98152 corresponding to US Patent No. 5,631,920. The technique described in Japanese Patent Application Laid-Open No. 9-98152 is intended to reduce the EMI by dispersing a harmonic spectrum by slightly changing a clock cycle which should be originally fixed. In other words, in order to operate at high speed in the system, for example, the bus timing between the memory and the memory is designed to be at the limit of the high-speed limit. I understand. In addition, a timer / counter that counts a clock to measure time and a communication interface for performing communication with the outside require an accurate time. I do. Accordingly, it is necessary to obtain the maximum EMI reduction effect with a limited frequency change.
) Is obtained. JP-A-9-
Japanese Patent Publication No. 98152 discloses such a technique.

The above-mentioned Japanese Patent Application Laid-Open No. 9-98152 discloses, for example, a table, a first counter, a second counter, a phase detector, and a voltage controlled oscillator (VCO: volt).
age controlled oscillator) to form a phase locked loop, and the output of the phase locked loop is
A spread-spectrum clock oscillator is disclosed that results in a spread-spectrum clock signal to be supplied to a clock-controlled electronic device. Different parts of the table in which the digital values are stored are addressed by different counts of the first counter. The second counter receives a digital value that is addressed for each change in the count of the first counter. In response to the reference frequency clock signal,
The second counter is stepped after the second counter receives each digital value. In response to the second counter reaching a predetermined value, the first counter is stepped and provides one input to the phase detector. The voltage controlled oscillator receives the output of the phase detector and supplies another input to the phase detector to form a phase locked loop.

In Japanese Patent Application Laid-Open No. 62-63327, a plurality of delay lines are provided at the output of an
It is disclosed that by selectively switching these delay lines with an output read / write signal, an apparent jitter is generated in a clock signal supplied to a microcomputer. JP-A-11-15550 discloses that a control voltage supplied to a voltage-controlled oscillator is switched by a selector driven by a counter.
FM (frequency modulation) modulation of the oscillator output is disclosed. JP-A-8-16274 discloses that the oscillator output is FM-modulated by modulating the power supply of the oscillator.

FIG. 3 shows a configuration of a conventional example of a semiconductor integrated circuit device having a central processing unit, a memory, and a peripheral circuit unit. The semiconductor integrated circuit device includes a memory 111,
Central processing unit (CPU) 11
2. General-purpose port / A / D (analog-digital) converter / others 113, interrupt controller 114, timer / counter 115, communication (SIO: serial input / out)
put) unit 116 and a clock oscillator (CG: clock gen)
erator) 117. The clock oscillator 117 generates a clock signal having a fixed period, and outputs the clock signal to the memory 111, the central processing unit 112, the general-purpose port, the A / D converter, and the like.
3, interrupt controller 114, timer / counter 1
15 and the communication unit 116 to drive them synchronously. In this manner, all the components of the semiconductor integrated circuit device are driven by the clock oscillator 117, and the power supply current flows in synchronization with the clock signal of a fixed period generated by the clock oscillator 117, so that the harmonics are radiated and diffused. Then, EMI occurs.

FIG. 4 shows a general configuration of a PLL applicable to the clock oscillator 117 and the like. The PLL is
Original oscillator 121, phase detector 122, charge pump 1
23, a voltage controlled oscillator (VCO) 124 and a programmable frequency divider 125. The output of the original oscillator 121 is input to the phase detector 122. Phase detector 122
Is supplied as a control voltage to a voltage controlled oscillator 124 via a charge pump 123. Voltage controlled oscillator 1
The oscillation output of the oscillator 24 is divided by a programmable divider 125 at a dividing ratio based on a constant C given as a dividing ratio, and is supplied to a phase detector 122 so that the original oscillator 12
1 output. The PLL is configured in this manner, and the oscillation output of the voltage controlled oscillator 124 is output to the outside, for example, as a clock signal. By appropriately setting the constant C for determining the frequency division ratio in the programmable frequency divider 125, various clock cycles can be set.

[0009]

The use of a spread spectrum clock oscillator as described above reduces EMI.
However, in a spread spectrum clock oscillator as disclosed in Japanese Patent Laid-Open No. 9-98152, the configuration of the spread spectrum clock oscillator becomes complicated. Also, JP-A-62-63327, JP-A-11-15
In the techniques disclosed in Japanese Patent Application Laid-Open No. 550 and Japanese Patent Application Laid-Open No. H8-16274, the period of the clock signal is varied by an analog method, and the operation is sufficiently appropriate in terms of operation stability and controllability. Generating a spread spectrum clock signal is not easy.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has been developed in a semiconductor integrated circuit device having a central processing unit, a memory, and a peripheral circuit unit by appropriately using a spread spectrum clock signal with a simple configuration. It is a first object of the present invention to provide a semiconductor integrated circuit device capable of effectively reducing the power consumption.

Another object of the present invention is to provide a spread spectrum clock oscillator suitable for the above-described semiconductor integrated circuit device, which can appropriately generate a spread spectrum clock signal with a simple configuration. The purpose of.

[0012]

To achieve the first object, a semiconductor integrated circuit device according to a first aspect of the present invention is a semiconductor integrated circuit device having a central processing unit, a memory, and a peripheral circuit unit. A first clock generating means for supplying a clock signal having a constant cycle to a communication unit for performing communication with the outside and a timer unit for measuring time, of the peripheral circuit unit, and for driving the communication unit and the timer unit And supplying the spread spectrum clock signal whose frequency periodically changes with respect to the clock signal having the constant period to the remaining part of the peripheral circuit part except the communication part and the timer part, the central processing part and the memory, And a second clock generating means for driving the central processing unit and the memory.

[0013] The second clock generating means is provided with the first clock generating means.
Phase detection means having a clock signal of a fixed period generated from the clock generation means as one input as an original clock, and control for outputting an oscillation output whose oscillation frequency is controlled by the output of the phase detection means as a spread spectrum clock signal An oscillating unit, a programmable frequency dividing unit that divides an oscillation output of the control oscillating unit by given data and uses the divided output as the other input of the phase detection unit to form a phase locked loop, Up / down counting means for alternately repeating up-counting and down-counting for the output of the circulating means in a predetermined count value range, and adding a constant to a signed count output of the up / down counting means to obtain the programmable frequency division. Means for supplying divided data to the means. It can have.

The communication unit and the timer unit are asynchronous interface means for exchanging information with at least a part of the peripheral circuit unit excluding the communication unit and the timer unit, a central processing unit, and a memory. May be included.

In order to achieve the second object, a spread spectrum clock oscillator according to a second aspect of the present invention comprises: an original oscillating means for generating an original clock signal; Detection means, control oscillation means for outputting an oscillation output whose oscillation frequency is controlled by the output of the phase detection means as a spread spectrum clock signal, and dividing the oscillation output of the control oscillation means by given data; A programmable frequency divider that forms a phase-locked loop using the frequency-divided output as the other input of the phase detector; and an output of the programmable frequency divider that repeats up-counting and down-counting alternately for a predetermined count value range. / Counting means, and a signed count output of the up / down counting means. By adding the number comprises a adding means for supplying the frequency division data in the programmable divider means.

In the semiconductor integrated circuit device according to the first aspect of the present invention, a communication unit for performing communication with the outside and a timer unit for measuring time among the peripheral circuit units are provided with first clock generation means. , A clock signal having a constant period is supplied to drive the communication unit and the timer unit, and the remaining of the peripheral circuit unit excluding the communication unit and the timer unit, the central processing unit and the memory are provided with a second clock. The generating means supplies a spread spectrum clock signal whose frequency periodically changes with respect to the clock signal having the fixed period, and drives the remaining part, the central processing unit and the memory. Therefore, a clock signal supplied to most of the inside of the semiconductor integrated circuit device is used as a spread spectrum clock signal, and a clock signal having a constant cycle is supplied to a communication unit and a timer unit which handle a common time with the outside, so that a peripheral circuit can be controlled. Spurious can be dispersed by using a spread spectrum clock signal for driving other than the communication unit and the timer unit inside, and EMI can be effectively reduced with a simple configuration.

In a spread spectrum clock oscillator according to a second aspect of the present invention, original oscillation means for generating an original clock signal, phase detecting means having the original clock signal as one input, and an output of the phase detecting means. Control oscillation means for outputting an oscillation output whose oscillation frequency is controlled as a spread spectrum clock signal, and dividing the oscillation output of the control oscillation means by given data, and dividing the divided output by the other of the phase detection means. A phase-locked loop is constituted by a programmable frequency divider as an input,
The output of the programmable frequency dividing means is supplied to an up / down counting means, and up counting and down counting are alternately repeated within a predetermined count value range. A constant is added to the count output and supplied to the programmable frequency dividing means as frequency-divided data. Therefore, it is possible to appropriately generate a spread spectrum clock signal with a simple configuration.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

An embodiment of a semiconductor integrated circuit device incorporating a spread spectrum clock oscillator according to the present invention will be described with reference to FIGS. FIG. 1 shows a configuration of a semiconductor integrated circuit device, and FIG. 2 shows details of a spread spectrum clock oscillator used in the semiconductor integrated circuit device of FIG.

The semiconductor integrated circuit device shown in FIG. 1 has a memory 11, a central processing unit (CPU) 12, a general-purpose port A / D
It includes a converter / others 13, an interrupt controller 14, a timer / counter 15, a communication (SIO) unit 16, a clock oscillator (CG) 17, and a spread spectrum clock oscillator (SSCG) 18.

The clock oscillator 17 is a first clock generator, and generates a first clock signal having a constant period. The clock oscillator 17 supplies the first clock signal to the timer / counter 15 and the communication unit 16 via the first clock line, and drives these units. The first clock signal generated by the clock oscillator 17 is
It is also supplied to the spread spectrum clock oscillator 18. The spread-spectrum clock oscillator 18 is a second clock generating means, and generates a first clock based on a first clock signal.
, A second clock signal composed of a spread spectrum clock signal whose period varies with reference to the period of the clock signal is generated. The spread spectrum clock oscillator 18 generates a second clock signal that is a spread spectrum clock signal,
The memory 11, the central processing unit 12, the general-purpose port / A / D converter / others 13, and the interrupt controller 14 are supplied via the second clock line to drive these units.

Memory 11, central processing unit 12, general-purpose port / A / D conversion unit / others 13, interrupt controller 1
4. The timer / counter 15 and the communication unit 16 are connected to an internal bus, and exchange information with each other via the internal bus. The transmission and reception of signals between the memory 11, the central processing unit 12, the general-purpose port / A / D conversion unit / others 13 and the interrupt controller 14, and the timer / counter 15 and the communication unit 16 are performed by the timer / counter 15 and the communication unit 16. And the internal bus via asynchronous interfaces 15a and 16a, respectively.

FIG. 2 shows a specific configuration of the spread spectrum clock oscillator 18 using a PLL. The spread spectrum clock oscillator 18 includes the clock oscillator 17
Operates as an original oscillator to generate a spread spectrum clock signal. The spread spectrum clock oscillator 18 includes a phase detector 21, a charge pump 22, and a voltage controlled oscillator 2
3. It has a programmable frequency divider 24, an up / down counter 25 and an adder 26.

The output of the clock oscillator 17 serving as the original oscillator is input to the phase detector 21. The output of the phase detector 21 is supplied to a voltage controlled oscillator 23 as a control voltage via a charge pump 22. The oscillation output of the voltage controlled oscillator 23 is supplied to an adder 26 in a programmable frequency divider 24.
Is divided by the frequency division ratio based on the data given by the clock generator 17, supplied to the phase detector 21 and compared with the output of the clock oscillator 17. Thus, a PLL is configured.

The output of the programmable frequency divider 24 is supplied to an up / down counter 25. The up / down counter 25 counts the output of the programmable frequency divider 24 and alternates between an up-count from “0” to “n (n is a natural number) and a down-count from“ n ”to“ 0 ”. And periodically repeated. The count value of the up / down counter 25 is supplied to the adder 26 as signed. The adder 26 adds a constant C to the signed count value of the up / down counter 25, supplies the result to the programmable frequency divider 24, and determines the frequency division ratio. The constant C is appropriately set as needed, and determines a reference frequency division ratio.

Next, the semiconductor integrated circuit device configured as described above will be described more specifically.

The semiconductor integrated circuit device shown in FIG. 1 has a central control unit 12, a memory 11, and general-purpose ports / A / D converters / others 13, an interrupt controller 14, a timer / counter 15, a communication unit 16, and the like. The circuit is, for example, a microcontroller (M
CU: micro controller unit-hereinafter referred to as “MCU”).

The timer / counter 15 is a peripheral circuit for generating date and time information, and counts a clock to measure time. The communication unit 16 is a peripheral circuit for performing communication between the MCU and an external device.
Performs serial communication conforming to interface specifications such as 2C.

The clock signal to be supplied to the timer / counter 15 and the communication section 16 needs to be a clock signal having a constant period without jitter, and is supplied from the clock oscillator 17 as an original oscillator via the first clock line to the first clock line. Provides a clock signal. The parts other than the timer / counter 15 and the communication unit 16, that is, the memory 11, the central processing unit 12, the general-purpose port / A / D conversion unit / others 13, and the interrupt controller 14 are supplied from the spread spectrum clock oscillator 18 to the clock oscillator 17. A second clock signal whose frequency periodically changes based on the output frequency is supplied via a second clock line. At this time, the memory 11, the central processing unit 12, the general-purpose port / A / D
Conversion unit / others 13 and interrupt controller 14
The transmission / reception of data between the timer / counter 15 and the communication unit 16 through the internal bus is performed by the timer / counter 1
5 and the communication unit 16 are provided via asynchronous interfaces 15a and 16a, respectively.

As shown in FIG. 2, the spread spectrum clock oscillator 18 supplies the output of the programmable frequency divider 24 to an up / down counter 25, and repeats up-counting and down-counting cyclically. The count value is treated with a sign, applied to an adder 26, and the result of adding the multiplier C is input to a programmable frequency divider 24. A comparison input that oscillates by one cycle is supplied to the phase detector 21. . As a result, the cycle of the output of the voltage controlled oscillator 23 also changes according to the vibration.

As described above, the clock supplied to most of the inside of the MCU is the second clock signal supplied from the spread spectrum clock oscillator 18 and the timer / counter 1
The first clock signal from the original clock oscillator 17 is supplied to the parts that handle time outside the MCU, such as the communication unit 5 and the communication unit 16. Therefore, the higher the frequency, the higher the frequency of the harmonic spurs generated by clock synchronization becomes from the center frequency, and the lower the peak, the lower the spurious.
I can be effectively reduced.

Although the configuration in which the frequency division ratio of the program divider is changed every cycle as the spread spectrum clock oscillator has been described, the output of a normal PLL may be FM-modulated with a sine wave without preparing a special one. You may make it.

[0033]

As described above, according to the present invention,
In a semiconductor integrated circuit device having a central processing unit, a memory, and a peripheral circuit unit, a semiconductor integrated circuit device capable of effectively reducing EMI by appropriately using a spread spectrum clock signal with a simple configuration can be provided.

Further, according to the present invention, it is possible to appropriately generate a spread spectrum clock signal with a simple configuration, and to provide a spread spectrum clock oscillator suitable for the above-described semiconductor integrated circuit device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a block diagram schematically showing details of a spread spectrum clock oscillator used in the semiconductor integrated circuit device of FIG. 1;

FIG. 3 is a block diagram showing a configuration of an example of a conventional semiconductor integrated circuit device.

FIG. 4 is a block diagram schematically showing details of a phase locked loop (PLL) used in a conventional clock oscillator.

[Description of Signs] 11 Memory 12 Central Processing Unit (CPU) 13 General-purpose Port / A / D Unit / Others 14 Interrupt Controller 15 Timer / Counter 16 Communication (SIO) Unit 17 Clock Oscillator (CG) 18 Spread Spectrum Clock Oscillator (SSCG) 21) phase detector 22 charge pump 23 voltage controlled oscillator (VCO) 24 programmable frequency divider 25 up / down counter 26 adder

Claims (4)

[Claims] 1. A semiconductor integrated circuit device having a central processing unit, a memory, and a peripheral circuit unit, wherein a communication unit that communicates with the outside of the peripheral circuit unit and a timer unit that measures time are provided with a clock having a fixed period. A first clock generating means for supplying a signal and driving the communication unit and the timer unit; and the remaining part of the peripheral circuit unit excluding the communication unit and the timer unit, the central processing unit and the memory, A semiconductor integrated circuit, comprising: a spread spectrum clock signal whose frequency periodically changes with respect to the clock signal; and a second clock generating means for driving the remainder, a central processing unit, and a memory. Circuit device. 2. The second clock generating means includes: a phase detecting means which receives a clock signal of a fixed period generated from the first clock generating means as an original clock as one input, and an output of the phase detecting means. A control oscillating means for outputting an oscillation output whose oscillation frequency is controlled as a spread spectrum clock signal; and dividing the oscillation output of the control oscillating means by given data, and dividing the divided output by the other of the phase detecting means. A programmable frequency dividing means forming a phase locked loop as an input; an up / down counting means for alternately repeating an up count and a down count for an output of the programmable frequency dividing means for a predetermined count value range; Adding a constant to the signed count output of The semiconductor integrated circuit device according to claim 1, adding means for supplying to the frequency dividing means as a frequency division data, comprising the to. 3. The communication unit and the timer unit are asynchronous for transmitting and receiving information to and from the remaining part of the peripheral circuit unit excluding the communication unit and the timer unit, the central processing unit, and at least a part of the memory. 3. The semiconductor integrated circuit device according to claim 1, further comprising an interface unit. 4. An original oscillating means for generating an original clock signal, a phase detecting means having the original clock signal as one input, and a spread spectrum clock whose oscillation frequency is controlled by an output of the phase detecting means. A control oscillating means for outputting as a signal, a programmable frequency dividing means for dividing the oscillation output of the control oscillating means by given data, and using the divided output as the other input of the phase detecting means to constitute a phase locked loop An up / down counting means for alternately repeating an up-count and a down-count for an output of the programmable frequency dividing means for a predetermined count value range; and adding a constant to a signed count output of the up / down counting means. Adding means for supplying to the programmable frequency dividing means as frequency-divided data, The spread spectrum clock generator, characterized by Bei.