JP2005006123A - Lvds receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an LVDS receiver which is not affected by the change of transition time and is capable of maximizing a skew margin. <P>SOLUTION: The LVDS receiver is provided with a voltage controlled oscillator having a plurality of stages of ring oscillators and a frequency divider of which the multiplication ratio is 2. The LVDS receiver is further provided with: a PLL circuit 2 which divides the frequency of the output signal of each stage of the voltage controlled oscillator by using the frequency divider; a common edge sense timing generator 7 which uses signals having frequencies divided by the PLL circuit 2 to generate clock signals of a plurality of equi-spaced phases from edges being in the same transition state as an input signal edge to which the PLL circuit 2 is locked; and a serial/parallel converter 8 which uses the clock signals generated by the common edge sense timing generator 7 to perform serial/parallel conversion. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
[Industrial application fields]
The present invention relates to an LVDS (Low Voltage Differential Signaling) receiver used for an interface of an FPD (Flat Panel Display) panel represented by an LCD (Liquid Crystal Display) requiring high speed operation and low power consumption, and a semiconductor provided with the LVDS receiver. The present invention relates to an integrated device, and relates to an effective technique that contributes to improving the accuracy and performance of an LVDS receiver by suppressing the influence of manufacturing process variations.
[0002]
[Prior art]
As the LVDS receiver described above, one having a PLL (phase locked loop) circuit is known.
[0003]
FIG. 6 shows the configuration of a conventional PLL circuit. This PLL circuit includes a phase comparator 91, a charge pump 92, a loop filter 93, a voltage controlled oscillator (hereinafter referred to as VCO) 94, and a frequency divider 95.
[0004]
The phase comparator 91 detects a phase difference between the reference signal FR and the feedback signal FP from the frequency divider 95, and outputs a control signal UP for increasing the oscillation frequency of the VCO 94 or a control signal DN for decreasing it. When the feedback signal FP is delayed with respect to the reference signal FR, the phase comparator 91 outputs a control signal UP for increasing the oscillation frequency of the VCO 94 for a period corresponding to the phase difference. On the contrary, when the feedback signal FP is advanced with respect to the reference signal FR, the phase comparator 91 outputs a control signal DN for decreasing the oscillation frequency of the VCO 94 for a period corresponding to the phase difference. As described above, the phase comparator 91 outputs a signal obtained by pulse-modulating the phase difference between the two input signals.
[0005]
The charge pump 92 converts the control signal (UP or DN) from the phase comparator 91 into an analog signal, and the output signal CPO is passed through the loop filter 93 and output to the VCO 94 as the control voltage Vc.
[0006]
The loop filter 93 is a low-pass filter circuit (hereinafter referred to as LPF) composed of a resistor and a capacitor, and it aims to reduce high-frequency noise and the like contained in the output signal CPO from the charge pump 92 and stabilize the feedback loop. It is used for the purpose.
[0007]
The output signal FO of the VCO 94 is output as the output signal FO of the PLL circuit, and is divided by the frequency divider 95 and input to the phase comparator 91 as the feedback signal FP. At that time, since the output signal FO is converted to a frequency of 1 / N by the frequency divider 95, the relationship between the feedback signal FP and the output signal FO is expressed by the following equation (1).
[0008]
[Expression 1]
FP = FO / N (1)
Since the PLL circuit configured as described above controls the control voltage Vc so that FR = FP, the output signal FO is expressed by the following equation (2). That is, an output signal FO having a frequency N times that of the reference signal FR is output from the PLL circuit.
[0009]
[Expression 2]
FO = N × FR (2)
FIG. 7 is a diagram showing a circuit configuration of the serial / parallel converter. This serial / parallel converter is an example in the case of converting 7-bit serial data to parallel data, for example. A serial / parallel converter having seven flip-flops is supplied with a clock obtained by multiplying the input clock from the PLL circuit by seven. The 7-bit serial data is converted into parallel data and output. FIG. 8 is a diagram showing the relationship among the input clock, serial data, and 7-fold clock in this case.
[0010]
However, when the PLL circuit is operated at 7 times as described above, there is a problem that power consumption increases as the speed increases and design for high-speed operation of the VCO becomes difficult. This will be described in detail below. That is, in an LCD interface circuit or the like using an LVDS receiver, it is necessary to multiply the input clock by 7 to generate a serial / parallel conversion latch clock, so that the PLL circuit has a division ratio N = 7. Configure. At this time, the oscillation frequency of the VCO is seven times the input clock (N = 7). However, by multiplying the input clock by 7, the oscillation frequency of the VCO is increased by 7 times, so that power consumption is increased and it is difficult to oscillate the VCO at 7 times the frequency of the input clock. There's a problem.
[0011]
Therefore, a technique for solving the above problem has been proposed (see, for example, Patent Document 1).
[0012]
This proposed technique does not multiply the PLL circuit as shown in FIG. 9, and takes out the outputs p1 to p7 from each stage of the ring oscillator to a plurality of stages of the VCO unit, thereby providing a plurality of equally spaced phase clock signals. Configured to operate serial-parallel conversion using the edges of each clock signal, equalize the load of each stage in a multi-stage ring oscillator, and use each clock signal to make multiple equal intervals This is a technique for generating a phase clock signal. For this reason, since it is possible to perform a multiple frequency latch operation of the input clock signal without multiplying the input clock signal, it is possible to realize a high speed operation at a low oscillation frequency.
[0013]
[Patent Document 1]
JP 2002-94360 A [0014]
[Problems to be solved by the invention]
By the way, in the above proposed technique, the output of each stage of the plurality of ring oscillators constituting the VCO in the PLL circuit is the timing to latch with the polarity opposite to the edge polarity of the input clock signal that locks the PLL circuit, as shown in FIG. Due to the difference between the rising transition time (Δtr) and the falling transition time (Δtf), as shown in FIG. 11, the falling edge positions of p1 to p7 for latching serial data do not become the data valid center. As shown in FIG. 11 (b), when the transition time is short (small), it is further to the left than the center, and when the transition time is long (large), it is to the right of the center. This is because the inverter elements that constitute the ring oscillator have different rising times and falling edge transition times due to variations in manufacturing processes.
[0015]
FIG. 10 shows the timings of the outputs p1 to p7 in each stage of the seven-stage ring oscillator constituting the PLL circuit with respect to the period T.
[0016]
In FIG. 10, when attention is paid to the output waveform of each stage of the ring oscillator with respect to the period T, since the PLL circuit is locked at the rising edge at the period T, the period T of each output waveform is T = tH (High Time; high time) + tL (Low Time; low time). The falling and rising transition times are different due to variations in the manufacturing process of the inverter elements constituting the ring oscillator, the influence of the operating temperature, and the like. Therefore, it can be seen that tH ≠ tL (the duty ratio is not 50%).
[0017]
Therefore, in this technique, when the PLL circuit is locked at the rising edge of the input clock as shown in FIG. 10, the clock for latching the serial data becomes the timing for latching the serial data at the falling edge as shown in FIG. . For this reason, when the transition time changes due to variations in the manufacturing process or the like, the falling edge position where the serial data is latched changes. In other words, when the transition time is small, the edge position for latching the serial data is shifted in the direction of decreasing the setup time (setup-time) as shown in FIG. 11, and conversely when the transition time is large, the hold time (hold− (time) is shifted in a decreasing direction.
[0018]
This change in transition time reduces either the setup / hold time margin when latching serial data as the serial data of the clock signal for serial-to-parallel conversion increases in speed. If skew occurs between data and the clock, serial / parallel conversion may not be performed correctly. In addition, the skew margin, which is an important specification of the LVDS receiver, is also reduced.
[0019]
The present invention has been made to solve such a problem of the prior art, and provides an LVDS receiver that is not affected by changes in transition time and that can maximize the skew margin. Objective.
[0020]
[Means for Solving the Problems]
An LVDS receiver according to the present invention includes a voltage controlled oscillator having a plurality of stages of ring oscillators and a frequency divider having an even multiplication ratio, and each of the output signals of each stage in the voltage controlled oscillator is divided by the frequency divider. And a signal that generates a clock signal having a plurality of phases at equal intervals from the transition state of the input signal edge that is locked by the PLL circuit, using a signal that is frequency-divided by the PLL circuit. And a serial / parallel converter that performs serial / parallel conversion using the clock signal generated by the signal generating means.
[0021]
In the LVDS receiver according to the present invention, the PLL circuit is configured to multiply evenly, and a signal is generated using only one edge (rising or falling) of the output signal at each stage of the ring oscillator constituting the VCO. Since the means are provided, it is possible to create clock signals having a plurality of phases at equal intervals without being affected by manufacturing process variations such as transition time and duty ratio. As a result, the setup / hold margin of the clock signal for each bit of the serial data can be maximized, and the skew tolerance margin of the input clock signal for the serial data can be maximized.
[0022]
In the LVDS receiver of the present invention, the signal generating means may be a common edge sense timing generator that reacts only to the same edge of the input signal. In this configuration, it can be easily manufactured using a flip-flop.
[0023]
In the LVDS receiver of the present invention, the interface LSI, the PLL circuit, and the serial / parallel converter may be formed on a semiconductor substrate. With this configuration, a circuit can be integrated on a semiconductor substrate as a semiconductor integrated device, and the size can be reduced. The interface LSI corresponds to that used for an FPD panel such as an LCD.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be specifically described.
[0025]
FIG. 1 shows a configuration diagram of an LVDS receiver according to the present invention. The LVDS receiver 1 includes an even multiplication PLL circuit 2, LVDS input buffer circuits 3, 4, 5, 6,
It has a common edge sense timing signal generator 7 and a serial / parallel converter 8 as signal generating means. The input buffer circuits 3 to 6 are made of an LSI and used for an interface of an FPD panel such as an LCD, for example. The PLL circuit 2, the LVDS input buffer circuits 3 to 6, a common edge sense timing signal generator 7 and the serial / parallel converter 8 are formed on a single semiconductor substrate 10.
[0026]
As shown in FIG. 2, the PLL circuit 2 includes a phase comparator 21, a charge pump 22, an LPF (loop filter) 23, a VCO 24, and a frequency divider (multiplier) 25.
[0027]
The phase comparator 21 detects a phase difference between the reference clock signal FR and the period signal FP from the frequency divider 25, and outputs a control signal UP for increasing the oscillation frequency of the VCO 24 or a control signal DN for decreasing it. When the feedback signal FP is delayed with respect to the reference signal FR, the phase comparator 21 outputs a control signal UP that increases the oscillation frequency of the VCO 24 for a period corresponding to the phase difference. On the other hand, when the feedback signal FP is advanced with respect to the reference signal FR, the control signal DN for decreasing the oscillation frequency of the VCO 24 is output from the phase comparator 21 for a period corresponding to the phase difference. In this manner, the phase comparator 21 outputs a signal obtained by performing pulse width conversion on the phase difference between the two input signals FR and FP.
[0028]
The charge pump 22 converts the control signal (UP or DN) from the phase comparator 21 into an analog signal, and supplies the output signal CPO to the VCO 24 as the control voltage Vc through the loop filter 23.
[0029]
The loop filter 23 is a low-pass filter circuit composed of a resistor and a capacitor, and is used for the purpose of reducing noise included in the output signal CPO from the charge pump 92.
[0030]
The VCO 24 has seven stages of ring oscillators (inverter elements) 24a, 24b, 24c, 24d, 24e, 24f, and 24g. The output signal S1 of the VCO 24 is output as an output signal of the PLL circuit 2, and The frequency is divided by the frequency divider 25 and input to the phase comparator 21 as the feedback signal FP. At that time, since the output signal S1 is converted to a frequency of 1 / N (N is an integer) by the frequency divider 25, the relationship between the feedback signal FP and the output signal S1 is FP = S1 / N, that is, S1 = N · FP. Thus, N is multiplied. That is, since the PLL circuit 2 operates so that FR = FP, an output signal S1 having a frequency N times that of the reference signal FR is output. Therefore, each of the tap output signals S1 to S7 of the ring oscillator in the VCO 24 similarly has N times the frequency.
[0031]
Here, FIG. 2 shows an example in which the division ratio N, that is, the multiplication ratio N is 2, and the number of stages of the ring oscillator constituting the VCO is seven. With this configuration, a double PLL circuit is obtained. The output timing of the double PLL circuit 2 is as shown in FIG. The LVDS input buffer circuit 3 has serial data (LVDS data 1), the LVDS input buffer circuit 4 has serial data (LVDS data 2), and the LVDS input buffer circuit 5 has serial data (LVDS data 3). However, the LVDS input buffer circuit 6 receives the LVDS input clock signal.
[0032]
As shown in FIG. 5, the common edge sense timing generator 7 is composed of seven stages of flip-flop circuits 7a, 7b, 7c, 7d, 7e, 7f and 7g, and the doubled PLL shown in FIG. The output signals S1 to S7 of the circuit 2 are input, and a clock signal for serial / parallel conversion is generated. As can be seen from the timing chart of FIG. 3, output signals S1 to S7 multiplied by two are used to generate multiphase clock signals CKSP1 to CKSP7 for serial / parallel conversion. When attention is paid to this timing, it can be seen that the polarity of the edge of the input clock signal FR for locking the PLL circuit 2 and the edge of the generated serial / parallel conversion clock signal FP are the same.
[0033]
Since the PLL circuit 2 operates so that the period between the locked edges is matched, the PLL circuit 2 is locked at the rising edge. At this time, if the period of the input clock signal FR is T, the period between the rising edges of the clock signals CKSP1 to CKSP7 is T. Further, serial data (LVDS data 1, LVDS data 2, LVDS data 3) is latched at the same rising edge as the locked edge.
[0034]
Therefore, according to the present embodiment, it is possible to create a clock signal having a plurality of phases at regular intervals without being affected by variations in the manufacturing process such as transition time and duty ratio. The clock signal setup / hold margin for the serial data can be maximized, and the skew tolerance margin of the input clock signal for the serial data can be maximized.
[0035]
FIG. 4 shows an example in which the present invention is applied to an LVDS receiver 1A that receives 7-bit LVDS serial data at the timing shown in FIG. 3 and converts it into 7-bit parallel data. The PLL circuit 2, the LVDS input buffer circuits 3 to 6, the common edge sense timing signal generator 7 and the serial / parallel converter 8 are formed on a single semiconductor substrate 10.
[0036]
The LVDS data 1, 2, and 3 are first received by the LVDS input buffer units 3, 4, and 5, respectively, where they are converted from differential signals to single-phase signals. Similarly, the LVDS input clock signal is also received by the LVDS input buffer unit 6, where it is converted from a differential signal to a single-phase signal and output to the PLL circuit 2. The PLL circuit 2 operates to lock with the LVDS input clock signal. At this time, the configuration of the PLL circuit 2 is configured like the above-described double-multiplication PLL circuit (see FIG. 2), so that the multi-phase clock for performing serial-to-parallel conversion is supplied to the multiplication outputs S1 to S7 of the PLL circuit 2. The common edge sense timing generator 7 can be created from the same edge. As a result, it is possible to generate a multiphase clock signal at equal intervals without being affected by the transition time of rising and falling. The common edge sense timing generator 7 is composed of seven stages of flip-flop circuits 7a to 7g as shown in FIG.
[0037]
The operations of the PLL circuit 2 and the common edge sense timing generator 7 at this time will be described in detail below.
[0038]
FIG. 3 shows the timing of the output signal of the PLL circuit 2 when the frequency is doubled. By multiplying by two, S1 to S7 become S2, S3, S4, S5, S6, and S7 at a timing delayed by Δt (T / 28) by equal intervals with reference to S1. That is, with reference to S1, S2 is inverted from S1 by being delayed by Δt with respect to S1, and S3 is inverted from S2 by being delayed by Δt with respect to S2. The subsequent S4, S5, S6 and S7 are the same.
[0039]
Then, a clock signal for serial / parallel conversion is created using S1 to S7 multiplied by 2 with respect to the reference signal FR. In addition, by generating the clock signals CKSP1 to CKSP7 from the same rising edge in the common edge sense timing generator 7 using the S1 to S7 signals, the influence due to the difference in transition time between the rising and falling edges as described above. No longer receive. This will be described in detail below.
[0040]
When the LVDS data 1, 2, 3 (serial data) and the LVDS input clock signal FR are at the timing shown in FIG. 3, the double PLL circuit 2 is locked at the rising edge of the LVDS input clock signal FR. The phases of the signal FP and the signal FR coincide with each other. The common edge sense timing generator 7 generates clock signals CKSP1 to CKSP7 using the rising edges of the output signals S1 to S7 of the PLL circuit 2. The rising edges of CKSP1 to CKSP7 created in this way are located at each bit of the serial data. At this time, since the PLL circuit 2 is locked at the rising edge and with the period T, the period between the rising edges of the clock signals CKSP1 to CKSP7 is also T. The rising edge intervals of the clock signals CKSP1 to CKSP7 are equal to T / 7. Further, the S1 to S7 signals that generate the clock signals CKSP1 to CKSP7 can be considered in the same manner. Since the VCO oscillates at twice the signal FR, the period between the rising edges of the output signals S1 to S7 is T / 2. is there.
[0041]
Now, when attention is paid to the rising edge positions of the output signals S1 to S7 that create the rising edges of the clock signals CKSP1 to CKSP7, the period is also T. As long as the PLL circuit 2 is locked at the rising edge of the signal FR in the period T, this relationship does not change. In other words, when the relationship between the LVDS data and the LVDS input clock signal as shown in FIG. 3 is used, a signal edge having the same polarity as the edge of the input clock signal locked by the PLL circuit 2 is used. The clock signal for serial / parallel conversion can be created at equal intervals and in multiple phases without using edges that vary depending on the frequency of the signal.
[0042]
On the other hand, in the conventional proposed technique, as shown in FIG. 9, the output of each stage of the seven-stage ring oscillator that is not multiplied is different in rising and falling transition times, so that the PLL circuit is locked at the rising edge. If this is the case, the serial data is latched at the falling edge of the multi-phase clock signal for serial / parallel conversion (see FIG. 10).
[0043]
As shown in FIG. 10, assuming that the period between the rising edge and the rising edge is T, the falling edge position for latching serial data from the difference in transition time between the rising edge and the falling edge is at the center of each bit of the serial data. Must not. In addition, the position of the falling edge changes due to the variation in the manufacturing process, so that the transition time changes to change both. That is, when the transition time is small, the edge position for latching serial data shifts in the direction of decreasing the setup time (setup-time) as shown in FIG. (hold-time) is shifted in a decreasing direction.
[0044]
In this embodiment, since the common edge sense timing generation circuit 7 is configured as shown in FIG. 5, it is possible to generate equidistant 7-phase clock signals using only the same rising edges of the signals S1 to S7. it can. Assuming that the PLL circuit 2 is locked at the rising edge of the input clock, the 7-phase clock signal generated in this way is serial-parallel converted by the serial-to-parallel converter 8 using the same rising edge. The edge of the clock signal of each phase to be latched is positioned at the position of each bit data Valid center of the serial data.
[0045]
Therefore, it is possible to maximize the operation margin with respect to the skew and to configure a stable LVDS receiver. Further, since the same polarity as the edge locked by the PLL circuit is used, it is not affected by the difference in transition time between the rising and falling edges. As a result, a PLL circuit of double frequency is configured, and a clock signal for serial / parallel conversion is generated by the same common edge using the doubled output signal, so that the 7-phase clock signal is converted into a transition time and a duty ratio. Regardless of the influence of the above, it can be obtained at equal intervals. This means that the edge position of the 7-phase clock signal for latching serial data is adjusted to the same position for each bit once by design, and the edge position of the clock signal for serial / parallel conversion can be obtained even if the manufacturing process varies. The serial data setup / hold time for the serial / parallel conversion seven-phase clock can be maximized, and the skew margin can be maximized.
[0046]
In the above description, the configuration is such that a PLL circuit of double multiplication is used. However, the present invention is not limited to this, and a configuration using a PLL circuit of even multiplication is also possible.
[0047]
【The invention's effect】
As described above in detail, in the case of the present invention, the clock signal for latching each bit of the serial data is set to the same edge as the edge of the input clock signal to be locked by the PLL circuit, so that the transition time between the rising and falling edges. The multi-phase clock signal with the same interval can be supplied to the serial-to-parallel converter without being affected by the difference between the LVDS receiver and the skew margin of the LVDS receiver can be maximized, as well as low power consumption and high performance. An LVDS receiver can be realized.
[Brief description of the drawings]
FIG. 1 is a basic configuration diagram of an LVDS receiver of the present invention.
FIG. 2 is a configuration diagram of a PLL circuit used in the LVDS receiver of the present invention.
FIG. 3 is a timing diagram in the LVDS receiver of the present invention.
FIG. 4 is a configuration diagram of a 7-bit-3ch LVDS receiver to which the present invention is applied.
FIG. 5 is a configuration diagram of a common edge sense timing generator used in the LVDS receiver of the present invention.
FIG. 6 is a block diagram of a prior art PLL circuit.
FIG. 7 is a block diagram of a prior art serial-to-parallel converter.
FIG. 8 is a timing diagram of serial / parallel conversion using a 7-fold clock.
FIG. 9 is a configuration diagram of a ring oscillator of the proposed technique (Japanese Patent Laid-Open No. 2002-94360).
FIG. 10 is an explanatory diagram of a timing problem of the proposed technique (Japanese Patent Laid-Open No. 2002-94360).
FIG. 11 is a timing diagram of serial / parallel conversion using a non-multiplying PLL of the proposed technique (Japanese Patent Laid-Open No. 2002-94360).
[Explanation of symbols]
1, 1A LVDS receiver 2 PLL circuit 3, 4, 5, 6 LVDS input buffer circuit (interface LSI)
7 Common edge sense timing signal generator (Signal creation means)
8 Serial-parallel converter 10 Semiconductor substrate

Claims (3)

A PLL circuit including a voltage controlled oscillator having a plurality of stages of ring oscillators and a frequency divider having an even multiplication ratio, and frequency-dividing each output signal of each stage in the voltage controlled oscillator by the frequency divider;
A signal generating means for generating a clock signal having a plurality of phases at equal intervals from an edge of the same transition state as the transition state of the input signal edge locked by the PLL circuit, using the signal divided by the PLL circuit;
An LVDS receiver comprising a serial / parallel converter that performs serial / parallel conversion using the clock signal generated by the signal generating means. 2. The LVDS receiver according to claim 1, wherein the signal generating means is a common edge sense timing generator that reacts only to the same edge of the input signal. 2. The LVDS receiver according to claim 1, wherein the interface LSI, the PLL circuit, the signal generating means, and the serial / parallel converter are formed on a semiconductor substrate.

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