RU2491713C1 - Phase-locked loop based frequency grid synthesiser with fractionality noise compensation - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: frequency grid synthesiser has a pulsed frequency-phase detector, a charge pumping current source, a capacitive element, a switching element, a control loop filter, voltage controlled generator, a fractionally variable ratio divider (FVRD), a division ratio control circuit in the FVRD, a fractionality compensation current source, the output of which is connected to the output of the charge pumping current source.

EFFECT: eliminating residual pulsations of fractionality noise in the control signal of a voltage-controlled generator.

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Description

The invention relates to electronic equipment, in particular to frequency grid synthesizers (FSS) based on a phase-locked loop (PLL) with fractional noise compensation and can be used when using circuits based on pulse-amplitude or pulse-width modulation of the compensation current.

Frequency grid synthesizers are widely used in various devices of computer technology, control, radio automation and communications. One of the most important parameters of the frequency response is the frequency range, frequency resolution (minimum tuning step) and phase noise of the output signals of the synthesized frequencies, as well as the tuning time between the frequencies.

In the frequency response system based on the PLL, the frequency and phase of the voltage-controlled oscillator (VCO) are stabilized. Multiplication of the input reference frequency is ensured by dividing the VCO frequency in the loop feedback circuit. The requirement to decrease the value of the step of the frequency grid of the output signal entails a corresponding decrease in the value of the reference frequency and an increase in the value of the division coefficient. The value of the reference frequency determines the speed with which the PLL can be adjusted between the control pulses. As a result of an increase in the inertia of the PLL, the quality of control parameters is deteriorated as a whole, which generally leads to an increase in the duration of the transient process of automatic frequency control and an increase in the phase noise of the output signal of the MSS. This is the main disadvantage of the SSN using a divider with an integer division factor.

To eliminate the contradiction between the frequency resolution and phase noise, methods have been developed that use dividers with a fractionally variable division coefficient (DDPKD) in the feedback circuit, which realize the division value below the decimal point. The result is the operation of the PLL with the value of the reference frequency far exceeding the value of the step of the frequency grid of the output signal. Such synthesizers are called fractional-N MSS.

In fractional N NSS, a periodic change in the division coefficient occurs in such a way that, on average, the effect of division by a number containing a fractional part is obtained. In the simplest case, for the period of the control sequence Tm, F divisions with the value N + 1 and M - F divisions with the value N are performed. The output frequency of the VCO Fvco is calculated by the formula

$$F_{VCO}=F_{REF}\times \left(N+\frac{F}{M}\right)$$

where Fref is the value of the reference frequency, M is the modulus of fragmentation, equal to the number of frequency periods Fref in the periodic control sequence Tm. The value of the step of the frequency grid of the output signal Fvco is equal to the value of the reference frequency divided by the fractional modulus.

The result of a periodic change in the division coefficients in the DDPCD are periodic phase errors in the PLL loop, called the fragmentation noise. Fractional interference leads to deviations of the instantaneous phase of the output VCO signal from the ideal position in time and, as a result, to the appearance of spurious harmonics in its spectrum.

Thus, the development of methods for compensating for the effect of interference of fractionality in the PLL circuit is one of the main directions in the design technique of fractional-N MSS.

The closest technical solution to the claimed invention is a frequency response circuit based on a PLL with compensation for fragmentation noise described in US patent No. 6639475 B2 "PLL Circuity IPC H03L 7/00 [1]. This scheme is selected as a prototype of the claimed invention and is shown in figure 1.

The circuit of the invention [1] has a first (Fref), second (N) and third (F) inputs and output Fvco. The composition of the scheme of the invention [1] includes:

1 - pulse frequency-phase detector (ICPD), comparing the phase of the signal Fref of the reference frequency and the phase of the signal Ffb of the feedback frequency and generating signals Up and Dn in accordance with the phase difference;

2 - a source of charge pump current (ITNZ), which generates an output current Io in accordance with the output signals of the ICPD;

3 - capacitive element connected to the output of ITNZ for the formation of the control signal Vc;

4 - switching element connected by the first output to the output of the ITNZ and controlled by the Sw signal so that it is transferred to the open state when the ITNZ produces an output current;

5 - filter control loop (PKU) connected to the second output of the switching element (signal Vf) and generating a control signal Vvco;

6 - voltage-controlled oscillator (VCO) generating an output signal Fvco with a frequency in accordance with the output signal of the FCU;

7 - a divider with a fractionally variable division coefficient (DDPKD), dividing the output frequency of the VCO by a coefficient determined by the value of N and the state of the OVER control signal, and generating a feedback frequency signal Ffb;

8 is a diagram of controlling the value of the division coefficient (UKD) in the DPCD, accumulating the value of the phase error of the fractionality Fc in proportion to one period of the output frequency of the VCO, and generating the control signal OVER to form the division fractionation specified by the value F;

9 is a fragmentation compensation current source (ICCD) connected to the second terminal Vf of the switching element and generating current Ic in accordance with the value of the accumulated phase error Fc.

On figa presents a typical block diagram of the UKD fractional-N MSC based on the adder (81), the output value of Fc which increases by F on the signal Ffb. When overflowing, the adder generates an OVER signal.

In order to generate the output compensation current Ic in the ICTD scheme, pulse-amplitude modulation (AIM), pulse-width modulation (PWM), or a combination thereof is used. The main requirement is the equality of the areas of the pulses of the compensation current Ic and the output current Io of the ITNZ circuit.

On figb presents a typical block diagram of ITKD fractional-N MSC based on the AIM current compensation. The duration Tc of the compensation current pulse is equal to one period Tvco of the output frequency of the VCO. The amplitude Ic of the compensation current pulse is equal to the amplitude Io of the ITNZ output current divided by the fractional modulus M and multiplied by the output value Fc of the UCD circuit. The main limitation of the use of AIM is the accuracy of establishing the amplitude Ic of the compensation current for large values of the modulus of fractionality.

On figv presents a typical block diagram of the ICD fractional-N MSC based on the PWM current compensation. The duration Tc of the compensation current pulse is equal to the duration Tvco of the output VCO frequency multiplied by the output value Fc of the RCD circuit. The amplitude Ic of the compensation current pulse is equal to the amplitude Io of the output current of the ITNZ divided by the fractional modulus M. The main limitation of the use of PWM is the impossibility of setting the value of the fractional modulus M greater than the integer part N of the DDPKD coefficient, and, as with AIM, the accuracy of establishing the amplitude of compensation for large values of the modulus of fractionality.

To solve the restrictions imposed on the value of the fractional modulus M, the combined AIM and PWM control are widely used in the formation of the compensation current.

Figure 3 presents diagrams explaining the process of compensating for the interference of fractionality in the PLL of a fractional-N MSS of the invention [1] using the example of AIM of the compensation current with a fractional value F equal to 3/8.

Let the PLL loop be in steady state. Since the average value of the division coefficient is not an integer, inside the periodic control sequence Tm, the phases of the signals Fref of the reference frequency and Ffb of the feedback frequency do not coincide, which leads to the PWM output current of the ITNZ I0. The magnitude of the modulation is proportional to the phase error caused by fractional division. At each phase of the phase comparison in the ICPD, the content Fc of the adder of the UCF scheme increases by a fractional increment F. When the value in the adder reaches the value of the modulus of fragmentation, an overflow signal of the adder is generated, under which the division coefficient in the DDCA changes from N to N + 1. The value of Fc is used when the ITKD circuit generates a current of 1 s to compensate for the current I0 caused by a phase error in the fractionality of the division coefficient in the DDPKD.

The signal Sw controls the switching element so that when the output current I0 of the ITNZ circuit is in the active state, the switching element is open. After the switching element is closed, the transient process of adding up the charges caused by the output currents of the ITPL and ICTD circuits begins, after which the voltage potential of the signal Vf supplied to PKU, returns to its original state. However, the absence of the opposite interaction between the ITNZ and ITKD currents on the capacitive element when the currents are simultaneously active leads to a transient process of mutual compensation of the charges introduced by them after the switching element is closed, which causes residual ripple of the Vf signal. The presence of residual ripple interference noise fragmentation in the VCO control signal is a disadvantage of the invention [1].

In the case of using PWM in the formation of the compensation current, the duration of the transient process of mutual compensation will increase due to the lower current amplitude Ic.

Subsequent filtering of the Vf signal by reducing the passband of the PCF can significantly reduce the amplitude of the residual ripple. However, according to the principle of operation of the PLL, a smaller passband of the PCF will increase the passage of the own low-frequency VCO noise to the output signal of the MSS.

The technical result of the present invention is the elimination of residual ripple interference noise fragmentation in the control signal VCO loop PLL fractional-N MSS when using compensation schemes, noise fragmentation based on AIM or PWM compensation current.

The technical result is achieved due to the fact that when the interference currents of fractionality or compensation of fractionality, being in the active state, change the voltage potential of the capacitive element, the switching element opens the PLL circuit. The circuit closes after the end of the transient process of mutual compensation of charges on the capacitive element introduced by the named currents. For this, in the fractional-N MSS scheme of the invention [1], having first (Fref), second (N) and third (F) inputs, Fvco output and including: ICPD (1) comparing the phase of the reference frequency signal Fref and the phase of the frequency signal feedback Ffb and generating signals Up and Dn in accordance with the phase difference; ITNZ (2), generating an output current I0 in accordance with the output signals of the ICHFD; a capacitive element (3) connected to the output of the ITNZ to form a control signal Vc; a switching element (4) connected to the output of the ITNZ by the first output and controlled by the Sw signal so that it is switched to the open state when the ITNZ produces an output current; PKU (5) connected to the second output of the switching element (signal Vf) and generating a control signal Vvco; VCO (6), generating an output signal Fvco with a frequency in accordance with the output signal of the PKU; DDPKD (7), dividing the output frequency of the VCO in accordance with the OVER control signal and generating a feedback frequency signal; the UKD circuit (8), accumulating the value of the phase error of the fractionality Fc in proportion to one period of the output frequency of the VCO, and generating the control signal OVER to form the fractionality specified by the value of F; The ICTD (9), which generates current in accordance with the value of the accumulated phase error Fc, it is proposed to connect the ITCD output to the ITNZ output, while controlling the switching element so that the switching element is switched to the open state during the transition of the ITCD output to the active state.

As a result, by the end of the compensation current, the output currents of the ITNZ and ITKD, folding on the capacitive element, completely compensate for the charges introduced by each other, and the voltage on the capacitive element returns to the state that was before the switching element opened. Consequently, the input of the FCU will be connected back to the capacitive element after the transition process of compensating for the fragmentation noise on it and, thus, the voltage ripple in the VCO control signal is eliminated. At the time of opening the PLL, the potential of the control voltage of the VCO control signal is stored on the capacitance of the capacitors of the FCU.

The invention is illustrated by the following graphic materials:

Figure 1. The SCN circuit based on the PLL with compensation for fragmentation noise presented in the invention [1], selected as a prototype of the claimed invention.

Figa. Typical block diagram of a fractional N-UCC.

Figb. A typical block diagram of the ICD fractional-N MSC based on AIM current compensation.

Figv. A typical block diagram of the ICD fractional-N MSC based on PWM current compensation.

Figure 3. Diagrams explaining the process of compensating for the interference of the fractionality in the PLL of the fractional-N MSS of the invention [1] by the example of the AIM of the compensation current with the value of the fractionality F equal to 3/8.

Figure 4. The SCN circuit based on the PLL with the compensation of noise fragmentation, claimed in this invention.

Figure 5. Diagrams explaining the process of compensating for the interference of fractionality in the PLL circuit of a fractional-N MSS claimed in this invention, using the example of the AIM of the compensation current with a fractional value F equal to 3/8.

Figa. The spectrogram of the output signal of the fractional-N MSS with a frequency of 166 MHz at a resolution of 1 MHz per division.

Figb. The spectrogram of the output signal of the fractional-N MSS with a frequency of 166 MHz at a resolution of 50 kHz per division.

The SCN circuit based on the PLL with the compensation of noise fragmentation, claimed in this invention, is presented in figure 4. The circuit has first (Fref), second (N) and third (F) inputs, an Fvco output and includes an ICPD (1) having a first input Fref, a second input Ffb, a first output Up and a second output Dn; ITNZ (2) having a first input Up, a second input Dn and an output I0; a capacitive element (3) having a terminal Vc; a switching element (4) having a control input Sw and first and second terminals; PKU (5) having an input Vf and an output Vvco; A VCO (6) having a Vvco input and an Fvco output; DDPKD (7) having a first input Fvco, a second input N, a third input OVER and an output Ffb; a UKD circuit (8) having an input F, a first output OVER and a second output Fc; ITKD (9), having input Fc and output Ic.

The reference frequency signal from the first input Fref of the device is supplied to the first input of the ICHPD circuit. The second input of the ICHPD circuit is connected to the output Ffb of the DDPKD circuit. The outputs Up and Dn of the ICHPD circuit are connected to the corresponding inputs of the ITNZ circuit. The outputs of the ITNZ and ITKD circuits, the output Vc of the capacitive element and the first output of the switching element are interconnected. The second output of the switching element is connected to the input of the FCU circuit, the output of which is connected to the Vvco input of the VCO circuit. The output of the VCO circuit, the first input of the DDPKD circuit and the output of the Fvco device are interconnected. The value of the integer part of the division coefficient from the second input N of the device is supplied to the second input of the DDPKD circuit. The third input of the DDPKD circuit is connected to the first output of the UKD circuit. The value of the fractional part of the division coefficient from the third input F of the device is supplied to the input of the UKD circuit. The input of the ICTD circuit is connected to the second output Fc of the ACD circuit.

The device operates as follows. The ICPD scheme compares the phase of the reference signal Fref and the phase of the feedback frequency signal Ffb and generates the signals Up and Dn in accordance with the phase difference. Based on these signals, the ITNZ circuit generates an output current I0, under the action of which, together with the output current Ic of the ITKD circuit, the signal voltage potential Vc is formed on the capacitive element. The Sw signal controls the switching element so that it switches to the open state for the time when the output currents of the ITNZ or ITKD circuits are in the active state, and to the closed state when the outputs of the ITNZ and ITKD circuits are off. At the output of the PCF circuit, a Vvco signal is generated, which is the control signal for the VCO. The signal Fvco of the output frequency of the VCO is supplied to the DPCD circuit, dividing by N or N + 1 depending on the state of the OVER control signal, and generating a feedback frequency signal Ffb. At each phase of the phase comparison in the ICPD, the UCF circuit accumulates the phase error value Fc in proportion to one period of the VCO output frequency and generates an OVER signal to form the fractionality specified by the value F. The ICD circuit, in accordance with the Fc value of the accumulated phase error, generates a current Ic for pulse compensation current I0 ITNZ caused by fractional division in DDPKD.

Figure 5 presents diagrams explaining the process of compensating for the interference of fractionality in the PLL circuit of a fractional-N MSS claimed in this invention, using the example of an AIM of the compensation current with a fractional value F equal to 3/8.

Let the PLL loop be in steady state. Since the average value of the division coefficient is not an integer, inside the periodic control sequence Tm, the phases of the signals Fref of the reference frequency and Ffb of the feedback frequency do not coincide, which leads to the PWM output current of the ITNZ I0. The magnitude of the modulation is proportional to the phase error caused by fractional division. When the value in the adder of the UCD scheme reaches the value of the modulus of fragmentation, an overflow signal of the adder is generated, under the control of which the division coefficient in the DDPCD changes from N to N + 1. The value of Fc is used when the IKD circuit generates a current Ic to compensate for the current Io caused by a phase error in the fractionality of the division coefficient in the DDPKD.

During the active state of the outputs of the ITNZ and ITKD, the switching element is switched to the open state. In this case, the output currents of the ITNZ and ITKD, folding on the capacitive element (signal Vc), completely compensate for the charges introduced by each other so that after the compensation current is over, the voltage potential on the capacitive element will return to the state that was before the switching element was opened. Thus, the input of the PCF is connected back to the capacitive element after the transition process of compensating for the fragmentation noise on it ends, as a result of which the voltage ripple of the signal Vf will be eliminated. At the time of opening the PLL, the potential of the control voltage of the VCO control signal is stored on the capacitance of the capacitors of the FCU.

To illustrate the quality of the compensation for interference of fragmentation in the PLL of a fractional-N MSC based on the claimed invention, FIG. 6A and FIG. 6B show spectrograms of the output signal of a complex functional block (SF block) of clock frequency synthesizers for an integrated information processing device, implemented using CMOS technology 180 nm. This SF block is built according to a two-level scheme. An external quartz resonator of a real-time clock with a frequency of 32.768 kHz is a reference for the first-level NSS. The first-level MSS has an integer division coefficient in the feedback loop of the PLL and generates a signal in the frequency range 16-30 MHz. Further, the signals of several frequencies simultaneously required for different units of the information processing device are synthesized from the output signal of the first level MSS by several fractional-N second-level MSS, having a fractional modulus M equal to eight and using the fractional noise compensation claimed in this invention.

For example, when synthesizing a signal with a frequency of 166 MHz from a reference frequency of 32.768 kHz, an integer first-level integer is programmed in accordance with the expression:

$$F_{VCO\_\mathrm{one}}=5\mathrm{one}3\times 32.768\left[\mathrm{to}Gc\right]=\mathrm{one}6,80998\mathrm{four}\left[MGc\right].$$

Fractional-N MSS of the second level is programmed in accordance with the expression

$$F_{VCO\_2}=9\frac{7}{8}\times F_{VCO\_\mathrm{one}}=\mathrm{one}65,998592\left[MGc\right]$$

At the same time, the normalized installation error of the required frequency of 166 MHz is less than 8.5 × 10 ^-6 .

On figa and figb presents spectrograms of the output signal of the SF block of the MSS with a frequency of 166 MHz at a resolution of 1 MHz and 50 kHz per division, respectively. The spectral characteristics of the synthesized signal confirm the elimination of residual voltage ripple in the VCO control signal of the PLL fractional-N MSS of the second level.

In order to accelerate the transient processes of frequency self-tuning, the following algorithm for the operation of the ICPD and the control of the switching element can be used. If the ICPD scheme detects a phase difference of more than ± 2π radians, then the ICPD controls the ITNZ circuit so that the output current I0 is continuously generated. In this case, the switching element is constantly in a closed state. If the phase difference detected by the ICPD circuit is less than ± 2π radian, then the control shown in FIG. 5 is carried out.

Claims (1)

A frequency grid synthesizer including a pulse frequency-phase detector (ICPD) comparing the phase of the reference frequency signal and the phase of the feedback frequency signal and generating the first and second signals in accordance with the phase difference; a charge pump current source (TEC) generating an output current in accordance with the first and second output signals of the ICPD; a capacitive element connected to the output of ITNZ to form a third control signal; a switching element connected by the first output to the output of the ITNZ and controlled so that it is transferred to the open state when the ITNZ generates an output current; a control loop filter connected to a second terminal of the switching element and generating a fourth control signal based on the third control signal; a voltage controlled oscillator (VCO) generating an output signal with a frequency in accordance with a fourth control signal; a divider with a fractionally variable division coefficient (DDPKD), dividing the output frequency of the VCO in accordance with the fifth control signal and generating a feedback frequency signal; the control circuit of the value of the division coefficient in DDPKD, accumulating the value of the phase error caused by fractional division, and generating the fifth control signal; fractional current compensation source (ITKD) generating a current in accordance with the accumulated phase error value, characterized in that the ITKD output is connected to the ITNZ output, while the switching element is controlled so that for the time the ITKD output goes into active state, the switching element is switched to open state.

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