CN116667846B - Frequency synthesis circuit - Google Patents
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- CN116667846B CN116667846B CN202310958203.0A CN202310958203A CN116667846B CN 116667846 B CN116667846 B CN 116667846B CN 202310958203 A CN202310958203 A CN 202310958203A CN 116667846 B CN116667846 B CN 116667846B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The application provides a frequency synthesis circuit, including first signal generation module, second signal generation module, first frequency divider and second frequency divider, wherein: the first signal generation module is provided with a reference signal input end and a feedback signal input end, the output end of the first signal generation module is connected with the reference signal input end of the second signal generation module through the first frequency divider, and the output end of the second signal generation module is connected with the feedback signal input end of the first signal generation module to form a phase-locked loop; the output end of the second signal generating module is also connected with the feedback signal input end of the second signal generating module through the second frequency divider so as to form a sub phase-locked loop. The frequency synthesis circuit provided by the application can realize the fractional division ratio without using a differential integral modulator, so that quantization noise and fractional spurious are optimized.
Description
Technical Field
The application relates to the technical field of frequency synthesis, in particular to a frequency synthesis circuit.
Background
In order to achieve higher frequency resolution and stability in frequency synthesis circuits, output signals are often generated in a manner that produces Fractional-N frequency division ratios. The frequency synthesis is realized more accurately through tiny frequency adjustment, so as to meet the requirements on frequency precision and adjustment range.
A common process for manufacturing fractional division ratios is to incorporate a differential integral modulator (DSM, delta sigma modulator) into the frequency synthesis circuit, for example to obtain a differential integral modulation synthesizer as shown in fig. 1. But using a differential integral modulator to produce a fractional division ratio will produce quantization noise and will not eliminate fractional spurs around the dominant frequency.
Disclosure of Invention
In order to solve the above technical problems, embodiments of the present application provide a frequency synthesis circuit.
Other features and advantages of the present application will be apparent from the following detailed description, or may be learned in part by the practice of the application.
In a first aspect, an embodiment of the present application provides a frequency synthesis circuit, including a first signal generating module, a second signal generating module, a first frequency divider and a second frequency divider, where: the first signal generation module is provided with a reference signal input end and a feedback signal input end, the output end of the first signal generation module is connected with the reference signal input end of the second signal generation module through the first frequency divider, and the output end of the second signal generation module is connected with the feedback signal input end of the first signal generation module to form a phase-locked loop; the output end of the second signal generating module is also connected with the feedback signal input end of the second signal generating module through the second frequency divider so as to form a sub phase-locked loop.
In an embodiment of the present application, based on the foregoing solution, the first signal generating module and the second signal generating module respectively include a frequency adjusting module, a low-pass filter module, and a voltage-controlled oscillator module that are sequentially connected.
In one embodiment of the present application, based on the foregoing solution, the frequency adjustment module includes a phase frequency detector and a driving charge pump module; the driving charge pump module comprises a first charge pump, a first switch, a second switch and a second charge pump which are sequentially connected, wherein the first charge pump is provided with a power input end, and the output end of the second charge pump is grounded; the phase frequency detector is provided with a reference signal input end and a feedback signal input end and is used for comparing an input reference signal with a feedback signal and controlling whether the first switch and the second switch work or not according to a comparison result.
In one embodiment of the present application, based on the foregoing solution, when the signal frequency of the reference signal is greater than the signal frequency of the feedback signal, the first switch is controlled to be closed and the second switch is controlled to be opened, so that the driving charge pump module charges.
In one embodiment of the present application, based on the foregoing scheme, when the signal frequency of the reference signal is smaller than the signal frequency of the feedback signal, the first switch is controlled to be opened and the second switch is controlled to be closed, so that the driving charge pump module discharges.
In one embodiment of the present application, based on the foregoing scheme, when the signal frequency of the reference signal is equal to the signal frequency of the feedback signal, the first switch and the second switch are controlled to be closed so as to obtain an output signal in phase with the same frequency as the reference signal.
In an embodiment of the present application, based on the foregoing solution, a resistor, a first capacitor and a second capacitor are connected between an input end and an output end of the low-pass filter module, the resistor and the first capacitor are connected in series, the second capacitor is connected in parallel with the resistor and the first capacitor, and the first capacitor and the second capacitor are grounded respectively.
In one embodiment of the present application, based on the foregoing solution, the voltage-controlled oscillator module is configured to convert the voltage signal output by the low-pass filter module into a frequency signal.
In one embodiment of the present application, based on the foregoing scheme, an external reference signal is input to the phase-locked loop integrated circuit via a reference signal input terminal of the first signal generating module, and a signal frequency output by an output terminal of the first signal generating module is a product of the external reference signal and a frequency division ratio, where the frequency division ratio is a ratio of a frequency division factor of the first frequency divider to a frequency division factor of the second frequency divider.
In the technical scheme provided by the embodiment of the application, the frequency synthesis circuit comprises a first signal generation module, a second signal generation module, a first frequency divider and a second frequency divider, wherein the first signal generation module is provided with a reference signal input end and a feedback signal input end, the output end of the first signal generation module is connected with the reference signal input end of the second signal generation module through the first frequency divider, and the output end of the second signal generation module is connected with the feedback signal input end of the first signal generation module, so that a phase-locked loop is formed; the output end of the second signal generation module is connected with the input end of the second frequency divider, and the output end of the second frequency divider is connected with the feedback signal input end of the second signal generation module, so that a sub-phase-locked loop is formed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. It is apparent that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic diagram of a differential integral modulation synthesizer employed in the prior art.
Fig. 2 is a block diagram of a frequency synthesizer according to an exemplary embodiment of the present application.
Fig. 3 is a block diagram of a frequency synthesizer according to another exemplary embodiment of the present application.
Fig. 4 is a circuit diagram of a frequency synthesizer according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
The present application is described in further detail below with reference to the drawings and examples. It is specifically noted that the following examples are only for illustration of the present application, but do not limit the scope of the present application. Likewise, the following embodiments are only some, but not all, of the embodiments of the present application, and all other embodiments obtained by one of ordinary skill in the art without inventive effort are within the scope of the present application.
The terms first, second and the like in the description and in the claims of the present application and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented, for example, in sequences other than those illustrated or described herein. Furthermore, in the embodiments shown in the drawings, indications of direction (such as up, down, left, right, front and rear) are used to explain the structure and movement of the various elements of the present application are not absolute but relative. These descriptions are appropriate when these elements are in the positions shown in the drawings. If the description of the position of these elements changes, the indication of these directions changes accordingly. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Reference to "a plurality" in this application means two or more than two. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., a and/or B may represent: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
As previously mentioned, the prior art typically incorporates a differential integral modulator (DSM, delta sigma modulator) in the frequency synthesis circuit to produce the fractional division ratio according to a differential integral modulation synthesizer such as that shown in fig. 1, but using a differential integral modulator will produce quantization noise and will not eliminate fractional spurs around the dominant frequency.
In order to solve the problems of quantization noise and fractional spurious, the present application proposes a frequency synthesis circuit, and the scheme proposed in the present application will be described in detail below.
Referring to fig. 2, fig. 2 is a block diagram illustrating a frequency synthesizer according to an exemplary embodiment of the present application. As shown in fig. 2, the frequency synthesizer includes a first signal generation module 110, a first frequency divider 120, a second signal generation module 130, and a second frequency divider 140.
The first signal generating module 110 has a reference signal input and a feedback signal input, and the output of the first signal generating module 110 is connected to the first frequency divider 120, the first frequency divider 120 is also connected to the reference signal input of the second signal generating module 130, and the output of the second signal generating module 130 is connected to the feedback signal input of the first signal generating module 110, thereby forming a phase locked loop;
the output end of the second signal generating module 130 is connected to the input end of the second frequency divider 140, and the output end of the second frequency divider 140 is connected to the feedback signal input end of the second signal generating module 130, so as to form a sub phase-locked loop.
The functions of the first signal generating module 110, the first frequency divider 120, the second signal generating module 130, and the second frequency divider 140, and their roles will be described individually.
The first signal generating module 110 is provided with a reference signal input terminal for receiving the reference signal Fref from the outside and a feedback signal input terminal for receiving the feedback signal generated through the phase-locked loop. The first signal generating module is configured to compare the frequency and the phase of the reference signal Fref with those of the feedback signal, and convert an error signal obtained by the comparison to obtain an output signal Fout, which is not stable.
The first frequency divider 120 is configured to divide the frequency of the input signal into lower frequencies and divide the high frequency signal into lower frequency signals, where the division factor is an important parameter of the frequency divider and indicates the degree of division of the input frequency. For example, if the first frequency divider 120 is a divide-by-two or four divider, the division factor of the first frequency divider 120 corresponds to two or four, where the divide-by-two is represented as reducing the frequency of the output signal to half the frequency of the input signal.
The second signal generating module 130 has the same structure as the first signal generating module 110, and the second signal generating module 130 is configured to compare the reference signal output through the first frequency divider 120 with the feedback signal output through the second frequency divider 140, and convert an error signal obtained by the comparison into an output signal.
The second frequency divider 140 functions in the same way as the first frequency divider 120 to divide the frequency of the input signal into lower frequencies and to divide the high frequency signal into low frequency signals. For example, if the second frequency divider 140 is a six-divider or an eight-divider, the division factor of the second frequency divider 140 corresponds to six or eight, where the six-divider is represented as reducing the frequency of the output signal to one sixth of the frequency of the input signal.
It should be noted that, the second signal generating module 130 and the second frequency divider 140 form a sub-phase-locked loop, and the sub-phase-locked loop functions as a frequency multiplier in the loop. The frequency multiplier is used for multiplying the frequency of the input signal and increasing the low-frequency signal to the high-frequency signal, and the multiplication factor of the frequency multiplier has correlation with the frequency division factor of the second frequency divider, specifically, if the frequency division factor of the second frequency divider is 10, the multiplication factor of the frequency multiplier is 10, and if the frequency division factor of the second frequency divider is M, the multiplication factor of the frequency multiplier is M.
The external reference signal Fref is input to the phase-locked loop integrated circuit via the reference signal input terminal of the first signal generating module 110, and the frequency of the signal output by the output terminal of the first signal generating module 110 is the product of the external reference signal and the frequency dividing ratio, which is the ratio of the frequency dividing factor of the first frequency divider to the frequency dividing factor of the second frequency divider.
Assuming that the division factors of the first frequency divider 120 and the second frequency divider 140 are N and M, respectively, the desired division ratio can be determined by freely selecting the appropriate N and M, the magnitude of the division ratio is N/M, and by way of example, the first frequency divider with the division factor of n=101 is selected, and the second frequency divider with the division factor of m=10 is selected, so that the fractional division ratio with the division ratio of N/m=10.1 is obtained. The signal frequency Fout output by the output of the first signal generating module 110 is equal to the frequency division ratio N/M multiplied by the external reference signal Fref, fout=10.1 Fref.
Although the fractional frequency division ratio can be realized by the traditional fractional synthesizer, the fractional frequency division ratio is fixed and cannot be changed at will, so that the fractional frequency division ratio has no wide applicability, and the ideal frequency division ratio can be obtained by selecting a proper frequency division factor, so that the fractional frequency division ratio has good spurious performance.
Fig. 3 is a block diagram of a frequency synthesizer according to another exemplary embodiment of the present application. As shown in fig. 3, the first signal generating module 110 includes a frequency adjusting module 111, a low-pass filter module 112, and a voltage-controlled oscillator module 113, where an output end of the frequency adjusting module 111 is connected to an input end of the low-pass filter module 112, and an output end of the low-pass filter module 112 is connected to the voltage-controlled oscillator module 113. Similarly, the second signal generating module 130 includes a frequency adjusting module 131, a low-pass filter module 132, and a voltage-controlled oscillator module 133, where an output end of the frequency adjusting module 131 is connected to an input end of the low-pass filter module 132, and an output end of the low-pass filter module 132 is connected to the voltage-controlled oscillator module 133. The frequency adjustment module 111 and the frequency adjustment module 131, the low-pass filter module 112 and the low-pass filter module 132, and the voltage-controlled oscillator module 113 and the voltage-controlled oscillator module 133 are identical elements, respectively, and have the same structure.
The functions of the frequency adjustment module, the low-pass filter module and the voltage-controlled oscillator module and their roles will be described one by one.
The frequency adjustment module 111 is configured to measure the frequency and phase of the reference signal Fref, compare the frequency and phase with the feedback signal, and adjust the generated error signal to ensure that the reference signal and the feedback signal are in phase with each other at the same frequency by detecting and comparing the phase and frequency difference between the reference signal Fref and the feedback signal.
The frequency adjustment module 131 is configured to measure the reference signal output through the first frequency divider 120, compare the reference signal with the feedback signal output through the second frequency divider 140, and adjust the generated error signal to ensure that the reference signal is in phase with the feedback signal.
The low-pass filter module 112 and the low-pass filter module 132 are respectively configured to remove high-frequency noise and spurious components in the output signals output by the frequency adjustment module 111 and the frequency adjustment module 131, and only allow signals of a low-frequency part to filter the high-frequency noise in a filtering manner, so that the output signals are smoother and more stable.
The voltage-controlled oscillator module 113 and the voltage-controlled oscillator module 133 are used for providing stable output signals, and the frequency of the output signals can be adjusted according to the requirement; and is responsible for generating a feedback signal for comparison by the frequency adjustment module to form a feedback closed loop control.
Fig. 4 is a circuit diagram of a frequency synthesizer according to an exemplary embodiment of the present application, as shown in fig. 4, wherein the frequency adjustment module 111 and the frequency adjustment module 131 each include a phase frequency detector and a driving charge pump module.
The phase frequency detector is provided with a reference signal input end and a feedback signal input end, in the driving charge pump module, a first charge pump is connected with the power input end, the output end of the first charge pump is sequentially connected with a first switch and a second switch, and the input end and the output end of the second charge pump are respectively connected with the second switch and the ground. The output end of the phase frequency detector is respectively connected with a first switch and a second switch which drive the charge pump module.
The functions of the phase frequency detector and the driving charge pump and their actions will be described individually.
The phase frequency detector is used for measuring the frequency and the phase of an external reference signal Fref, comparing the frequency and the phase with a feedback signal, and controlling whether the first switch and the second switch work or not, namely controlling the switch to be opened or closed or not according to the comparison result. The output signal of the phase frequency detector module is used for adjusting the working frequency and the phase of the subsequent module so as to ensure that the output signal is synchronous with the feedback signal. The charge pump is driven to change the charge and discharge states of the capacitor, so that the voltage boosting or the voltage reducing conversion is realized.
When the signal frequency of the reference signal is greater than the signal frequency of the feedback signal, the first switch is controlled to be closed and the second switch is controlled to be opened, and the charge pump module is driven to be charged so as to improve the signal frequency of the feedback signal.
When the signal frequency of the reference signal is smaller than the signal frequency of the feedback signal, the first switch is controlled to be opened and the second switch is controlled to be closed, and the driving charge pump module is discharged to reduce the signal frequency of the feedback signal.
When the signal frequency of the reference signal is equal to the signal frequency of the feedback signal, the first switch and the second switch are controlled to be closed, so that the electric charge in the power supply directly flows to the ground, thereby having no influence on the feedback signal, and a stable output signal with the same frequency and the same phase as the reference signal is obtained.
In the low-pass filter module 112 and the low-pass filter module 132, a resistor, a first capacitor and a second capacitor are connected between an input end and an output end of the low-pass filter module, wherein the resistor and the first capacitor are connected in series, the second capacitor is connected in parallel with the resistor and the first capacitor, and the first capacitor and the second capacitor are respectively grounded.
The function of the resistor, the first capacitor and the second capacitor and their roles will be described individually.
The resistors in the low-pass filter module can influence the cut-off frequency of the low-pass filter module, the cut-off frequency is a characteristic parameter of the filter, the frequency of an input signal is determined to be suppressed, a larger resistor value can generate a lower cut-off frequency, a smaller resistor value can generate a higher cut-off frequency, and the filtering characteristic of the low-pass filter module in a frequency domain can be adjusted by selecting a proper resistor value. In addition, the oscillation of the frequency integrated circuit can be restrained, and the stability and the reliability of the frequency integrated circuit are improved. The first capacitor and the second capacitor can receive charges, the function of controlling frequency is achieved in the low-pass filter module, high-frequency signals can be filtered, signal components in lower frequency bands can be reserved, and the low-pass filter module can remove unwanted high-frequency noise and rapidly-changing signals through combination of the resistor, the first capacitor and the second capacitor, so that smoother and stable output voltage signals are provided.
The voltage-controlled oscillator module 113 is configured to convert the voltage signal output by the low-pass filter module 112 into a frequency signal, and then pass through the first frequency divider after converting the voltage signal into the frequency signal to reduce the frequency of the frequency signal.
The voltage-controlled oscillator module 133 is configured to convert the voltage signal output by the low-pass filter module 132 into a frequency signal, and then pass through the second frequency divider to reduce the frequency of the frequency signal after converting the voltage signal into the frequency signal.
In summary, the frequency synthesis circuits shown in the embodiments of the present application can implement the fractional division ratio without using a differential integral modulator, so as to optimize quantization noise and fractional spurious.
The foregoing is merely a preferred exemplary embodiment of the present application and is not intended to limit the embodiments of the present application, and those skilled in the art may make various changes and modifications according to the main concept and spirit of the present application, so that the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (7)
1. The utility model provides a frequency integrated circuit, its characterized in that includes first signal generation module, second signal generation module, first frequency divider and second frequency divider, first signal generation module with second signal generation module includes frequency adjustment module, low pass filter module and the voltage controlled oscillator module that links to each other in proper order respectively, frequency adjustment module includes phase frequency detector and drive charge pump module, wherein:
the first signal generation module is provided with a reference signal input end and a feedback signal input end, the output end of the first signal generation module is connected with the reference signal input end of the second signal generation module through the first frequency divider, and the output end of the second signal generation module is connected with the feedback signal input end of the first signal generation module to form a phase-locked loop;
the output end of the second signal generation module is also connected with the feedback signal input end of the second signal generation module through the second frequency divider so as to form a sub phase-locked loop;
the driving charge pump module comprises a first charge pump, a first switch, a second switch and a second charge pump which are sequentially connected, wherein the first charge pump is provided with a power input end, and the output end of the second charge pump is grounded;
the phase frequency detector is provided with a reference signal input end and a feedback signal input end and is used for measuring the frequency and the phase of the reference signal, comparing the reference signal with the feedback signal and controlling the first switch and the second switch to work according to the comparison result.
2. The frequency synthesis circuit of claim 1, wherein when the signal frequency of the reference signal is greater than the signal frequency of the feedback signal, the first switch is controlled to be closed and the second switch is controlled to be opened, so that the driving charge pump module charges.
3. The frequency synthesis circuit of claim 1, wherein when the signal frequency of the reference signal is less than the signal frequency of the feedback signal, the first switch is controlled to open and the second switch is controlled to close, causing the driving charge pump module to discharge.
4. The frequency synthesis circuit according to claim 1, wherein the first switch and the second switch are controlled to be closed when the signal frequency of the reference signal is equal to the signal frequency of the feedback signal, so as to obtain an output signal in phase with the same frequency as the reference signal.
5. The frequency synthesis circuit according to claim 4, wherein a resistor, a first capacitor and a second capacitor are connected between the input terminal and the output terminal of the low-pass filter module, the resistor and the first capacitor are connected in series, the second capacitor is connected in parallel with the resistor and the first capacitor, and the first capacitor and the second capacitor are respectively grounded.
6. The frequency synthesis circuit according to claim 5, wherein the voltage controlled oscillator module is configured to convert the voltage signal output by the low pass filter module into a frequency signal.
7. The frequency synthesis circuit according to claim 1, wherein an external reference signal is input to the phase-locked loop synthesis circuit via a reference signal input of the first signal generation module, and a frequency of a signal output by an output of the first signal generation module is a product of the external reference signal and a division ratio, the division ratio being a ratio of a division factor of the first frequency divider to a division factor of the second frequency divider.
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| CN101783680A (en) * | 2009-12-30 | 2010-07-21 | 上海迦美信芯通讯技术有限公司 | Frequency synthesizer and calibration method thereof |
| CN102158227A (en) * | 2010-02-11 | 2011-08-17 | 奇景光电股份有限公司 | Non-integer N type phase-locked loop |
| CN204425319U (en) * | 2015-03-26 | 2015-06-24 | 成都爱洁隆信息技术有限公司 | The fractional frequency division frequency synthesizer with charge pump linearization technique is compensated with DAC |
| CN109818612A (en) * | 2019-01-10 | 2019-05-28 | 复旦大学 | A kind of frequency source applied to millimeter-wave communication system |
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