CN102158227B - Non-Integer-N Phase-Locked Loop - Google Patents

Abstract

The present invention relates to a non-integer N-type phase-locked loop, which includes a phase detector (PD), a voltage-controlled oscillator (VCO), a frequency divider (FD) and a frequency multiplier, wherein the frequency multiplier has a frequency multiplication coefficient in a fractional form. The phase detector compares a reference voltage and a phase difference between a frequency-divided signal output by the frequency divider, the voltage-controlled oscillator generates an output frequency according to the phase difference, and the frequency multiplier then multiplies the output frequency to generate a multiplied signal. The frequency multiplier includes a second phase-locked loop, thereby generating a second loop. The frequency divider divides the multiplied signal to generate a frequency-divided signal. The phase detector compares the frequency-divided signal with the reference frequency to determine the phase difference.

Description

Non-Integer-N Phase-Locked Loop

technical field

The invention relates to a phase-locked loop, in particular to a nested non-integer N-type phase-locked loop.

Background technique

A phase-locked loop (PLL) is a control circuit that uses negative feedback to lock the phase of an output frequency to a reference frequency. Phase-locked loops are widely used in various applications, such as synthesizing a stable frequency or recovering signals from communication channels. The ratio of the output frequency of the phase-locked loop to the reference frequency can be an integer, or an integer plus a fractional fraction. The former is usually called an integer-N phase-locked loop/synthesizer (integer-N PLL/synthesizer), and the latter The latter is usually called a fractional-N PLL/synthesizer. Among various types of non-integer N-type synthesizers, a delta-sigma synthesizer (delta-sigma synthesizer) with a delta-sigma (delta-sigma modulator, SDM) is often used. However, the quantization noise generated by the delta-sigma modulator will cause the phenomenon of output clock jitter (clock jitter). In order to slow down the clock jitter, a capacitor with a large capacitance (for example more than several thousand picofarads (pF)) is used to filter out the quantization error, thus resulting in an increase in circuit area and power consumption.

In view of the fact that the existing phase-locked loop cannot effectively reduce the clock jitter of the delta-sigma synthesizer, it is urgent to propose a new architecture that can efficiently filter out the quantization error without increasing the circuit area.

Contents of the invention

In view of the above-mentioned background of the invention, the purpose of the embodiments of the present invention is to provide a non-integer N-type phase-locked loop, which can efficiently filter quantization errors without using too large a capacitor.

According to an embodiment of the present invention, a fractional-N phase-locked loop (fractional-N PLL) includes a first phase-locked loop and a second phase-locked loop. In the first phase-locked loop, a first phase detector (phase detector) compares a first phase difference and generates a first error signal to represent the first phase difference. A first voltage-controlled oscillator (VCO) generates an output frequency according to a first error signal. A frequency multiplier multiplies the output frequency to generate a frequency multiplied signal, and the frequency multiplier includes a second phase-locked loop forming a second loop. A first frequency divider (frequency divider) divides the frequency multiplied signal to generate a first frequency divided signal. The first frequency-divided signal is compared with a reference frequency by the first phase detector to determine the first phase difference. In a specific embodiment, the bandwidth of the second phase-locked loop of the frequency multiplier is greater than the bandwidth of the first phase-locked loop.

Description of drawings

FIG. 1 is a functional block diagram of a specific embodiment of a non-integral N-type PLL disclosed in the present invention.

FIG. 2 is a schematic diagram of a system architecture of a specific embodiment of a nested PLL disclosed in the present invention.

FIG. 3 is a specific embodiment of an exemplary implementation circuit with design parameters disclosed in the present invention.

[Description of main component symbols]

1 phase locked loop

10, 150 phase detector

11,151 charge pump

12, 152 loop filter

13, 153 voltage controlled oscillator

14, 154 frequency divider

15 frequency multiplier

155 delta-sigma modulator

f _r reference frequency

f _out output frequency

Detailed ways

First, please refer to FIG. 1 , which is a functional block diagram of a specific embodiment of a non-integral N-type PLL 1 disclosed by the present invention.

In this embodiment, the phase-locked loop 1 includes a phase detector (phase detector, PD) 10, a charge pump (Charge Pump, CP) 11, a loop filter (Loop Filter, LF) 12, a voltage-controlled oscillator (Voltage- Controlled Oscillator (VCO) 13 , Frequency Divider (Frequency Divider, FD) 14 and Frequency Multiplier (frequency multiplier) 15 . Specifically, the phase detector 10 is preferably a phase/frequency detector (phase frequency detector, PFD), which is used to compare the phase difference between the reference frequency f _r and the frequency-divided signal output by the frequency divider 14 to generate a The error signal represents the phase difference between the two frequencies. The charge pump 11 controls a charge pump current according to the error signal output by the phase detector 10 . The loop filter 12 can be a low-pass filter (low-pass filter) used to smooth the output of the charge pump 11 to generate a filtered signal and send it to the voltage-controlled oscillator 13, and the loop filter 12 can include a resistor Capacitor circuit (RC circuit). The voltage controlled oscillator 13 is used to generate an output frequency f _out which is proportional to the filtered signal or indirectly generated according to the error signal output by the phase detector ₁₀ . The frequency multiplier 15 multiplies the output frequency f _out to generate a multiplied signal. In this embodiment, the frequency multiplication coefficient of the frequency multiplier 15 is a banded fraction, that is, an integer M plus a fraction F. The frequency divider 14 is used to divide the frequency multiplied signal to generate a frequency divided signal. In this embodiment, the frequency division coefficient of the frequency divider 14 is an integer N. It should be noted that, in the PLL 1, all blocks except the frequency multiplier 15 can be implemented using common PLL technology.

Next, please refer to FIG. 2 , which is a schematic diagram of the system architecture of a specific embodiment of the nested PLL disclosed in the present invention. Please also refer to Figure 3 for an example implementation circuit with design parameters. As shown in FIG. 2 , the frequency multiplier 15 can be implemented by a phase-locked loop architecture. The frequency multiplier 15 includes a phase detector (PD) 150, a charge pump (CP) 151, a loop filter (LF) 152, a voltage-controlled oscillator (VCO) 153, and a frequency divider 154, wherein the divider The frequency converter 154 has a frequency division factor whose value is (M+F); the voltage controlled oscillator (VCO) 153 generates a multiplied frequency signal according to the filtered signal output by the loop filter (LF) 152 . The functions and structures of the above-mentioned blocks 151-154 are similar to the blocks 11-14, so details thereof will not be repeated. In particular, the phase detector 150 is used to compare the phase difference between the output frequency f _out and the frequency-divided signal output by the frequency divider 154 . In addition, the delta sigma modulator (SDM) 155 provides the fraction F to the frequency divider 154 according to the frequency division signal of the frequency divider 154 . In this specification, "first" can be added before components such as phase detector 10, charge pump 11, loop filter 12, voltage-controlled oscillator 13, frequency divider 14 and related signals; and phase detector 150, "Second" can be added before components such as the charge pump 151, the loop filter 152, the voltage-controlled oscillator 153, the frequency divider 154 and their related signals to facilitate distinction.

According to the architecture shown in FIG. 2 , a kind of multi-loop or nested PLL is thus formed. Although the present embodiment only uses a phase-locked loop with two layers of loops as an example, a phase-locked loop (multi-loop PLL) with more than two layers of loops can of course be implemented with the same concept, so the disclosed one is not taken as an example. limit. In this embodiment, the VCO gain (VCO gain) (for example 360MHz/v) of the VCO 13 of the first loop (or main loop) of the phase-locked loop is smaller than that of the second loop of the frequency multiplier 15. The VCO gain of the VCO 153 (eg, 1640 MHz/v). The bandwidth of the first loop is smaller than that of the second loop, so the operation speed of the second loop is faster than that of the first loop. Therefore, the second loop first filters out the quantization error generated by the delta-sigma modulator (SDM) 155 , and then the first loop with a narrower bandwidth further filters out the quantization error.

According to the above-mentioned embodiments, compared with the traditional PLL, the nested non-integer N-type PLL can filter the quantization error more efficiently, thereby reducing the jitter of the output clock. It should be noted that the capacitance value of the capacitor used in the nested non-integer N-type PLL is smaller than that used in the traditional PLL. For example, as shown in FIG. 3 , a capacitor with a capacitance of 273pF is sufficient to filter the quantization error, thus, the circuit area and power consumption of the nested non-integer N-type PLL can be reduced practically.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention; all other equivalent changes or modifications that do not deviate from the spirit disclosed by the invention should be included in the following applications within the scope of the patent.

Claims (8)

1. A non-integer N-type phase-locked loop, comprising: a first phase detector for comparing a first phase difference to generate a first error signal to represent the first phase difference; a first voltage-controlled oscillator, which generates an output frequency according to the first error signal; a frequency multiplier, which multiplies the output frequency to generate a frequency multiplied signal, the frequency multiplier comprising a second phase-locked loop, thereby forming a second loop; and A first frequency divider, which divides the frequency-multiplied signal to generate a first frequency-divided signal, wherein the first frequency-divided signal is compared with a reference frequency by the first phase detector to determine the first phase difference; Wherein, the first phase detector, the first voltage-controlled oscillator, the frequency multiplier and the first frequency divider form a first loop; Wherein the second phase-locked loop includes: a second phase detector for comparing a second phase difference to generate a second error signal to represent the second phase difference; a second charge pump, which controls a second charge pump current according to the second error signal output by the second phase detector; a second loop filter for smoothing the output of the second charge pump to generate a second filtered signal; a second voltage controlled oscillator, which generates the multiplied frequency signal according to the second filtered signal; and a second frequency divider for dividing the frequency-multiplied signal to generate a second frequency-divided signal, wherein the second frequency-divided signal is compared with the output frequency by the second phase detector, to determine the second phase difference; and Wherein the non-integer N-type phase-locked loop further includes a delta-sigma modulator, which provides fractional values of frequency multiplication coefficients according to the second frequency-divided signal. 2. The non-integer-N phase-locked loop as claimed in claim 1, wherein the bandwidth of the second loop is greater than the bandwidth of the first loop. 3. The non-integer-N phase-locked loop as claimed in claim 1, wherein the operation speed of the second loop is faster than that of the first loop. 4. The non-integer-N PLL as claimed in claim 1, wherein the first phase detector is a phase/frequency detector. 5. The non-integer-N phase-locked loop as claimed in claim 1, further comprising a first charge pump for controlling a first charge pump current according to the first error signal output by the first phase detector. 6. The non-integer-N phase-locked loop as claimed in claim 5, further comprising a first loop filter for smoothing the output of the first charge pump to generate a first filtered signal, wherein the first filtered The signal is further transmitted to the first VCO. 7. The non-integer-N phase-locked loop as claimed in claim 6, wherein the first loop filter is a low-pass filter. 8. The non-integer-N phase-locked loop as claimed in claim 7, wherein the first loop filter comprises a resistor-capacitor circuit (RC circuit).

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