CN1241325A - Multichannel radio device, radio communication system, and fractional division frequency synthesizer - Google Patents
Multichannel radio device, radio communication system, and fractional division frequency synthesizer Download PDFInfo
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- CN1241325A CN1241325A CN98801515A CN98801515A CN1241325A CN 1241325 A CN1241325 A CN 1241325A CN 98801515 A CN98801515 A CN 98801515A CN 98801515 A CN98801515 A CN 98801515A CN 1241325 A CN1241325 A CN 1241325A
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- frequency
- phase discriminator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
- H03L7/235—Nested phase locked loops
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
Abstract
Known are fractional division synthesizers for multichannel radio devices. A new architecture for such a type of synthesizer is proposed not having the drawbacks of such known synthesizers and having the same phase noise properties as ordinary integer divide by N synthesizers. The novel architecture has a main PLL with a first integer frequency divider in its feedback loop and further an auxiliary PLL having a second integer frequency divider in its feedback loop.
Description
The present invention relates to multichannel radio device.Such multichannel radio device can be a radio communication device, for example honeycomb or cordless telephone, pager, or any multichannel radio device that other is fit to.
The invention still further relates to wireless communication system, and fractional division frequency synthesizer.
RF (radio frequency) frequency synthesizer is used in, for example, and the multichannel radio device that in wireless communication system, uses.In such system, used multichannel receiver or transceiver, comprise the RF frequency synthesizer, it may be tuned to a plurality of channels.Like this tuning should be fast, because wireless device should switch to another wireless channel apace from a wireless channel.And wireless device should cause as far as possible little adjacent-channel interference.For this reason, aspect the spectral purity and its setting-up time of its output signal, should high requirement be proposed for the frequency synthesizer that in such wireless device, uses.Usually know that frequency synthesizer has the structure of frequency multiplier, for example at handbook " The Art of Electronics (electronic technology) ", P.Horowitz et al., Cambridge University Press, p.432, described in 1980.In such synthesizer,, for example, be the multiple of the stable reference frequency that produces by crystal oscillator from the output signal of VCO (voltage controlled oscillator).The integer frequency ratio frequency divider is the output signal frequency division, and the output of frequency divider is fed back to phase discriminator, and reference signal also is fed to phase discriminator simultaneously.Loop filter carries out filtering to the output of phase discriminator, and the signal controlling that is low pass filtering VCO.Such loop is PLL basically, has integer frequency divider in its feedback path.In communicator, reference frequency is selected as equaling channel spacing.Yet because the common little bandwidth of loop filter, the setting-up time of such synthesizer is relatively large, and like this, synthesizer speed is slower.In order to overcome this problem, fractional division frequency synthesizer has been proposed.At handbook " Digital PLL Frequency Synthesizers (digital PLL frequency synthesizer) ", U.L.Rohde, pp.124-141, Prentice-Hall, 1983, such fractional-N synthesizer has been described, N is a mark.Because higher reference frequency can be used, therefore can obtain in principle than common integral frequency divisioil synthesizer more performance, such fraction N frequency comprehensive device still has sizable shortcoming.In order to reach fraction division, the normal time when the output of phase discriminator arrives set-point removed the pulse that feeds back to frequency divider from VCO in the interval by the pulse remover.The result is to be replaced by the frequency division divided by N+1 divided by the frequency division of N.The frequency division that replaces like this causes undesired sideband in the output signal of synthesizer.Structure with high complexity is a cost, thus, by means of the digital-analog convertor that is coupled to accumulator, has produced a signal, and it is deducted from the output signal of phase discriminator, attempts to offset undesired sideband.For such mark-Fractional-N frequency frequency synthesizer more detailed description, can be with reference to application guide AN1891, " SA 8025 Fractional-N Frequency synthesis (SA8025 fractional-N frequency synthesis) ", Philips Semiconductors, 18 Sep 1994.In paper " delta sigma Modulation in Fractional-N Frequency Synthesis (the delta sigma modulation in the fractional-N frequency synthesis) ", T.A.D.Riley et al., IEEEjournal of Solid State Circuits, Vol.28, No.5, among the pp.553-559, the delta sigma modulator is used in mark-Fractional-N frequency frequency synthesizer noise-shaping is carried out in phase jitter.Such structure is complicated.Two kinds of mark-Fractional-N frequency frequency synthesizers all have shortcoming.There is the phase noise of expectation still much higher than common integral frequency divisioil frequency synthesizer.And, need outside the adjusting usually, so that the compensate for residual result.Because in two types marks-N synthesizer, need high speed circuit, so power consumption is being quite significant such as digital-analog convertor and the such digital circuit of delta sigma modulator.Quite high power consumption like this is undesired especially in mobile phone, in mobile phone, wishes standby and call time long as far as possible before running down of battery.High complexity also causes bigger chip, it seems that from the viewpoint and the high integrated level of hope of cost this is undesired.
An object of the present invention is to provide a kind of radio communication device, the fractional-n frequency synthesis that it comprises has high performance, simple structure simultaneously, and do not have the shortcoming of known mark-Fractional-N frequency synthesizer.
For this reason, fractional-n frequency synthesis is provided, particularly when it is included in multichannel radio device, this synthesizer has output signal at the synthesizer output, its frequency is the fractional multiple of the reference frequency that produced by the reference frequency generator, this synthesizer includes the forward path between reference and described output, it comprises first phase discriminator, the cascade of first loop filter and first voltage controlled oscillator, thus, the first input end of first phase discriminator is coupled to reference edge, this synthesizer also includes the feedback path between second input of the described output and first phase discriminator, it comprises first frequency divider, second phase discriminator, the cascade of second loop filter and second voltage controlled oscillator, thus, the output that the output of second voltage controlled oscillator is coupled to second input of first phase discriminator and first frequency divider is coupled to the first input end of second phase discriminator, and this synthesizer comprises second frequency divider, its input is coupled to second input of first phase discriminator, its output is coupled to second input of second phase discriminator, thus, the frequency dividing ratio of first and second frequency dividers is integers.The present invention based on viewpoint be, although use utmost point simple structure, still can only use integer frequency divider to obtain mark-Fractional-N frequency synthesizer.The surprising diverse notion of such mark-Fractional-N frequency frequency synthesizer has advantage, and its phase noise is the same low with the phase noise of ordinary integer Fractional-N frequency synthesizer.And, because auxiliary PLL by accurately divided by M/N, M is that the integer divisor and the N of first frequency divider is the integer divisor of second frequency divider, so can not produce undesired parasitic frequency.In addition, because the phase noise of second voltage controlled oscillator is suppressed by first loop filter of main PLL, so second voltage controlled oscillator can easily be integrated among the IC (integrated circuit).Because open-and-shut structure obtains low power consumption, also have little chip area and low-cost design and exploitation.When using BiCMOS or short channel CMOS technology, complete synthesizer can easily be integrated in the integrated circuit.
In claim 2-4, the various embodiment of the fractional-n frequency synthesis in multichannel radio device has been proposed.In claim 2, proposing frequency divider is pre-divider.The preferably technical so-called bimodulus piece pre-divider of knowing of such pre-divider, it has two parameters able to programme.In claim 3, such controllability has been proposed.Thus, the output frequency of any fractional multiple as input reference frequency all can be by comprehensively.
By example the present invention is described referring now to accompanying drawing.
Fig. 1 schematically shows the wireless communication system that has according to multichannel radio device of the present invention, and
Fig. 2 has shown the block diagram according to fractional-n frequency synthesis of the present invention.
On all figure, identical reference number is used for identical characteristic.
Fig. 1 schematically shows the wireless communication system that has according to multichannel radio device 2 of the present invention and 3.Such system can be a cellular wireless system, and for example GSM (FD/TDMA system) has the cdma system in conjunction with the channel of sign indicating number branch, cordless telephone system, and as the DECT system, paging system is as FLEX
TMSystem, or any multiple channel wireless system that other is fit to.This system also comprises wireless base station 4, and it can be communicated by letter with 3 with wireless device 2.Such wireless base station 2 comprises RF receiver branch 5 and RF transmitter branch 6, and the two all passes through duplexer or transmit-receive switch 8 is coupled to antenna 7.Receiver branch 5 comprises that with the down-conversion device of the form of frequency mixer 9 and frequency synthesizer 10, it can be according to fractional-n frequency synthesis of the present invention.RX path 5 also comprises the low noise RF amplifier 11 that is coupled to receiving filter 12.Synthesizer 10 provides local oscillator frequencies f
LOInput to frequency mixer 9.The output of frequency mixer 9 is fed to another mixer stage or modulator (not being shown specifically) here.Transmission path 6 comprises frequency mixer 13, is coupled to RF power amplifier 14 from its input, and its is coupled to duplexer 8 through emission filter 15.Frequency synthesizer 16 provides carrier frequency f
cGive frequency mixer 16.The data that are sent out are provided to the input of frequency mixer 13.Wireless device 2 comprises microcontroller 17, and it is programmed and is submitted to synthesizer 10 and 16 adjusting data, so that adjust their frequency.Similarly, wireless device 3 comprises frequency mixer 20, power amplifier 21, emission filter 22, duplexer 23, antenna 24, low noise amplifier 25, receiving filter 26, frequency mixer 27 and synthesizer 28.
Fig. 2 has shown the block diagram according to fractional-n frequency synthesis 10 of the present invention.Synthesizer 10 has output 30, has on it to have output frequency f
0Output signal, and have input, on it by feedback to have reference frequency f
RefReference signal.Reference frequency f
RefProduce (not being shown specifically on the figure), for example crystal or quartz (controlled) oscillator by the reference generator.Output frequency f
0Be reference frequency f
RefFractional multiple.Fractional-n frequency synthesis 10 is included in the forward path between input 31 and the output 32, and it comprises the first phase discriminator PD
1, the first loop filter LF
1, low pass filter normally is with first voltage controlled oscillator VCO
1Cascade.The first phase discriminator PD
1First input end be coupled to input 31.Synthesizer 10 also includes at the output 30 and the first phase discriminator PD
1 Second input 33 between feedback path, it comprises first frequency divider 34, the second phase discriminator PD with integer frequency ratio M
2, the second loop filter LF
2, low pass filter normally is with second voltage controlled oscillator VCO
2Cascade.At output, oscillator VCO
2Be coupled to the first phase discriminator PD
1Second input 33.The output 35 of first frequency divider 34 is coupled to the second phase discriminator PD
2First input end 36.Synthesizer 10 also comprises second frequency divider 37 with integer frequency ratio N, and its input 38 is coupled to the first phase discriminator PD
1 Second input 33, its output 39 is coupled to the second phase discriminator PD
2Second input 40.In one embodiment, frequency divider 34 and 37 is technical so-called bimodulus piece pre-dividers of knowing.In this embodiment, frequency divider comprises the P/P+1 counter, and its frequency dividing ratio can switch to P+1 or conversely, downward counter Q able to programme and downward counter R able to programme from P by control signal ct1.Downward counter Q able to programme and R are available.If counter count down to zero downwards from its preset value downwards, then the output of counter changes to another logical value from a logical value, for example change to logic low from logic high, and unison counter is loaded the preset value with it.Microcontroller 17 can change preset value, so Q can be set and R is any numerical value.Such pre-divider has total frequency dividing ratio of M=QP+R.Similarly, frequency divider or pre-divider 37 comprise the S/S+1 counter, downward counter T able to programme and downward counter U able to programme.Frequency divider 37 has total frequency dividing ratio of N=TS+U.But for the principle reference manual " " of so double mode pre-divider, R.E.Best, McGraw-Hill, pp.139 and 143-145,1993, second edition.At the 139th page, in Fig. 3 .22 (d), provided the block diagram of such bimodulus piece pre-divider.According to fractional divider of the present invention, frequency divider also can be implemented as 4-module pre-divider, or the frequency divider of any other adequate types.In given embodiment, like this, as the I/O relation of fractional division frequency synthesizer 10, following relation remains: f
0=(QP+R)/(TS+U) f
Ref
It seems from above-mentioned content, for those skilled in the art will be obviously can as after this in the spirit and scope of the present invention by the appended claims defined, make various correction, thereby the example that provided is provided in the present invention.
Claims (6)
1. multichannel radio device comprises at least one the RF-receiver branch that is used to receive wireless signal that is coupled to antenna, this receiver branch comprises down-conversion device that is used for the wireless signal that down-conversion receives and the fractional-n frequency synthesis that is included in down-conversion device, this synthesizer has output signal at the synthesizer output, it is used to the wireless signal that down-conversion receives, output signal frequency is the fractional multiple of the reference frequency that produced by the reference frequency generator, this synthesizer includes the forward path between reference source and described output, it comprises first phase discriminator, the cascade of first loop filter and first voltage controlled oscillator, thus, the first input end of first phase discriminator is coupled to reference source, this synthesizer also includes the feedback path between second input of the described output and first phase discriminator, it comprises first frequency divider, second phase discriminator, the cascade of second loop filter and second voltage controlled oscillator, thus, the output that the output of second voltage controlled oscillator is coupled to second input of first phase discriminator and first frequency divider is coupled to the first input end of second phase discriminator, and this synthesizer comprises second frequency divider, its input is coupled to second input of first phase discriminator, its output is coupled to second input of second phase discriminator, thus, the frequency dividing ratio of first and second frequency dividers is integers.
2. as the desired wireless device of claim 1, it is characterized in that wherein at least one frequency divider is a pre-divider.
3. as claim 1 and 2 desired wireless devices, it is characterized in that wherein frequency dividing ratio is adjustable.
4. as claim 1,2, or 3 desired wireless devices, it is characterized in that, also comprise the RF-emission branch that is coupled to antenna.
5. wireless communication system, comprise at least one multichannel radio device, it comprises that multichannel radio device comprises at least one the RF-receiver branch that is used to receive wireless signal that is coupled to antenna, this receiver branch comprises down-conversion device that is used for the wireless signal that down-conversion receives and the fractional-n frequency synthesis that is included in down-conversion device, this synthesizer has output signal at the synthesizer output, it is used to the wireless signal that down-conversion receives, output signal frequency is the fractional multiple of the reference frequency that produced by the reference frequency generator, this synthesizer includes the forward path between reference source and described output, it comprises first phase discriminator, the cascade of first loop filter and first voltage controlled oscillator, thus, the first input end of first phase discriminator is coupled to reference source, this synthesizer also includes the feedback path between second input of the described output and first phase discriminator, it comprises first frequency divider, second phase discriminator, the cascade of second loop filter and second voltage controlled oscillator, thus, the output that the output of second voltage controlled oscillator is coupled to second input of first phase discriminator and first frequency divider is coupled to the first input end of second phase discriminator, and this synthesizer comprises second frequency divider, its input is coupled to second input of first phase discriminator, its output is coupled to second input of second phase discriminator, thus, the frequency dividing ratio of first and second frequency dividers is integers.
6. fractional-n frequency synthesis, this synthesizer has output signal at the synthesizer output, the frequency that it has is the fractional multiple of the reference frequency that produced by the reference frequency generator, this synthesizer includes the forward path between reference source and described output, it comprises first phase discriminator, the cascade of first loop filter and first voltage controlled oscillator, thus, the first input end of first phase discriminator is coupled to reference source, this synthesizer also includes the feedback path between second input of the described output and first phase discriminator, it comprises first frequency divider, second phase discriminator, the cascade of second loop filter and second voltage controlled oscillator, thus, the output that the output of second voltage controlled oscillator is coupled to second input of first phase discriminator and first frequency divider is coupled to the first input end of second phase discriminator, and this synthesizer comprises second frequency divider, its input is coupled to second input of first phase discriminator, its output is coupled to second input of second phase discriminator, thus, the frequency dividing ratio of first and second frequency dividers is integers.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP97202491 | 1997-08-12 | ||
| EP97202491.3 | 1997-08-12 | ||
| PCT/IB1998/001081 WO1999008384A2 (en) | 1997-08-12 | 1998-07-16 | Multichannel radio device, a radio communication system, and a fractional division frequency synthesizer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1241325A true CN1241325A (en) | 2000-01-12 |
Family
ID=8228637
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN98801515A Pending CN1241325A (en) | 1997-08-12 | 1998-07-16 | Multichannel radio device, radio communication system, and fractional division frequency synthesizer |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0943180A1 (en) |
| JP (1) | JP2001502157A (en) |
| KR (1) | KR20000068744A (en) |
| CN (1) | CN1241325A (en) |
| WO (1) | WO1999008384A2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158227A (en) * | 2010-02-11 | 2011-08-17 | 奇景光电股份有限公司 | Non-integer N type phase-locked loop |
| CN109104185A (en) * | 2017-06-21 | 2018-12-28 | 三星电子株式会社 | The operating method of digital phase-locked loop and digital phase-locked loop |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NZ507556A (en) * | 1999-04-14 | 2002-10-25 | Tait Electronics Ltd | Phase lock loop frequency synthesis controller includes digital modulator |
| US6198354B1 (en) * | 1999-12-07 | 2001-03-06 | Hughes Electronics Corporation | System for limiting if variation in phase locked loops |
| JP4071464B2 (en) * | 2001-07-17 | 2008-04-02 | 株式会社東芝 | Audio clock recovery apparatus and audio clock recovery method |
| KR100837115B1 (en) * | 2007-02-28 | 2008-06-11 | 지씨티 세미컨덕터 인코포레이티드 | Dual radio frequency receiver circuit and method for controlling the same |
| WO2009101811A1 (en) * | 2008-02-14 | 2009-08-20 | Panasonic Corporation | Receiver and electronic device using the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0677823A (en) * | 1992-08-24 | 1994-03-18 | Oki Electric Ind Co Ltd | Frequency synthesizer |
-
1998
- 1998-07-16 WO PCT/IB1998/001081 patent/WO1999008384A2/en not_active Application Discontinuation
- 1998-07-16 JP JP11511896A patent/JP2001502157A/en active Pending
- 1998-07-16 CN CN98801515A patent/CN1241325A/en active Pending
- 1998-07-16 KR KR1019997003082A patent/KR20000068744A/en not_active Application Discontinuation
- 1998-07-16 EP EP98929594A patent/EP0943180A1/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158227A (en) * | 2010-02-11 | 2011-08-17 | 奇景光电股份有限公司 | Non-integer N type phase-locked loop |
| CN102158227B (en) * | 2010-02-11 | 2013-04-17 | 奇景光电股份有限公司 | Non-integer N type phase-locked loop |
| CN109104185A (en) * | 2017-06-21 | 2018-12-28 | 三星电子株式会社 | The operating method of digital phase-locked loop and digital phase-locked loop |
| CN109104185B (en) * | 2017-06-21 | 2022-06-07 | 三星电子株式会社 | Digital phase locked loop and method of operating digital phase locked loop |
Also Published As
| Publication number | Publication date |
|---|---|
| WO1999008384A3 (en) | 1999-04-29 |
| EP0943180A1 (en) | 1999-09-22 |
| WO1999008384A2 (en) | 1999-02-18 |
| KR20000068744A (en) | 2000-11-25 |
| JP2001502157A (en) | 2001-02-13 |
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