TWI412233B - Fractional-n phase-locked loop - Google Patents

Abstract

The present invention is directed to a fractional-N phase-locked loop (PLL). The fractional-N PLL includes a phase detector, a voltage-controlled oscillator (VCO), a frequency divider and a frequency multiplier with a multiplication factor of a mixed number. The phase detector compares phase difference between a reference frequency and a divided signal from the frequency divider. The voltage-controlled oscillator generates the output frequency according to the phase difference. The frequency multiplier performs frequency multiplication on the output frequency to generate a multiplied signal, and the frequency multiplier comprises a second phase-locked loop, thereby forming a second loop therein. The frequency divider performs frequency division on the multiplied signal to generate the divided signal. The divided signal and the reference frequency are compared by the phase detector to determine the phase difference.

Description

Non-integer N-type phase-locked loop

The present invention relates to a phase locked loop, and more particularly to a nested non-integer N type phase locked loop.

A phase-locked loop (PLL) is a control circuit that uses negative feedback to lock the phase of the output frequency to a reference frequency. Phase-locked loops are widely used in a variety of applications, such as synthesizing a stable frequency or recovering a signal from a communication channel. The ratio of the output frequency of the phase-locked loop to the reference frequency can be an integer, or an integer plus a fractional fraction, the former being commonly referred to as an integer-type N-phase phase-locked loop/synthesizer (integer-N PLL/synthesizer). The latter is often referred to as a non-integer N-type phase-locked loop/synthesizer (fractional-N PLL/synthesizer). Among various types of non-integer N-type synthesizers, a delta-sigma synthesizer with a delta sigma modulator (SDM) is often used. However, the quantization noise generated by the delta-sigma modulator causes a phenomenon of output clock jitter. In order to slow down the clock jitter, a capacitor with a large amount of capacitance (for example, more than a thousand picofarad (pF)) is used to filter out the quantization error, resulting in an increase in circuit area and energy consumption.

In view of the fact that the existing phase-locked loop cannot effectively reduce the clock jitter of the delta-synthesizer, it is urgent to propose a new architecture that can effectively filter out the quantization error before adding the circuit area.

In view of the above background of the invention, it is an object of embodiments of the present invention to provide a non-integer N-type phase-locked loop that can efficiently filter out quantization errors without using too large a capacitance.

In accordance with an embodiment of the invention, a non-integer N-type phase-locked loop (fractional-N PLL) includes a first phase locked loop and a second phase locked loop. In the first phase locked loop, the first phase detector compares the first phase difference and generates a first error signal to indicate the first phase difference. A first voltage-controlled oscillator (VCO) generates an output frequency based on the first error signal. A frequency multiplier multiplies the output frequency to produce a multiplied signal, the frequency multiplier comprising a second phase locked loop that forms a second loop. The first frequency divider divides the frequency multiplied signal to generate a first frequency divided signal. The first frequency detector is compared with a reference frequency by the first phase detector to determine the first phase difference. In a specific embodiment, the frequency bandwidth of the second phase locked loop of the frequency multiplier is greater than the bandwidth of the first phase locked loop.

First, please refer to the first figure, which is a functional block diagram of a specific embodiment of the non-integral N-type phase-locked loop 1 disclosed in the present invention.

In this embodiment, the phase locked loop 1 includes a phase detector (PD) 10, a charge pump (CP) 11, a loop filter (LF) 12, and a voltage controlled oscillator (Voltage). -Controlled Oscillator, VCO) 13, Frequency Divider (FD) 14 and frequency multiplier 15. Specifically, the phase detector 10 is preferably a phase frequency detector (PFD) for comparing the phase difference between the reference frequency f _r and the frequency-divided signal output by the frequency divider 14 . An error signal is generated to represent the phase difference between the two frequencies. The charge cylinder 11 controls the ㄧ charge tube current according to the error signal output from the phase detector 10. The loop filter 12 can be a low-pass filter for smoothing the output of the charge cylinder 11 to generate a filtered signal for transmission to the voltage controlled oscillator 13, and the loop filter 12 can include a ㄧ resistor RC circuit. Based voltage controlled oscillator 13 for generating an output frequency f _out, the output frequency f _out of the system and the filtered signal in proportion or indirectly generated according to the error signal output of the phase detector 10. Multiplier 15 the output frequency f _out to produce an octave-frequency signal. In the present embodiment, the multiplication factor of the frequency multiplier 15 is a band fraction, that is, an integer M plus a fraction F. The frequency divider 14 is used to divide the frequency multiplied signal to generate a divisor signal. In the present embodiment, the frequency dividing coefficient of the frequency divider 14 is an integer N. It should be noted that in the phase-locked loop 1, all blocks except the frequency multiplier 15 can be implemented using a general phase-locked loop technique.

Next, please refer to the second figure, which is a schematic diagram of a system architecture of a specific embodiment of a nested phase-locked loop disclosed in the present invention. Please also refer to the third figure, which is an example implementation circuit with design parameters. As shown in the second figure, the frequency multiplier 15 can be implemented by a phase-locked loop architecture. The frequency multiplier 15 includes a phase detector (PD) 150, a charge pump (CP) 151, a loop circuit filter (LF) 152, a voltage controlled oscillator (VCO) 153, and a frequency divider 154. The frequency divider 154 has a frequency division factor of (M+F); the voltage controlled oscillator (VCO) 153 generates a frequency multiplied signal based on the filtered signal output by the loop filter (LF) 152. The functions and architectures of the above blocks 151 to 154 are similar to the blocks 11 to 14, so the details thereof will not be described. In particular, the phase detector 150 is for comparing the phase difference between the output frequency f _out and the divided signal output by the frequency divider 154. In addition, a delta sigma modulator (SDM) 155 provides a fraction F to the frequency divider 154 based on the divisor signal of the frequency divider 154. In the present specification, the phase detector 10, the charge cylinder 11, the loop filter 12, the voltage controlled oscillator 13, the frequency divider 14 and the like and the related signals may be added with a "first"; and the phase detector 150, the charge cylinder 151, the loop filter 152, the voltage controlled oscillator 153, the frequency divider 154 and other components and their associated signals can be added "second" to facilitate differentiation.

According to the architecture shown in the second figure, a multi-loop or nested phase-locked loop is thus formed. Although the present embodiment is only exemplified by a two-layer loop phase-locked loop, the multi-loop PLL of the multi-layer loop of more than two layers can of course be implemented in the same concept, and therefore is not limited to the disclosed one. . In this embodiment, the voltage controlled oscillator gain (VCO gain) of the voltage controlled oscillator 13 of the first loop (or main loop) of the phase locked loop (for example, 360 MHz/v) is smaller than the second loop of the frequency multiplier 15. The voltage controlled oscillator gain of the voltage controlled oscillator 153 (e.g., 1640 MHz/v). The bandwidth of the first loop is smaller than that of the second loop, so the second loop operates faster than the first loop. Thus, the second loop first filters out the quantization error produced by the triangular integral modulator (SDM) 155, and then filters the quantization error step by step from the narrower bandwidth first loop.

According to the embodiment described above, the nested non-integer N-type phase-locked loop can filter the quantization error more effectively than the conventional phase-locked loop, thereby reducing the phenomenon of output clock jitter. It is worth noting that the capacitance of the capacitor used in the nested non-integer N-type phase-locked loop is smaller than that used in the conventional phase-locked loop. For example, as shown in the third figure, a capacitor with a capacitance value of 273 pF is sufficient to filter the quantization error, and thus, the circuit area and energy loss of the nested non-integer N-type phase-locked loop can be practically reduced.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

1‧‧‧ phase-locked loop
10, 150‧‧‧ phase detector
11, 151‧‧‧ charge cylinder
12, 152‧‧‧ loop filter
13, 153‧‧‧voltage controlled oscillator
14, 154‧‧ ‧ frequency divider
15‧‧‧Multiplier
155‧‧‧Triangle integral modulator
f _r ‧‧‧reference frequency
f _out ‧‧‧output frequency

The first figure is a functional block diagram of a specific embodiment of a non-integral N-type phase-locked loop disclosed in the present invention.
The second figure is a schematic diagram of a system architecture of a specific embodiment of a nested phase locked loop disclosed in the present invention.
The third figure is a specific embodiment of an example implementation circuit having design parameters disclosed in the present invention.

10,150‧‧‧ phase detector

11,151‧‧‧charged cylinder

12,152‧‧‧ loop filter

13,153‧‧‧Variable Control Oscillator

14,154‧‧‧Delephone

15‧‧‧Multiplier

155‧‧‧Triangle integral modulator

f _r ‧‧‧reference frequency

f _out ‧‧‧output frequency

Claims (10)

A non-integer N-type phase-locked loop, comprising:
a first phase detector for comparing a first phase difference to generate a first error signal to indicate the first phase difference;
The first voltage controlled oscillator is configured to generate an output frequency according to the first error signal;
a frequency multiplier that multiplies the output frequency to generate a frequency multiplied signal, the frequency multiplier includes a second phase locked loop, thereby forming a second loop; and a first frequency divider, the pair The frequency-divided signal is divided to generate a first frequency-divided signal, wherein the first phase-detecting signal is compared with a reference frequency by the first phase detector to determine the first phase difference;
The first phase detector, the first voltage controlled oscillator, the frequency multiplier and the first frequency divider form a first loop. The non-integer N-type phase-locked loop of claim 1, wherein the bandwidth of the second loop is greater than the bandwidth of the second loop. The non-integer N-type phase-locked loop of claim 1, wherein the second loop operates faster than the first loop. The non-integer N-type phase-locked loop of claim 1, wherein the second phase-locked loop comprises:
a second phase detector for comparing a second phase difference to generate a second error signal to indicate the second phase difference;
a second charge cylinder, which controls the second charge tube current according to the second error signal output by the second phase detector;
a second loop filter for smoothing the output of the second charge cartridge to generate a second filtered signal;
a second voltage-controlled oscillator, which generates the multi-frequency signal according to the second filtered signal; and a second frequency divider for dividing the multi-frequency signal to generate a second frequency-divided signal, The second phase detector is compared with the output frequency by the second phase detector to determine the second phase difference. The non-integer N-type phase-locked loop as described in claim 4, further comprising a delta-sigma integral modulator, according to the second frequency-divided signal, to provide a fractional value of the multiplication factor. The non-integer N-type phase-locked loop according to claim 1, wherein the first phase detector is a ㄧ phase/frequency detector. The non-integer N-type phase-locked loop according to claim 1, further comprising a first charge cylinder, wherein the first error signal is output according to the first error signal of the second phase detector to control the first charge current . The non-integer N-type phase-locked loop as described in claim 7 further includes a first-loop filter for smoothing the output of the first charge cartridge to generate a first filtered signal, wherein the first The filtered signal is further transmitted to the first voltage controlled oscillator. A non-integer N-type phase-locked loop as described in claim 8 wherein the first loop filter is a low-pass filter. The non-integer N-type phase-locked loop of claim 9, wherein the first loop filter comprises a RC circuit.