CN1815892A - Circuit for detecting phase-error and generating control signal - Google Patents
Circuit for detecting phase-error and generating control signal Download PDFInfo
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Abstract
Being applied to phase locked loop, the disclosed circuit includes a digital phase detector, and a digital filter. Receiving two input signals, the digital phase detector generates a set of control signal of phase difference based on phase error. The digital filter includes a correspondence table, an adder, and a register. Receiving the control signal of phase difference, the correspondence table outputs a corresponding value. Receiving the corresponding value and a value of register, the adder generates control data. Receiving and storing the control data, the register outputs the data stored as the value of the register. The correspondence table can be as a memory, and control signal of phase difference is as its address information. Chip area of phase locked loop of using the disclosed circuit is smaller than area of traditional circuit.
Description
Technical field
The present invention relates to a kind of detected phase error and produce the circuit of control signal, particularly relate to a kind of detected phase error of handling with digital form and the circuit that produces control signal, this circuit application is in phase-locked loop or delay locked loop.
Background technology
General traditional phase-locked loop comprises analog phase-locked loop and two kinds of digital phase-locked loops, and wherein the phase detectors of the phase-locked loop that shows of Fig. 1 are analogue phase detectors, and the phase detectors of the phase-locked loop of Fig. 2 demonstration are digital phase detectors.
The phase-locked loop 10 of Fig. 1 comprises phase detectors (Phase Detector) 13, one charge pumps (Charge Pump) 14, one loop filters (Loop Filter) 15 and one voltage controlled oscillator (Voltage Control Oscillator, VCO) 16.Phase detectors 13 are used for detecting the phase difference value of input signal (Fref) and phase-locked clock pulse (Fvco), and control charge pump 14 according to phase difference value output control pulse Up, Dn.For example, when the phase place of leading (leading) input signal Fref of the phase place of phase-locked clock pulse Fvco, the width of the control impuls Up of phase detectors 13 outputs can make charge pump 14 produce the Control current Icp of negative value (negative) less than the width of control impuls Dn thus.At this moment, loop filter 15 will be controlled voltage Vctl according to this negative value Control current Icp and reduce, and allow the clock pulse of the phase-locked clock pulse Fvco that voltage controlled oscillator 16 exported reduce.Otherwise, when the phase place of phase lag (lagging) the input signal Fref of phase-locked clock pulse Fvco, the width of the control impuls Up of phase detectors 13 output can be greater than the width of control impuls Dn, makes charge pump 14 produce Control current Icp on the occasion of (positive) thus.15 bases of loop filter should will controls voltage Vctl on the occasion of Control current Icp to be increased, and allows the clock pulse lifting of the phase-locked clock pulse Fvco that voltage controlled oscillator 16 exported.
The phase-locked loop 20 of Fig. 2 comprises a digital phase detector (Digital Phase Detector) 23, one charge pump 24, a loop filter 15 and a voltage controlled oscillator 16.Wherein the digital phase detector 23 of phase-locked loop 20 is disclosed for the 6th, 259, No. 278 by No. the 510083rd, TaiWan, China patent documentation and United States Patent (USP).Digital phase detector 23 utilizes digital mode to produce one group of phase difference control signal Up1～UpN, Dn1～DnN and is sent to charge pump.And, send loop filter 15 again to and produce control voltage Vctl by charge pump 14 generations one Control current Icp.Phase-locked loop 20 is identical with the operating principle of phase-locked loop 10, and its otherness is that the signal that digital phase detector 23 is produced is a digital signal.Mode phase-locked loop 20 can provide quite good detecting effectiveness according to this, detects dead band (dead zone) to reduce, and can reduce the shake (jitter) and the tolerance that increases data randomized jitters (data random jitter) of clock pulse.
But the output signal of the loop filter 15 of phase-locked loop 20 remains analog signal, and this loop filter 15 belongs to low pass filter, needs bigger area implement this loop filter 15.
Summary of the invention
The object of the present invention is to provide a digital detected phase error and produce the circuit of control signal, reduce the chip area of the phase-locked loop of using this circuit thus.
For reaching above-mentioned purpose, detected phase error of the present invention and the circuit that produces control signal comprise a digital phase detector and a digital filter.This digital phase detector receives an input signal and a reference signal, and produces one group of phase difference control signal, and digital filter produces a control data according to the phase difference control signal.This digital filter comprises a correspondence table, an adder and a register.This correspondence table receiving phase difference control data, and export a respective value.And adder receives a respective value and a register value, and produces control data.Register receives and storage control data, and the data that output is stored are as register value.
The invention provides a kind of phase-locked loop, comprise a voltage controlled oscillator, produce an oscillator signal; One digital phase detector receives a reference signal and described oscillator signal, and produces one group of phase difference control signal according to the phase difference of two signals; One digital filter receives described phase difference control signal and produces control data; And a digital analog converter, receive described control data and convert a control voltage to; Wherein said voltage controlled oscillator produces described oscillator signal according to described control voltage.
The present invention also provides a kind of delay phase-locked loop, comprises a voltage controlled delay line, produces an output signal; One digital phase detector receives a reference signal and described output signal, and produces one group of phase difference control signal according to the phase difference of two signals; One digital filter receives described phase difference control signal and produces control data; And a digital analog converter, receive described control data and convert a control voltage to; Wherein said voltage controlled delay line produces described output signal according to described control voltage and described reference signal.
Adopt the present invention, can make the chip area of the phase-locked loop that is applied to this circuit littler than the traditional circuit.
Description of drawings
Fig. 1 is the block diagram of a conventional phase locked loops.
Fig. 2 is the block diagram of another conventional phase locked loops.
Fig. 3 is a block diagram according to phase-locked loop of the present invention.
Fig. 4 is a schematic diagram according to a kind of digital filter of the present invention.
Fig. 5 is the embodiment of corresponding relation of the respective value of phase difference control signal and correspondence table.
Fig. 6 is one according to the phase difference control signal that a kind of digital filter of the present invention received and the coordinate diagram of its register relativeness.
Fig. 7 is a block diagram according to delay locked loop of the present invention.
Fig. 8 is the block diagram of embodiment of the voltage controlled delay line of Fig. 7.
Fig. 9 is another block diagram according to delay locked loop of the present invention.
In the accompanying drawings:
10 analog phase-locked loops
13 phase clock pulse detectors
14 charge pumps
15 loop filters
16 voltage controlled oscillators
20 phase-locked loops
23 digital phase detectors
30 digital type phase-locked loops
31 phase measuring circuits
311 digital phase detectors
312 digital filters
3121 correspondence table
3122 adders
3123 registers
32 digital analog converters
70 phase-locked loops
73 voltage controlled delay lines
731 reversers
Embodiment
Describe detected phase error of the present invention in detail and produce the circuit of control signal below with reference to accompanying drawing, and the phase-locked loop and the delay locked loop that use this circuit.
Fig. 3 display application detected phase error of the present invention also produces the block diagram of phase-locked loop of the circuit of control signal.As shown in the drawing, phase-locked loop 30 comprises a detected phase error and produces the circuit (hereinafter to be referred as phase measuring circuit) 31 of control signal, a digital analog converter (Digital to Analog Converter, DAC) 32 and one voltage controlled oscillator 16.Phase measuring circuit 31 receives a reference signal Fref and a running clock pulse Fvco, and produces a control data according to its phase difference.Afterwards, this phase-locked loop 30 utilizes digital analog converter 32 to convert control data to control voltage Vctl and controls voltage controlled oscillator 16.Because phase measuring circuit 31 produces control data with digital form, so phase-locked loop of the present invention 30 has preferable control accuracy, thereby has preferable noise immunity (noise immunity).
Phase-locked loop shown in Fig. 3 also can be used for locking in the application of a clock pulse signal, this moment, reference signal Fref was a clock pulse signal, this phase-locked loop also can be used in the application of data recovery circuit (datarecovery circuit), and then this moment, reference signal Fref was the data of being imported.
Fig. 4 is the block diagram of the digital filter 312 of Fig. 3.As shown in Figure 4, (Up1～Upn, Dn1～DnN) produce a control data to the phase difference control signal that transmits according to digital phase detector 311 of digital filter 312.This digital filter 312 comprises a correspondence table 3121, an adder 3122 and a register 3123.
Correspondence table 3121 receiving phase difference control signals (Up1～Upn, Dn1～DnN), and export a respective value.Adder 3122 receives a respective value and a register value, and produces control data.Register 3123 receives and storage control data, and exports its data of storing as register value.Wherein correspondence table 3121 can be implemented by a memory, and with phase difference control signal (Up1～Upn, Dn1～DnN) as address signal.Perhaps this correspondence table can be made up of gate, makes the output of correspondence table meet the specification of Fig. 5.Certainly, this specification is a kind of embodiment, and the phase difference control signal of needs cooperation digital filter 311 (Up1～Upn, Dn1～DnN) decide.
As shown in Figure 5, when state S1, phase difference control signal Up1, Up2 ..., Up5, Dn1, Dn2 ..., Dn5 is [1000000000], correspondence table 3121 is output as 1, expression has slight phase lag at present.When phase place seriously falls behind, then be state S5, phase difference control signal Up1, Up2 ..., Up5, Dn1, Dn2 ..., Dn5 is [0000100000], correspondence table 3121 is output as 16.And when phase place is slight leading, phase difference control signal Up1, Up2 ..., Up5, Dn1, Dn2 ..., Dn5 is [0000010000], correspondence table 3121 is output as-1.When phase place is serious leading, phase difference control signal Up1, Up2 ..., Up5, Dn1, Dn2 ..., Dn5 is [0000000001], correspondence table 3121 is output as-16.Therefore, correspondence table 3121 can according to phase difference control signal Up1, Up2 ..., Up5, Dn1, Dn2 ..., Dn5 exports a suitable respective value.
In addition, digital filter of the present invention is to utilize adder and register to accumulate the respective value that produces because of phase error, filters radio-frequency component thus.Fig. 6 show the phase difference control signal (relativeness of Up1～Upn, Dn1～DnN) and register accumulation amount (respective value), can represent according to following manner:
When slight phase lag error, the Up1 of phase difference control signal is a high level, and respective value is 1, and therefore, register increases by 1 via adder; When the phase lag error increased, the Up2 of phase difference control signal was a high level, and respective value is 2, so register increases by 2 via adder; When the phase lag error increased again, the Up3 of phase difference control signal was a high level, and register increases by 4 via adder; When the phase lag error increased again, the Up4 of phase difference control signal was a high level, and register increases by 8 via adder; And when the phase lag error was quite serious, the Up5 of phase difference control signal was a high level, and register increases by 16 via adder.Therefore, the effect of register and adder can be filtered the radio-frequency component of phase error with regard to a similar integrator, just carries out the low-pass filtering action.The leading error situation of phase place is also similar.
Certainly, as what those skilled in the art extensively knew, the size of the respective value of being stored in correspondence table 3121 will determine the degree of above-mentioned low-pass filtering, and just therefore the position of the 3dB clock pulse of digital filter 312 can be set according to practical application.
Next illustrate the manner of execution of digital filter 312.When digital phase detector 311 transmitted one group of phase difference control signal (Up2, Up3 are high level in regular turn) to digital filter 312, correspondence table 3121 was exported a respective value (is 2 and 4 at this embodiment) after receiving this group phase difference control signal.Respective value 2 when at first correspondence table 3121 is H with phase difference control signal Up2 is sent to adder 3122.Adder 3122 is respective value 2 register value 0 (this register value the is preset as 0) addition with register, and the result of gained is stored to register as new register value 2.Adder 3122 exports this new register value 2 to digital analog converter 32 simultaneously, as a control data.Respective value 4 when then correspondence table 3121 is H with Up3 again is sent to adder 3122.Adder 3122 is this respective value 4 and register value 2 additions, and the result of gained is stored to register as new register value 6.Simultaneously adder 3122 will this new register value 6, exports digital analog converter 32 to, as next control data.Then digital filter 312 continues to receive another group phase difference control signal.
Because the application's digital filter 312 is to utilize correspondence table 3121, adder 3122 and register 3123 to do numeral control, to reach the effect of filtering.Compare with traditional loop filter 15, this digital filter 312 has preferable noise immunity (noise immunity), and the characteristic that is easier to planning (easy to program) is arranged.And compare with traditional loop filter 15, this digital filter 312 only need use the minority gate, and not need capacitive means when low frequency uses, and can reduce traditional loop filter 15 equipment volume that increase increased because of capacitance when low frequency uses.
Fig. 7 display application detected phase error of the present invention also produces delay locked loop (Delay Locked Loop, block diagram DLL) of the circuit of control signal.Delay locked loop shown in Fig. 7 is used for locking the application of a clock pulse signal.As shown in the drawing, delay locked loop 70 comprises a phase measuring circuit 31, a digital analog converter 32 and a voltage controlled delay line (voltage controlled delayline) 73.This delay phase-locked loop 70 is that delay phase-locked loop 70 is to replace voltage controlled oscillator 16 with voltage controlled delay line 73 with the difference of the phase-locked loop 30 of Fig. 3.Voltage controlled delay line 73 receives the control voltage Vctl and the reference signal Fref of digital analog converter 32, and produces output clock pulse Fout.Phase measuring circuit 31 receives reference signal Fref and output clock pulse Fout, and produces control data.32 of digital analog converters receive control data, and produce control voltage Vctl.Owing to action and the framework and described identical of phase measuring circuit 31 with digital analog converter 32, no longer repeat specification.
Fig. 8 is the block diagram of embodiment of the voltage controlled delay line of Fig. 7.As shown in the drawing, general voltage controlled delay line 73 is formed by a plurality of voltage control reverser 731 serial connections.First reverser 731 receives reference signal Fref, and last reverser 731 output output clock pulse Fout.Each reverser 731 is by control voltage Vctl control.
Fig. 9 shows Another Application detected phase error of the present invention and produces the block diagram of delay locked loop of the circuit of control signal.Delay locked loop shown in Fig. 9 is used in the application of data recovery circuit.The delay locked loop of Fig. 9 and shown in Figure 7 very close only replaces to the signal of input phase detector 311 data of input data recovery circuit, the then input separately of pulse reference clocks that voltage controlled delay line 73 is required.
Though more than with embodiment the present invention is described, therefore do not limit the scope of the invention, only otherwise break away from aim of the present invention, these those skilled in the art can carry out various changes or modification.
Claims (10)
1. a detected phase error and produce the circuit of control signal is characterized in that, comprises:
One digital phase detector receives an input signal and a reference signal, and produces one group of phase difference control signal according to the phase difference of two signals; And
One digital filter receives described phase difference control signal and produces control data.
2. detected phase error according to claim 1 also produces the circuit of control signal, it is characterized in that described digital filter includes:
One correspondence table receives described phase difference control signal, and exports a respective value;
One adder receives a described respective value and a register value, and produces described control data; And
One register receives and stores described control data, and the data that output is stored are as described register value.
3. detected phase error according to claim 1 also produces the circuit of control signal, it is characterized in that described digital filter carries out the low-pass filtering computing to the control signal that this phase difference produces.
4. detected phase error according to claim 1 also produces the circuit of control signal, it is characterized in that described correspondence table is a memory, and with described phase difference control signal as address signal.
5. detected phase error according to claim 1 also produces the circuit of control signal, it is characterized in that described correspondence table is a combinational logic, and produces described respective value according to described phase difference control signal.
6, detected phase error according to claim 1 and produce the circuit of control signal is characterized in that this circuit application is in phase-locked loop.
7, a kind of phase-locked loop is characterized in that, comprises:
One voltage controlled oscillator produces an oscillator signal;
One digital phase detector receives a reference signal and described oscillator signal, and produces one group of phase difference control signal according to the phase difference of two signals;
One digital filter receives described phase difference control signal and produces control data; And
One digital analog converter receives described control data and converts a control voltage to;
Wherein said voltage controlled oscillator produces described oscillator signal according to described control voltage.
8, phase-locked loop according to claim 5 is characterized in that, described digital filter comprises:
One correspondence table receives described phase difference control signal, and exports a respective value;
One adder receives a described respective value and a register value, and produces described control data; And
One register receives and stores described control data, and the data that output is stored are as described register value.
9, a kind of delay phase-locked loop is characterized in that, comprises:
One voltage controlled delay line produces an output signal;
One digital phase detector receives a reference signal and described output signal, and produces one group of phase difference control signal according to the phase difference of two signals;
One digital filter receives described phase difference control signal and produces control data; And
One digital analog converter receives described control data and converts a control voltage to;
Wherein said voltage controlled delay line produces described output signal according to described control voltage and described reference signal.
10, delay phase-locked loop according to claim 7 is characterized in that, described digital filter comprises:
One correspondence table receives described phase difference control signal, and exports a respective value;
One adder receives a described respective value and a register value, and produces described control data; And
One register receives and stores described control data, and the data that output is stored are as described register value.
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