CN1815892A - A circuit that detects phase errors and generates control signals - Google Patents

Abstract

A circuit for detecting phase error and generating control signal is applied to a phase-locked loop. The circuit includes a digital phase detector and a digital filter. The digital phase detector receives two input signals and generates a set of phase difference control signals according to the phase error. The digital filter includes a corresponding table, an adder, and a register. The mapping table receives the phase difference control signal and outputs a corresponding value. The adder receives the corresponding value and a register value and generates control data. The register receives and stores the control data, and outputs the stored data as a register value. The mapping table may be a memory, and the phase difference control signal is used as the address signal. The invention can make the chip area of the phase-locked loop applied to the circuit smaller than that of the traditional circuit.

Description

A circuit that detects phase errors and generates control signals

technical field

The invention relates to a circuit for detecting phase error and generating a control signal, in particular to a circuit for detecting phase error and generating a control signal processed in a digital mode, which is applied to a phase-locked loop or a delay-locked loop.

Background technique

Generally, traditional phase-locked loops include analog phase-locked loops and digital phase-locked loops. The phase detector of the phase-locked loop shown in Figure 1 is an analog phase detector, and the phase detector of the phase-locked loop shown in Figure 2 detector is a digital phase detector.

The phase locked loop 10 of Fig. 1 comprises a phase detector (Phase Detector) 13, a charge pump (Charge Pump) 14, a loop filter (Loop Filter) 15, and a voltage controlled oscillator (Voltage Control Oscillator, VCO) )16. The phase detector 13 is used to detect the phase difference between the input signal (Fref) and the phase-locked clock (Fvco), and output control pulses Up and Dn according to the phase difference to control the charge pump 14 . For example, when the phase of the phase-locked clock pulse Fvco is leading the phase of the input signal Fref, the width of the control pulse Up output by the phase detector 13 will be smaller than the width of the control pulse Dn, thereby causing the charge pump 14 to generate a negative value ( negative) control current Icp. At this moment, the loop filter 15 reduces the control voltage Vctl according to the negative control current Icp, so that the clock pulse of the phase-locked clock pulse Fvco output by the voltage-controlled oscillator 16 decreases. Conversely, when the phase of the phase-locked clock pulse Fvco lags (lagging) the phase of the input signal Fref, the width of the control pulse Up output by the phase detector 13 will be greater than the width of the control pulse Dn, thereby enabling the charge pump 14 to generate a positive value (positive) control current Icp. The loop filter 15 increases the control voltage Vctl according to the positive control current Icp, so that the clock pulse of the phase-locked clock pulse Fvco output by the voltage-controlled oscillator 16 is boosted.

The phase-locked loop 20 of FIG. 2 includes a digital phase detector (Digital Phase Detector) 23, a charge pump 24, a loop filter 15, and a voltage-controlled oscillator 16. The digital phase detector 23 of the PLL 20 is disclosed in Taiwan Patent Document No. 510083 and US Patent No. 6,259,278. The digital phase detector 23 digitally generates a set of phase difference control signals Up1-UpN, Dn1-DnN and sends them to the charge pump. And the charge pump 14 generates a control current Icp, which is then sent to the loop filter 15 to generate the control voltage Vctl. The operation principle of the phase-locked loop 20 is the same as that of the phase-locked loop 10, and the difference is that the signal generated by the digital phase detector 23 is a digital signal. In this manner, the phase-locked loop 20 can provide a better detection effect to reduce the detection dead zone, reduce the jitter of the clock pulse and increase the tolerance of data random jitter.

However, the output signal of the loop filter 15 of the phase-locked loop 20 is still an analog signal, and the loop filter 15 is a low-pass filter, requiring a larger area to implement the loop filter 15 .

Contents of the invention

The object of the present invention is to provide a digital circuit for detecting phase errors and generating control signals, thereby reducing the chip area of the PLL in which the circuit is applied.

To achieve the above object, the circuit for detecting phase error and generating control signal of the present invention includes a digital phase detector and a digital filter. The digital phase detector receives an input signal and a reference signal, and generates a set of phase difference control signals, and the digital filter generates a control data according to the phase difference control signals. The digital filter includes a correspondence table, an adder, and a register. The corresponding table receives the phase difference control data and outputs a corresponding value. The adder receives the corresponding value and a registered value, and generates control data. The register receives and stores control data, and outputs the stored data as a registered value.

The present invention provides a phase-locked loop, comprising a voltage-controlled oscillator to generate an oscillating signal; a digital phase detector to receive a reference signal and the oscillating signal, and generate a set of phase difference control according to the phase difference between the two signals signal; a digital filter that receives the phase difference control signal and generates control data; and a digital-to-analog converter that receives the control data and converts it into a control voltage; wherein the voltage-controlled oscillator operates according to the control voltage The oscillating signal is generated.

The present invention also provides a delay-locked loop, including a voltage-controlled delay line, which generates an output signal; a digital phase detector, which receives a reference signal and the output signal, and generates a set of phases according to the phase difference between the two signals a difference control signal; a digital filter that receives the phase difference control signal and generates control data; and a digital-to-analog converter that receives the control data and converts it into a control voltage; wherein the voltage-controlled delay line is based on the control voltage with the reference signal to generate the output signal.

By adopting the invention, the chip area of the phase-locked loop applied to the circuit can be made smaller than that of the traditional circuit.

Description of drawings

FIG. 1 is a block diagram of a conventional phase-locked loop.

FIG. 2 is a block diagram of another conventional PLL.

Fig. 3 is a block diagram of a phase locked loop according to the present invention.

FIG. 4 is a schematic diagram of a digital filter according to the present invention.

FIG. 5 is an embodiment of the corresponding relationship between the phase difference control signal and the corresponding value in the corresponding table.

FIG. 6 is a coordinate diagram of the relative relationship between the phase difference control signal received by a digital filter and its register according to the present invention.

FIG. 7 is a block diagram of a delay locked loop according to the present invention.

FIG. 8 is a block diagram of an embodiment of the voltage-controlled delay line of FIG. 7 .

FIG. 9 is a block diagram of another delay locked loop according to the present invention.

In the attached picture:

10 Analog PLL

13 phase clock pulse detector

14 charge pump

15 loop filter

16 voltage controlled oscillator

20 PLL

23 Digital Phase Detector

30 digital phase locked loop

31 Phase measurement circuit

311 Digital Phase Detector

312 digital filter

3121 correspondence table

3122 adder

3123 Register

32 digital to analog converter

70 phase locked loop

73 Voltage controlled delay line

731 reverser

Detailed ways

The circuit for detecting a phase error and generating a control signal, and a phase-locked loop and a delay-locked loop using the circuit of the present invention will be described in detail below with reference to the accompanying drawings.

Fig. 3 shows a block diagram of a phase-locked loop applying the circuit of the present invention to detect phase error and generate a control signal. As shown in the figure, the phase-locked loop 30 includes a circuit (hereinafter referred to as the phase measurement circuit) 31 for detecting phase error and generating a control signal, a digital-to-analog converter (Digital to Analog Converter, DAC) 32, and a voltage-controlled oscillator device 16. The phase measurement circuit 31 receives a reference signal Fref and an oscillating clock Fvco, and generates a control data according to their phase difference. Afterwards, the phase-locked loop 30 utilizes the digital-to-analog converter 32 to convert the control data into a control voltage Vctl to control the voltage-controlled oscillator 16 . Since the phase measurement circuit 31 generates control data in a digital manner, the phase-locked loop 30 of the present invention has better control accuracy and thus better noise immunity.

The phase-locked loop shown in Fig. 3 can also be used in the application of locking a clock pulse signal, and this moment, reference signal Fref is a clock pulse signal, and this phase-locked loop can also be used in the application of data recovery circuit (datarecovery circuit), Then the reference signal Fref at this time is the input data.

The phase measurement circuit 31 includes a digital phase detector 311 and a digital filter 312 . The digital phase detector 311 receives the reference signal Fref and the oscillating clock pulse Fvco, and generates a set of phase difference control signals (Up1˜Upn, Dn1˜DnN) according to their phase differences. For the circuit and structure of the digital phase detector 311 , reference can be made to Taiwan Patent Document No. 510083 and US Patent No. 6,259,278, which will not be repeated here.

FIG. 4 is a block diagram of the digital filter 312 of FIG. 3 . As shown in FIG. 4 , the digital filter 312 generates a control data according to the phase difference control signals (Up1˜Upn, Dn1˜DnN) transmitted by the digital phase detector 311 . The digital filter 312 includes a mapping table 3121 , an adder 3122 , and a register 3123 .

The corresponding table 3121 receives the phase difference control signals (Up1˜Upn, Dn1˜DnN), and outputs a corresponding value. The adder 3122 receives the corresponding value and a registered value, and generates control data. The register 3123 receives and stores control data, and outputs the stored data as a registered value. The correspondence table 3121 can be implemented by a memory, and the phase difference control signals (Up1˜Upn, Dn1˜DnN) are used as address signals. Alternatively, the correspondence table may be composed of logic gates, so that the output of the correspondence table conforms to the specifications in FIG. 5 . Of course, this specification is just an embodiment, and it needs to be determined in conjunction with the phase difference control signals (Up1˜Upn, Dn1˜DnN) of the digital filter 311 .

As shown in Figure 5, in the state S1, the phase difference control signals Up1, Up2, ..., Up5, Dn1, Dn2, ..., Dn5 are [1000000000], and the output of the corresponding table 3121 is 1, indicating that there are Slightly out of phase. When the phase is seriously behind, it is in state S5, the phase difference control signals Up1, Up2, . . . , Up5, Dn1, Dn2, . And when the phase is slightly ahead, the phase difference control signals Up1, Up2, . . . , Up5, Dn1, Dn2, . When the phase is seriously advanced, the phase difference control signals Up1, Up2, . . . , Up5, Dn1, Dn2, . Therefore, the corresponding table 3121 can output an appropriate corresponding value according to the phase difference control signals Up1, Up2, . . . , Up5, Dn1, Dn2, . . . , Dn5.

In addition, the digital filter of the present invention uses an adder and a register to accumulate corresponding values generated by phase errors, thereby filtering high-frequency components. Figure 6 shows the relative relationship between the phase difference control signals (Up1~Upn, Dn1~DnN) and the accumulative value of the register (corresponding value), which can be expressed in the following way:

When there is a slight phase lag error, Up1 of the phase difference control signal is high level, and the corresponding value is 1, therefore, the register is increased by 1 through the adder; when the phase lag error increases, Up2 of the phase difference control signal is high level , the corresponding value is 2, so the register increases by 2 through the adder; when the phase lag error increases again, the Up3 of the phase difference control signal is high, and the register increases by 4 through the adder; when the phase lag error increases again, the phase difference When Up4 of the control signal is at high level, the register is incremented by 8 through the adder; and when the phase lag error is serious, Up5 of the phase difference control signal is at high level, and the register is incremented by 16 through the adder. Therefore, the function of the register and the adder is similar to an integrator, which can filter the high-frequency components of the phase error, that is, perform low-pass filtering. The error situation for phase lead is also similar.

Of course, as those skilled in the art know widely, the size of the corresponding value stored in the corresponding table 3121 will determine the degree of the above-mentioned low-pass filtering, that is, the position of the 3dB clock pulse of the digital filter 312, so it can be based on practical application to be set.

The operation of the digital filter 312 is described next with an example. When the digital phase detector 311 transmits a group of phase difference control signals (Up2, Up3 are at high level in sequence) to the digital filter 312, after the corresponding table 3121 receives the group of phase difference control signals, it outputs a corresponding value (here Examples are 2 and 4). First, the corresponding table 3121 transmits the corresponding value 2 when the phase difference control signal Up2 is H to the adder 3122 . The adder 3122 adds the corresponding value 2 to the register value 0 (the register value is preset as 0), and stores the result in the register as a new register value 2 . At the same time, the adder 3122 outputs the new registered value 2 to the digital-to-analog converter 32 as a control data. Then the corresponding table 3121 transmits the corresponding value 4 when Up3 is H to the adder 3122 . The adder 3122 adds the corresponding value 4 to the registered value 2 and stores the result in the register as a new registered value 6 . At the same time, the adder 3122 outputs the new registered value 6 to the digital-to-analog converter 32 as the next control data. Then the digital filter 312 continues to receive another set of phase difference control signals.

Because the digital filter 312 of the present application uses the corresponding table 3121, the adder 3122, and the register 3123 for digital control, so as to achieve the effect of filtering. Compared with the conventional loop filter 15, the digital filter 312 has better noise immunity and is easier to program. And compared with the traditional loop filter 15, the digital filter 312 only needs to use a small number of logic gates when it is used at low frequencies, and does not need a capacitor device, which can reduce the traditional loop filter 15 due to the capacitance loss when it is used at low frequencies. Increase the increased equipment volume.

FIG. 7 shows a block diagram of a delay-locked loop (Delay Locked Loop, DLL) of a circuit for detecting a phase error and generating a control signal using the present invention. The delay locked loop shown in Fig. 7 is used to lock the application of a clock pulse signal. As shown in the figure, the delay locked loop 70 includes a phase measurement circuit 31 , a digital-to-analog converter 32 , and a voltage controlled delay line (voltage controlled delay line) 73 . The difference between the DLL 70 and the PLL 30 of FIG. 3 is that the DLL 70 uses a voltage-controlled delay line 73 to replace the VCO 16 . The voltage-controlled delay line 73 receives the control voltage Vctl of the digital-to-analog converter 32 and the reference signal Fref, and generates an output clock pulse Fout. The phase measurement circuit 31 receives the reference signal Fref and the output clock pulse Fout, and generates control data. The digital-to-analog converter 32 receives the control data and generates the control voltage Vctl. Since the actions and structures of the phase measurement circuit 31 and the digital-to-analog converter 32 are the same as those described above, the description will not be repeated.

FIG. 8 is a block diagram of an embodiment of the voltage-controlled delay line of FIG. 7 . As shown in the figure, a general voltage-controlled delay line 73 is formed by a plurality of voltage-controlled inverters 731 connected in series. The first inverter 731 receives the reference signal Fref, and the last inverter 731 outputs the output clock pulse Fout. Each inverter 731 is controlled by a control voltage Vctl.

FIG. 9 shows a block diagram of a DLL of another circuit for detecting a phase error and generating a control signal using the present invention. The delay locked loop shown in Figure 9 is used in data recovery circuit applications. The delay locked loop in FIG. 9 is very similar to that shown in FIG. 7, only the signal input to the phase detector 311 is replaced with the data input to the data recovery circuit, and the reference clock pulse required by the voltage-controlled delay line 73 is input separately.

Although the present invention has been described above with examples, the scope of the present invention is not limited thereto. Those skilled in the art can make various changes or modifications as long as they do not deviate from the gist of the present invention.

Claims (10)

1. a detected phase error and produce the circuit of control signal is characterized in that, comprises:

One digital phase detector receives an input signal and a reference signal, and produces one group of phase difference control signal according to the phase difference of two signals; And

One digital filter receives described phase difference control signal and produces control data.

2. detected phase error according to claim 1 also produces the circuit of control signal, it is characterized in that described digital filter includes:

One correspondence table receives described phase difference control signal, and exports a respective value;

One adder receives a described respective value and a register value, and produces described control data; And

One register receives and stores described control data, and the data that output is stored are as described register value.

3. detected phase error according to claim 1 also produces the circuit of control signal, it is characterized in that described digital filter carries out the low-pass filtering computing to the control signal that this phase difference produces.

4. detected phase error according to claim 1 also produces the circuit of control signal, it is characterized in that described correspondence table is a memory, and with described phase difference control signal as address signal.

5. detected phase error according to claim 1 also produces the circuit of control signal, it is characterized in that described correspondence table is a combinational logic, and produces described respective value according to described phase difference control signal.

6, detected phase error according to claim 1 and produce the circuit of control signal is characterized in that this circuit application is in phase-locked loop.

7, a kind of phase-locked loop is characterized in that, comprises:

One voltage controlled oscillator produces an oscillator signal;

One digital phase detector receives a reference signal and described oscillator signal, and produces one group of phase difference control signal according to the phase difference of two signals;

One digital filter receives described phase difference control signal and produces control data; And

One digital analog converter receives described control data and converts a control voltage to;

Wherein said voltage controlled oscillator produces described oscillator signal according to described control voltage.

8, phase-locked loop according to claim 5 is characterized in that, described digital filter comprises:

One correspondence table receives described phase difference control signal, and exports a respective value;

One adder receives a described respective value and a register value, and produces described control data; And

One register receives and stores described control data, and the data that output is stored are as described register value.

9, a kind of delay phase-locked loop is characterized in that, comprises:

One voltage controlled delay line produces an output signal;

One digital phase detector receives a reference signal and described output signal, and produces one group of phase difference control signal according to the phase difference of two signals;

One digital filter receives described phase difference control signal and produces control data; And

One digital analog converter receives described control data and converts a control voltage to;

Wherein said voltage controlled delay line produces described output signal according to described control voltage and described reference signal.

10, delay phase-locked loop according to claim 7 is characterized in that, described digital filter comprises:

One correspondence table receives described phase difference control signal, and exports a respective value;

One adder receives a described respective value and a register value, and produces described control data; And

One register receives and stores described control data, and the data that output is stored are as described register value.

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