CN101202616B - Method and apparatus for controlling data processing - Google Patents
Method and apparatus for controlling data processing Download PDFInfo
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- CN101202616B CN101202616B CN2007100324570A CN200710032457A CN101202616B CN 101202616 B CN101202616 B CN 101202616B CN 2007100324570 A CN2007100324570 A CN 2007100324570A CN 200710032457 A CN200710032457 A CN 200710032457A CN 101202616 B CN101202616 B CN 101202616B
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- H03M1/66—Digital/analogue converters
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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Abstract
The invention discloses a processing method for a control data, which includes dividing the control data which has phase locked loop median that is higher than DAC device digit capacity into high control data and low control data, the digit capacity of which is equal to the digit capacity to the DAC device; calculating the time length respectively occupied by the corresponding pulse part after the high control data valve is added a fixed value and the corresponding non-pulse part of the high control data value in a PWM signal period; and transmitting the PWM signal to the DAC device to be processed. The invention also discloses a processing device for the control data. By adopting the invention, the functions of a high digit capacity DAC device can be realized by a low digit capacity DAC device by adopting the PWM function. The invention has the advantages of reducing cost as well as simpleness and easy application.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of processing method and control data processing unit of control data.
Background technology
In the communications field, the quality of Network Synchronization performance is great to the telecommunication service influence, the Network Synchronization performance is bad to tend to bring a series of problems, in wireless network, problems such as it is particularly important that stationary problem seems, voice quality is poor, cutting off rate height, handover success rate are low, can't insert are largely all bad relevant with the Network Synchronization performance down.
At code division multiple access (Code Division Multiple Access, CDMA)/TD SDMA (Time Division-Synchronous Code Division Multiple Access, TD-SCDMA)/Ultra-Mobile Broadband (Ultra Mobile Broadband, UMB)/Long Term Evolution (Long Term Evolution, LTE)/micro-wave access global inter communication standard wireless base station devices such as (Worldwide Interoperability for Microwave Access) in, require all to realize between the base station that precise time is synchronous, as working as global positioning system (Global Position System, GPS) system just often, the lpps phase place that requires clock phase and GPS between the different base station in the CDMA agreement is less than 3 microseconds (us), (Time Division Duplexing TDD) requires it less than 1us to the WIMAX time division duplex; When gps system is unusual (as: antenna short circuit in the receiver), the cdma base station sending and receiving stations (Base Transceiver station, BTS) require be no more than in after reference source is lost 8 hours+/-10us.At synchronizer or generally exchange the requirement that keeps for phase place when generally also existing reference source on the synchronization node of transmission equipment (as: switch) and losing, reaching better phase place under same cost situation, to keep performance all be the target that system design is pursued.
Under the gps system normal condition, system clock is by the reference clock of soft phase locked track GPS receiver output, realize required clock index easily, but under the gps system abnormal conditions, as hope long phase place hold facility can be arranged, then relatively difficult comparatively speaking, and be directly connected to the realization cost.For the phase place that improves as far as possible under the gps system abnormal conditions keeps performance, can adopt high performance local clock source, as rubidium clock and high-resolution digital analog converter (Digital Analog Converter, DAC) or Direct Digital Synthesizer (Direct Digital Synthesizer, DDS).
The system clock module block diagram of general communication equipment as shown in Figure 1, mainly comprise phase demodulation module, filtration module, DAC device and oscillator module composition, wherein, the reference clock of gps system receiver output, reference clock that transmission reports or the comprehensive regularly feed system of building (Building Integrated Time System, BITS) reference clock that provides of equipment are provided reference clock; The phase demodulation module generally is made of the special-purpose phase demodulation chip of logic OR, mainly realizes the frequency discrimination phase discrimination function of local clock and reference clock; Filtration module is handled the phase demodulation value that the phase demodulation module provides, if then finish the shake filtering of reference clock and the work that certain operations is safeguarded the aspect by processor with software realization filtering, according to the designing requirement of whole phase-locked loop, produce the control corresponding data then; The DAC device is controlled local clock (the local clock track reference all the time) according to described control data, thereby reaches the purpose that phase place keeps.
Phase place keeps performance can be reduced to following this formula:
Δp＝Δp
0+∫Afdt
Initial phase residual delta p wherein
0Can be controlled as much as possible by phase locked algorithm, and the influence that it brought under phase place maintenance situation is relatively low; Because a back ∫ Δ fdt is frequency residual error after the losing lock and the integration of time, so frequency residual error after the losing lock and compensation are main factors, the influence that influences the frequency residual error is more, as temperature, power supply noise, discriminator sensitivity, control sensitivity etc.
And have following to the factor that Δ f can exert an influence:
The performance in A, local clock source;
B, precision of phase discrimination and control precision;
C, clock filtering and maintenance algorithm.
High performance clock source is subjected to the influence of temperature and power supply noise more little, and the stability of its clock is high more, but corresponding cost also can increase greatly; Good clock source only is to realize that good phase place keeps a basis of performance, and also necessity has corresponding precision of phase discrimination and control precision, and good clock filtering matches with keeping algorithm.
In the software phase-lock loop road, the lifting of precision of phase discrimination can realize that control precision then relates to the figure place of selecting the DAC device for use by increasing the filtering time.Generally speaking, cut under the constant-temperature crystal oscillator at the SC that adopts high stability, need at least 16 DAC device could satisfy cdma base station reference source lose the desired 8 hours phase places in back remain on+/-the protocol specification requirement of 10us.
Because prior art needs the DAC device of seniority top digit to satisfy phase place and keeps performance, and the DAC device cost of seniority top digit is higher, therefore needs a kind of method when satisfying same phase place maintenance performance, reduces used device cost.
Summary of the invention
Embodiment of the invention technical problem to be solved is, a kind of processing method and control data processing unit of control data are provided, can realize adopting pulse width modulation (Pulse Width Modulation, PWM) function reduces cost with the function of the DAC device realization seniority top digit DAC device of lower-order digit.
In order to solve the problems of the technologies described above, the embodiment of the invention has proposed a kind of processing method of control data, comprising:
Obtain the control data that the phase-locked loop median is higher than the DAC figure place;
Described control data is divided into high-order control data that figure place equates with the DAC of institute figure place and figure place and described control data exceeds the low level control data that the figure place of described digital to analog converter equates;
Judge whether described low level control data value is 0; If, then send described high-order control data and handle to described digital to analog converter, obtain oscillator control signal in the described phase-locked loop; Otherwise
Calculate non-pulse part that described high-order control data value adds segment pulse corresponding behind the set-point, high-order control data value correspondence in pwm signal shared time span respectively in the cycle; , specifically comprise: introduce described pulse-width signal period T, low level control data figure place n
1, low level control data value is N; Calculate described high-order control data value and add the corresponding segment pulse in 1 back in pulse-width signal shared time span in the cycle
The non-pulse part of calculating described high-order control data value correspondence is at pulse-width signal shared time span T in the cycle
2: T
2=T-T
1
Send described pwm signal and handle, obtain oscillator control signal in the described phase-locked loop to described DAC.
Correspondingly, the embodiment of the invention also provides a kind of control data processing unit, comprising:
Control data obtains the unit, obtains the control data that the phase-locked loop median is higher than the DAC figure place;
Division unit is divided into high-order control data that figure place equates with described DAC figure place and figure place and described control data with described control data and exceeds the low level control data that the figure place of described digital to analog converter equates;
Judge performance element, judge whether described low level control data value is 0, if, then send described high-order control data and handle to described digital to analog converter, obtain oscillator control signal in the described phase-locked loop; Otherwise, triggered time length computation unit work;
The time span computing unit calculates non-pulse part that described high-order control data value adds segment pulse corresponding behind the set-point, high-order control data value correspondence in pwm signal shared time span respectively in the cycle; Described time span computing unit comprises:
Introduce the unit, introduce described pulse-width signal period T, low level control data figure place n
1, low level control data value is N;
Computing unit calculates described high-order control data value and adds the corresponding segment pulse in 1 back at pulse-width signal shared time span T in the cycle
1:
The non-pulse part of calculating described high-order control data value correspondence is at pulse-width signal shared time span T in the cycle
2:
T
2＝T-T
1；
The control signal output unit sends described pulse-width signal and handles to described DAC, obtains oscillator control signal in the described phase-locked loop.
The embodiment of the invention is divided by the control data that the phase-locked loop median is higher than DAC device figure place, be divided into the high-order control data that figure place equates with described DAC device figure place, the low level control data, calculate described high-order control data value and add segment pulse corresponding behind the set-point, the non-pulse part of high-order control data value correspondence is distinguished shared time span at pwm signal in the cycle, and send described pwm signal to described DAC device and handle, thereby realize adopting the function of PWM function, reduce cost with the DAC device realization seniority top digit DAC device of lower-order digit.
Description of drawings
Fig. 1 is a prior art system clock module block diagram;
Fig. 2 is the first embodiment schematic diagram of the processing method of control data of the present invention;
Fig. 3 is pwm signal first schematic diagram of the embodiment of the invention;
Fig. 4 is pwm signal second schematic diagram through low-pass filtering treatment of the embodiment of the invention;
Fig. 5 is the second embodiment schematic diagram of the processing method of control data of the present invention;
Fig. 6 is the first embodiment schematic diagram of control data processing unit of the present invention;
Fig. 7 is the second embodiment schematic diagram of control data processing unit of the present invention.
Embodiment
The embodiment of the invention provides a kind of processing method and control data processing unit of control data, can realize adopting the PWM function to realize the function of seniority top digit DAC device with the DAC device of lower-order digit, thereby reduce cost.
Below in conjunction with accompanying drawing, the embodiment of the invention is elaborated.
Fig. 2 is the first embodiment schematic diagram of the processing method of control data of the present invention, DAC device control data in this method after resulting phase-locked loop phase demodulation, the Filtering Processing is 16 bits (Bit), and the DAC device figure place that is used for producing the phase-locked loop oscillator control signal is 12Bit, this method is to be solved to be to realize that with the DAC device of 12Bit the phase place of the DAC device of 16Bit keeps performance, with reference to this figure, this method mainly comprises:
201, obtain the DAC device control data of the 16Bit in the phase-locked loop, for example the DAC device control data value of 16Bit is 8b05h (with a hexadecimal representation, below flow process all with this example explanation);
202, the DAC device control data of 16Bit is divided into high-order control data (12Bit), the low level control data (4Bit) that figure place equates with DAC device figure place, promptly the high-order control data of 12Bit is that the low level control data of 8b0h, 4Bit is 5h;
203, judge whether the 4Bit low level control data value of dividing in 202 is 0, if, then the high-order control data 8b0h that sends described 12Bit to described DAC device handles, obtain oscillator control signal in the described phase-locked loop, otherwise change step 204, because the low level control data value of 4Bit is 5 (with decimal representations), then carry out 204 in the step 202;
204, introducing 16 seconds pwm signal cycles (s), low level control data figure place 4, low level control data value are 5;
205, calculate high-order control data value and add the corresponding segment pulse shared time span T in pwm signal cycle 16s in 1 gained 8b1h (with hexadecimal representation) back
1:
Calculate the corresponding non-pulse part shared time span T in pwm signal cycle 16s of high-order control data value 8b0h (with hexadecimal representation)
2:
T
2＝T-T
1＝16-5＝11(s)；
So formed pwm signal can be as shown in Figure 3, wherein the segment pulse value of pwm signal be 8b1h (with hexadecimal representation) and in a PWM cycle 16s shared time span be 5s, non-pulse part value be 8b0h and in a PWM cycle 16s shared time span be 11s;
206, send the pwm signal that above-mentioned steps obtains to the DAC of described 12Bit device, the DAC device of 12Bit can produce the control signal (as: voltage-controlled signal) that is used for control generator in the phase-locked loop according to this pwm signal afterwards.
As a kind of execution mode, after step 206, also can handle described pwm signal gained analog signal to the DAC device, carry out low-pass filtering treatment (as: resistance capacitance Filtering Processing, i.e. RC Filtering Processing), specifically comprise:
A1, judge whether the modulating frequency of the analog signal of described acquisition reaches pre-set threshold, if then carry out a2;
A2, described analog signal carried out low-pass filtering treatment obtain final analog signal, can with reference to as shown in Figure 4 through the final analog signal (form of this analog signal can be the PWM form) after the RC Filtering Processing.
Implement the processing method of the control data of the embodiment of the invention as shown in Figure 2, divide by the control data that the phase-locked loop median is higher than DAC device figure place, be divided into the high-order control data that figure place equates with described DAC device figure place, the low level control data, calculate described high-order control data value and add the corresponding segment pulse in 1 back, the non-pulse part of high-order control data value correspondence is distinguished shared time span at pwm signal in the cycle, and send described pwm signal to described DAC device and handle, obtain oscillator control signal in the described phase-locked loop, thereby realize adopting the function of PWM function, reduce cost with the DAC device realization seniority top digit DAC device of lower-order digit.
Fig. 5 is the second embodiment schematic diagram of the processing method of control data of the present invention, DAC device control data in this method after resulting phase-locked loop phase demodulation, the Filtering Processing is 16Bit, and the DAC device figure place that is used for producing the phase-locked loop oscillator control signal is 8Bit, this method is to be solved to be to realize that with the DAC device of 8Bit the phase place of the DAC device of 16Bit keeps performance, with reference to this figure, this method mainly comprises:
501, obtain the DAC device control data of the 16Bit in the phase-locked loop, for example the DAC device control data value of 16Bit is 9a11h (with a hexadecimal representation, below flow process all with this example explanation);
502, the DAC device control data of 16Bit is divided into high-order control data (8Bit), the low level control data (8Bit) that figure place equates with DAC device figure place, promptly the high-order control data of 8Bit is that the low level control data of 9ah, 8Bit is 11h;
503, introduce pwm signal cycle 16s, low level control data figure place 8, low level control data value 17 (with decimal representation, hexadecimal corresponds to 11h);
504, calculate the corresponding segment pulse in high-order control data value (set-point that is used for adjusting the pwm signal duty ratio is a natural number 2) gained 9ch (with the hexadecimal representation) back that adds 2 at the shared time span T ' of pwm signal cycle 16s
1:
Wherein, 2 for being used to adjust the set-point of pwm signal duty ratio, because duty ratio equals the ratio in the shared cycle of pwm signal really of pwm signal segment pulse time span, then when the pwm signal cycle is constant, described high-order control data set-point that value adds 2 can be used as and calculates the weight of segment pulse in pwm signal shared time span in the cycle, finally obtains high-order control data value and adds the corresponding segment pulses in 2 backs at pwm signal shared time span 0.53125s in the cycle;
Calculate the corresponding non-pulse part shared time span T in pwm signal cycle 16s of high-order control data value 8b0h (with hexadecimal representation)
2:
T
2＝T-T
1′＝16-0.53125＝15.46875(s)；
So formed pwm signal can be as shown in Figure 3, wherein the segment pulse value of pwm signal be 9ch (with hexadecimal representation) and in a PWM cycle 16s shared time span be 0.53125s, non-pulse part value be 9ah and in a PWM cycle 16s shared time span be 15.46875s;
505, send the pwm signal that above-mentioned steps obtains to the DAC of described 8Bit device, the DAC device of 8Bit can produce the control signal (as: voltage-controlled signal) that is used for control generator in the phase-locked loop according to this pwm signal afterwards.
Implement the processing method of the control data of the embodiment of the invention as shown in Figure 5, divide by the control data that the phase-locked loop median is higher than DAC device figure place, be divided into the high-order control data that figure place equates with described DAC device figure place, the low level control data, calculate described high-order control data value and add the corresponding segment pulse in 2 backs, the non-pulse part of high-order control data value correspondence is distinguished shared time span at pwm signal in the cycle, and send described pwm signal to described DAC device and handle, obtain oscillator control signal in the described phase-locked loop, thereby realize adopting the function of PWM function, reduce cost with the DAC device realization seniority top digit DAC device of lower-order digit.
The following points that are worth explanation:
1, the generation of described pwm signal can realize by software, for the least possible processor resource that takies, can as far as possible the PWM modulating frequency be reduced in conjunction with the regulating cycle of phase-locked loop;
2, the generation of described pwm signal can realize by logic, and the control data that is about to the DAC device writes logic, produces pwm signal by logic, can not take processor resource like this and reaches the purpose of the pwm signal that produces the different modulating frequency;
3, the set-point that is used to adjust the pwm signal duty ratio is not limited only to natural number 2, can also be other natural numbers 3,4 or the like, all can implement according to the principle of second embodiment of the processing method of control data of the present invention.
Correspondingly, below control data processing unit of the present invention is described.
Fig. 6 is the first embodiment schematic diagram of control data processing unit of the present invention, with reference to this figure, this control data processing unit comprises that control data obtains unit 61, division unit 62, judges performance element 63, time span computing unit 64, control signal output unit 65, wherein time span computing unit 64 comprises introducing unit 641, computing unit 642, each unit connection relation and function such as following:
Control data obtains unit 61, judges that performance element 63 links to each other with division unit 62 respectively, judges that performance element 63, control signal output unit 65 link to each other with time span computing unit 64 respectively, introduces unit 641 and links to each other with computing unit 642;
Control data obtains unit 61, is used for obtaining the DAC device control data of the 16Bit of phase-locked loop, and for example the DAC device control data value of 16Bit is 8b05h (with a hexadecimal representation, below flow process all with this example explanation);
Introduce unit 641, being used to introduce 16 seconds pwm signal cycles (s), low level control data figure place 4, low level control data value is 5;
Calculate the corresponding non-pulse part shared time span T in pwm signal cycle 16s of high-order control data value 8b0h (with hexadecimal representation)
2:
T
2＝T-T
1＝16-5＝11(s)；
So formed pwm signal still can be as shown in Figure 3, wherein the segment pulse value of pwm signal be 8b1h (with hexadecimal representation) and in a PWM cycle 16s shared time span be 5s, non-pulse part value be 8b0h and in a PWM cycle 16s shared time span be 11s;
Control signal output unit 65 is used for sending resulting pwm signal to the DAC of described 12Bit device, and the DAC device of 12Bit can produce the control signal (as: voltage-controlled signal) that is used for control generator in the phase-locked loop according to this pwm signal afterwards.
Implement the control data processing unit of the embodiment of the invention as shown in Figure 6, the control data that is higher than DAC device figure place by 62 pairs of phase-locked loop medians of division unit is divided, be divided into the high-order control data that figure place equates with described DAC device figure place, the low level control data, calculate described high-order control data value by time span computing unit 64 and add the corresponding segment pulse in 1 back, the non-pulse part of high-order control data value correspondence is distinguished shared time span at pwm signal in the cycle, and send described pwm signal by control signal output unit 65 to described DAC device and handle, obtain oscillator control signal in the described phase-locked loop, thereby realize adopting the function of PWM function, reduce cost with the DAC device realization seniority top digit DAC device of lower-order digit.
Fig. 7 is the second embodiment schematic diagram of control data processing unit of the present invention, with reference to this figure, this control data processing unit comprises that control data obtains unit 71, division unit 72, time span computing unit 73, control signal output unit 74, each unit connection relation and function such as following:
Control data obtains unit 71, time span computing unit 73 links to each other with division unit 72 respectively, and time span computing unit 73 links to each other with control signal output unit 74;
Control data obtains unit 71, is used for obtaining the DAC device control data of the 16Bit of phase-locked loop, and for example the DAC device control data value of 16Bit is 9a11h (with a hexadecimal representation, below flow process all with this example explanation);
Time span computing unit 73 is used at first introducing pwm signal cycle 16s, low level control data figure place 8, low level control data value 17 (with decimal representation, hexadecimal corresponds to 11h); Secondly, calculate the corresponding segment pulse in high-order control data value (set-point that is used for adjusting the pwm signal duty ratio is a natural number 2) gained 9ch (with the hexadecimal representation) back that adds 2 at the shared time span T of pwm signal cycle 16s
1':
Wherein, 2 for being used to adjust the set-point of pwm signal duty ratio, because duty ratio equals the ratio in the shared cycle of pwm signal really of pwm signal segment pulse time span, then when the pwm signal cycle is constant, described high-order control data set-point that value adds 2 can be used as and calculates the weight of segment pulse in pwm signal shared time span in the cycle, finally obtains high-order control data value and adds the corresponding segment pulses in 2 backs at pwm signal shared time span 0.53125s in the cycle;
Calculate the corresponding non-pulse part shared time span T in pwm signal cycle 16s of high-order control data value 8b0h (with hexadecimal representation)
2:
T
2＝T-T
1′＝16-0.53125＝15.46875(s)；
So formed pwm signal still can be as shown in Figure 3, wherein the segment pulse value of pwm signal be 9ch (with hexadecimal representation) and in a PWM cycle 16s shared time span be 0.53125s, non-pulse part value be 9ah and in a PWM cycle 16s shared time span be 15.46875s;
Control signal output unit 74 is used for sending resulting pwm signal to the DAC of described 8Bit device, and the DAC device of 8Bit can produce the control signal (as: voltage-controlled signal) that is used for control generator in the phase-locked loop according to this pwm signal afterwards.
Implement the control data processing unit of the embodiment of the invention as shown in Figure 7, the control data that is higher than DAC device figure place by 72 pairs of phase-locked loop medians of division unit is divided, be divided into the high-order control data that figure place equates with described DAC device figure place, the low level control data, calculate described high-order control data value by time span computing unit 73 and add the corresponding segment pulse in 2 backs, the non-pulse part of high-order control data value correspondence is distinguished shared time span at pwm signal in the cycle, and send described pwm signal by control signal output unit 74 to described DAC device and handle, obtain oscillator control signal in the described phase-locked loop, thereby realize adopting the function of PWM function, reduce cost with the DAC device realization seniority top digit DAC device of lower-order digit.
What deserves to be explained is that described control data processing unit can be present among the DAC device, also can have (linking to each other) etc. with the separate equipment form with the DAC device.
In addition, one of ordinary skill in the art will appreciate that all or part of flow process that realizes in the foregoing description method, be to instruct relevant hardware to finish by program, described program can be stored in the computer read/write memory medium, this program can comprise the flow process as the embodiment of above-mentioned each side method when carrying out.Wherein, described storage medium can be magnetic disc, CD, read-only storage memory body (Read-Only Memory, ROM) or at random store memory body (Radom Access Memory, RAM) etc.
The above is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also are considered as protection scope of the present invention.
Claims (10)
1. the processing method of a control data is characterized in that, comprising:
Obtain the control data that the phase-locked loop median is higher than the digital to analog converter figure place;
Described control data is divided into high-order control data that figure place equates with described digital to analog converter figure place and figure place and described control data exceeds the low level control data that the figure place of described digital to analog converter equates;
Judge whether described low level control data value is 0; If, then send described high-order control data and handle to described digital to analog converter, obtain oscillator control signal in the described phase-locked loop; Otherwise
Calculate non-pulse part that described high-order control data value adds segment pulse corresponding behind the set-point, high-order control data value correspondence in pulse-width signal shared time span respectively in the cycle, specifically comprise: introduce described pulse-width signal period T, low level control data figure place n
1, low level control data value is N; Calculate described high-order control data value and add the corresponding segment pulse in 1 back in pulse-width signal shared time span in the cycle
The non-pulse part of calculating described high-order control data value correspondence is at pulse-width signal shared time span T in the cycle
2: T
2=T-T
1
Send described pulse-width signal and handle, obtain oscillator control signal in the described phase-locked loop to described digital to analog converter.
2. the processing method of control data as claimed in claim 1 is characterized in that, described set-point is 1.
3. the processing method of control data as claimed in claim 2 is characterized in that, describedly judges that whether described low level control data value is after 0, also comprises:
If, then send described high-order control data and handle to described digital to analog converter, obtain oscillator control signal in the described phase-locked loop.
4. the processing method of control data as claimed in claim 1 is characterized in that, described set-point is a natural number, and this natural number is used to adjust the duty ratio of described pulse-width signal.
5. as the processing method of each described control data in the claim 1 to 4, it is characterized in that, describedly send described pulse-width signal to described digital to analog converter and handle, obtain also comprising after the oscillator control signal in the described phase-locked loop:
Whether the modulating frequency of judging described digital to analog converter processing gained analog signal reaches pre-set threshold,
If then described analog signal is carried out low-pass filtering treatment and obtains final analog signal.
6. as the processing method of each described control data in the claim 1 to 4, it is characterized in that this method logic-based produces described pulse-width signal.
7. a control data processing unit is characterized in that, comprising:
Control data obtains the unit, obtains the control data that the phase-locked loop median is higher than the digital to analog converter figure place;
Division unit is divided into high-order control data that figure place equates with described digital to analog converter figure place and figure place and described control data with described control data and exceeds the low level control data that the figure place of described digital to analog converter equates;
Judge performance element, judge whether described low level control data value is 0, if, then send described high-order control data and handle to described digital to analog converter, obtain oscillator control signal in the described phase-locked loop; Otherwise, triggered time length computation unit work;
The time span computing unit calculates non-pulse part that described high-order control data value adds segment pulse corresponding behind the set-point, high-order control data value correspondence in pulse-width signal shared time span respectively in the cycle; Described time span computing unit comprises:
Introduce the unit, introduce described pulse-width signal period T, low level control data figure place n
1, low level control data value is N;
Computing unit calculates described high-order control data value and adds the corresponding segment pulse in 1 back at pulse-width signal shared time span T in the cycle
1:
The non-pulse part of calculating described high-order control data value correspondence is at pulse-width signal shared time span T in the cycle
2:
T
2＝T-T
1；
The control signal output unit sends described pulse-width signal and handles to described digital to analog converter, obtains oscillator control signal in the described phase-locked loop.
8. control data processing unit as claimed in claim 7 is characterized in that, described set-point is 1.
9. control data processing unit as claimed in claim 8 is characterized in that, judges performance element, judges whether described low level control data value is 0, if then send described high-order control data and handle to described digital to analog converter.
10. control data processing unit as claimed in claim 7 is characterized in that, described set-point is a natural number, and this natural number is used to adjust the duty ratio of described pulse-width signal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100324570A CN101202616B (en) | 2007-12-14 | 2007-12-14 | Method and apparatus for controlling data processing |
| PCT/CN2008/073246 WO2009076838A1 (en) | 2007-12-14 | 2008-11-28 | Control data process method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100324570A CN101202616B (en) | 2007-12-14 | 2007-12-14 | Method and apparatus for controlling data processing |
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| Publication Number | Publication Date |
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| CN101202616A CN101202616A (en) | 2008-06-18 |
| CN101202616B true CN101202616B (en) | 2011-12-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100324570A Expired - Fee Related CN101202616B (en) | 2007-12-14 | 2007-12-14 | Method and apparatus for controlling data processing |
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| Country | Link |
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| CN (1) | CN101202616B (en) |
| WO (1) | WO2009076838A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101202616B (en) * | 2007-12-14 | 2011-12-28 | 华为技术有限公司 | Method and apparatus for controlling data processing |
| CN102542528B (en) * | 2011-12-26 | 2013-10-09 | Tcl集团股份有限公司 | Image conversion processing method and system |
| CN108183763B (en) * | 2018-01-17 | 2019-06-14 | 北京深思数盾科技股份有限公司 | A kind of clock correcting method, device and system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5355098A (en) * | 1992-04-24 | 1994-10-11 | Ricoh Company, Ltd. | Phase-locked loop with memory storing control data controlling the oscillation frequency |
| CN1378739A (en) * | 1999-08-10 | 2002-11-06 | 通用仪器公司 | Method and apparatus for providing clock signal with high freuqency accuracy |
| CN1815892A (en) * | 2005-01-31 | 2006-08-09 | 瑞昱半导体股份有限公司 | Circuit for detecting phase-error and generating control signal |
| CN101039118A (en) * | 2006-03-16 | 2007-09-19 | 凌阳科技股份有限公司 | Digital simulation conversion system and method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3313998B2 (en) * | 1997-03-17 | 2002-08-12 | 日本プレシジョン・サーキッツ株式会社 | Phase locked loop |
| CN1316746C (en) * | 2003-06-24 | 2007-05-16 | 松翰科技股份有限公司 | Method and apparatus for processing digital signal |
| CN101202616B (en) * | 2007-12-14 | 2011-12-28 | 华为技术有限公司 | Method and apparatus for controlling data processing |
-
2007
- 2007-12-14 CN CN2007100324570A patent/CN101202616B/en not_active Expired - Fee Related
-
2008
- 2008-11-28 WO PCT/CN2008/073246 patent/WO2009076838A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5355098A (en) * | 1992-04-24 | 1994-10-11 | Ricoh Company, Ltd. | Phase-locked loop with memory storing control data controlling the oscillation frequency |
| CN1378739A (en) * | 1999-08-10 | 2002-11-06 | 通用仪器公司 | Method and apparatus for providing clock signal with high freuqency accuracy |
| CN1815892A (en) * | 2005-01-31 | 2006-08-09 | 瑞昱半导体股份有限公司 | Circuit for detecting phase-error and generating control signal |
| CN101039118A (en) * | 2006-03-16 | 2007-09-19 | 凌阳科技股份有限公司 | Digital simulation conversion system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101202616A (en) | 2008-06-18 |
| WO2009076838A1 (en) | 2009-06-25 |
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