CN101202616B - Method and apparatus for controlling data processing - Google Patents

Method and apparatus for controlling data processing Download PDF

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CN101202616B
CN101202616B CN2007100324570A CN200710032457A CN101202616B CN 101202616 B CN101202616 B CN 101202616B CN 2007100324570 A CN2007100324570 A CN 2007100324570A CN 200710032457 A CN200710032457 A CN 200710032457A CN 101202616 B CN101202616 B CN 101202616B
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control data
order control
value
phase
digital
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CN101202616A (en
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储育红
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/82—Digital/analogue converters with intermediate conversion to time interval
    • H03M1/822—Digital/analogue converters with intermediate conversion to time interval using pulse width modulation

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

本发明公开了一种控制数据的处理方法，包括对锁相环路中位数高于DAC器件位数的控制数据进行划分，划分为位数与所述DAC器件位数相等的高位控制数据、低位控制数据，计算所述高位控制数据值加一给定值后对应的脉冲部分、高位控制数据值对应的非脉冲部分在PWM信号周期中分别所占时间长度，并发送所述PWM信号到所述DAC器件进行处理。本发明还公开了一种控制数据处理装置。采用本发明，可实现采用PWM功能以低位数的DAC器件实现高位数DAC器件的功能，降低成本，且简单易行。

Figure 200710032457

The invention discloses a method for processing control data, which includes dividing the control data with a phase-locked loop median higher than the number of bits of a DAC device into high-bit control data whose number of bits is equal to the number of bits of the DAC device, Low-order control data, calculate the corresponding pulse part after the high-order control data value plus a given value, and the time length of the non-pulse part corresponding to the high-order control data value in the PWM signal period, and send the PWM signal to the The DAC device described above is processed. The invention also discloses a control data processing device. By adopting the present invention, the function of the high-digit DAC device can be realized by the low-digit DAC device by using the PWM function, the cost is reduced, and the method is simple and easy.

Figure 200710032457

Description

The processing method of control data and device
Technical field
The present invention relates to the communications field, relate in particular to a kind of processing method and control data processing unit of control data.
Background technology
In the communications field, the quality of Network Synchronization performance is great to the telecommunication service influence, the Network Synchronization performance is bad to tend to bring a series of problems, in wireless network, problems such as it is particularly important that stationary problem seems, voice quality is poor, cutting off rate height, handover success rate are low, can't insert are largely all bad relevant with the Network Synchronization performance down.
At code division multiple access (Code Division Multiple Access, CDMA)/TD SDMA (Time Division-Synchronous Code Division Multiple Access, TD-SCDMA)/Ultra-Mobile Broadband (Ultra Mobile Broadband, UMB)/Long Term Evolution (Long Term Evolution, LTE)/micro-wave access global inter communication standard wireless base station devices such as (Worldwide Interoperability for Microwave Access) in, require all to realize between the base station that precise time is synchronous, as working as global positioning system (Global Position System, GPS) system just often, the lpps phase place that requires clock phase and GPS between the different base station in the CDMA agreement is less than 3 microseconds (us), (Time Division Duplexing TDD) requires it less than 1us to the WIMAX time division duplex; When gps system is unusual (as: antenna short circuit in the receiver), the cdma base station sending and receiving stations (Base Transceiver station, BTS) require be no more than in after reference source is lost 8 hours+/-10us.At synchronizer or generally exchange the requirement that keeps for phase place when generally also existing reference source on the synchronization node of transmission equipment (as: switch) and losing, reaching better phase place under same cost situation, to keep performance all be the target that system design is pursued.
Under the gps system normal condition, system clock is by the reference clock of soft phase locked track GPS receiver output, realize required clock index easily, but under the gps system abnormal conditions, as hope long phase place hold facility can be arranged, then relatively difficult comparatively speaking, and be directly connected to the realization cost.For the phase place that improves as far as possible under the gps system abnormal conditions keeps performance, can adopt high performance local clock source, as rubidium clock and high-resolution digital analog converter (Digital Analog Converter, DAC) or Direct Digital Synthesizer (Direct Digital Synthesizer, DDS).
The system clock module block diagram of general communication equipment as shown in Figure 1, mainly comprise phase demodulation module, filtration module, DAC device and oscillator module composition, wherein, the reference clock of gps system receiver output, reference clock that transmission reports or the comprehensive regularly feed system of building (Building Integrated Time System, BITS) reference clock that provides of equipment are provided reference clock; The phase demodulation module generally is made of the special-purpose phase demodulation chip of logic OR, mainly realizes the frequency discrimination phase discrimination function of local clock and reference clock; Filtration module is handled the phase demodulation value that the phase demodulation module provides, if then finish the shake filtering of reference clock and the work that certain operations is safeguarded the aspect by processor with software realization filtering, according to the designing requirement of whole phase-locked loop, produce the control corresponding data then; The DAC device is controlled local clock (the local clock track reference all the time) according to described control data, thereby reaches the purpose that phase place keeps.
Phase place keeps performance can be reduced to following this formula:
Δp＝Δp 0+∫Afdt
Initial phase residual delta p wherein 0Can be controlled as much as possible by phase locked algorithm, and the influence that it brought under phase place maintenance situation is relatively low; Because a back ∫ Δ fdt is frequency residual error after the losing lock and the integration of time, so frequency residual error after the losing lock and compensation are main factors, the influence that influences the frequency residual error is more, as temperature, power supply noise, discriminator sensitivity, control sensitivity etc.
And have following to the factor that Δ f can exert an influence:
The performance in A, local clock source;
B, precision of phase discrimination and control precision;
C, clock filtering and maintenance algorithm.
High performance clock source is subjected to the influence of temperature and power supply noise more little, and the stability of its clock is high more, but corresponding cost also can increase greatly; Good clock source only is to realize that good phase place keeps a basis of performance, and also necessity has corresponding precision of phase discrimination and control precision, and good clock filtering matches with keeping algorithm.
In the software phase-lock loop road, the lifting of precision of phase discrimination can realize that control precision then relates to the figure place of selecting the DAC device for use by increasing the filtering time.Generally speaking, cut under the constant-temperature crystal oscillator at the SC that adopts high stability, need at least 16 DAC device could satisfy cdma base station reference source lose the desired 8 hours phase places in back remain on+/-the protocol specification requirement of 10us.
Because prior art needs the DAC device of seniority top digit to satisfy phase place and keeps performance, and the DAC device cost of seniority top digit is higher, therefore needs a kind of method when satisfying same phase place maintenance performance, reduces used device cost.
Summary of the invention
Embodiment of the invention technical problem to be solved is, a kind of processing method and control data processing unit of control data are provided, can realize adopting pulse width modulation (Pulse Width Modulation, PWM) function reduces cost with the function of the DAC device realization seniority top digit DAC device of lower-order digit.
In order to solve the problems of the technologies described above, the embodiment of the invention has proposed a kind of processing method of control data, comprising:
Obtain the control data that the phase-locked loop median is higher than the DAC figure place;
Described control data is divided into high-order control data that figure place equates with the DAC of institute figure place and figure place and described control data exceeds the low level control data that the figure place of described digital to analog converter equates;
Judge whether described low level control data value is 0; If, then send described high-order control data and handle to described digital to analog converter, obtain oscillator control signal in the described phase-locked loop; Otherwise
Calculate non-pulse part that described high-order control data value adds segment pulse corresponding behind the set-point, high-order control data value correspondence in pwm signal shared time span respectively in the cycle; , specifically comprise: introduce described pulse-width signal period T, low level control data figure place n 1, low level control data value is N; Calculate described high-order control data value and add the corresponding segment pulse in 1 back in pulse-width signal shared time span in the cycle
Figure GDA0000095849110000031
The non-pulse part of calculating described high-order control data value correspondence is at pulse-width signal shared time span T in the cycle 2: T 2=T-T 1
Send described pwm signal and handle, obtain oscillator control signal in the described phase-locked loop to described DAC.
Correspondingly, the embodiment of the invention also provides a kind of control data processing unit, comprising:
Control data obtains the unit, obtains the control data that the phase-locked loop median is higher than the DAC figure place;
Division unit is divided into high-order control data that figure place equates with described DAC figure place and figure place and described control data with described control data and exceeds the low level control data that the figure place of described digital to analog converter equates;
Judge performance element, judge whether described low level control data value is 0, if, then send described high-order control data and handle to described digital to analog converter, obtain oscillator control signal in the described phase-locked loop; Otherwise, triggered time length computation unit work;
The time span computing unit calculates non-pulse part that described high-order control data value adds segment pulse corresponding behind the set-point, high-order control data value correspondence in pwm signal shared time span respectively in the cycle; Described time span computing unit comprises:
Introduce the unit, introduce described pulse-width signal period T, low level control data figure place n 1, low level control data value is N;
Computing unit calculates described high-order control data value and adds the corresponding segment pulse in 1 back at pulse-width signal shared time span T in the cycle 1:
T 1 = N 2 n 1 × T ;
The non-pulse part of calculating described high-order control data value correspondence is at pulse-width signal shared time span T in the cycle 2:
T 2＝T-T 1；
The control signal output unit sends described pulse-width signal and handles to described DAC, obtains oscillator control signal in the described phase-locked loop.
The embodiment of the invention is divided by the control data that the phase-locked loop median is higher than DAC device figure place, be divided into the high-order control data that figure place equates with described DAC device figure place, the low level control data, calculate described high-order control data value and add segment pulse corresponding behind the set-point, the non-pulse part of high-order control data value correspondence is distinguished shared time span at pwm signal in the cycle, and send described pwm signal to described DAC device and handle, thereby realize adopting the function of PWM function, reduce cost with the DAC device realization seniority top digit DAC device of lower-order digit.
Description of drawings
Fig. 1 is a prior art system clock module block diagram;
Fig. 2 is the first embodiment schematic diagram of the processing method of control data of the present invention;
Fig. 3 is pwm signal first schematic diagram of the embodiment of the invention;
Fig. 4 is pwm signal second schematic diagram through low-pass filtering treatment of the embodiment of the invention;
Fig. 5 is the second embodiment schematic diagram of the processing method of control data of the present invention;
Fig. 6 is the first embodiment schematic diagram of control data processing unit of the present invention;
Fig. 7 is the second embodiment schematic diagram of control data processing unit of the present invention.
Embodiment
The embodiment of the invention provides a kind of processing method and control data processing unit of control data, can realize adopting the PWM function to realize the function of seniority top digit DAC device with the DAC device of lower-order digit, thereby reduce cost.
Below in conjunction with accompanying drawing, the embodiment of the invention is elaborated.
Fig. 2 is the first embodiment schematic diagram of the processing method of control data of the present invention, DAC device control data in this method after resulting phase-locked loop phase demodulation, the Filtering Processing is 16 bits (Bit), and the DAC device figure place that is used for producing the phase-locked loop oscillator control signal is 12Bit, this method is to be solved to be to realize that with the DAC device of 12Bit the phase place of the DAC device of 16Bit keeps performance, with reference to this figure, this method mainly comprises:
201, obtain the DAC device control data of the 16Bit in the phase-locked loop, for example the DAC device control data value of 16Bit is 8b05h (with a hexadecimal representation, below flow process all with this example explanation);
202, the DAC device control data of 16Bit is divided into high-order control data (12Bit), the low level control data (4Bit) that figure place equates with DAC device figure place, promptly the high-order control data of 12Bit is that the low level control data of 8b0h, 4Bit is 5h;
203, judge whether the 4Bit low level control data value of dividing in 202 is 0, if, then the high-order control data 8b0h that sends described 12Bit to described DAC device handles, obtain oscillator control signal in the described phase-locked loop, otherwise change step 204, because the low level control data value of 4Bit is 5 (with decimal representations), then carry out 204 in the step 202;
204, introducing 16 seconds pwm signal cycles (s), low level control data figure place 4, low level control data value are 5;
205, calculate high-order control data value and add the corresponding segment pulse shared time span T in pwm signal cycle 16s in 1 gained 8b1h (with hexadecimal representation) back 1:
T 1 = N 2 n 1 × T = 5 2 4 × 16 = 5 ( s ) ;
Calculate the corresponding non-pulse part shared time span T in pwm signal cycle 16s of high-order control data value 8b0h (with hexadecimal representation) 2:
T 2＝T-T 1＝16-5＝11(s)；
So formed pwm signal can be as shown in Figure 3, wherein the segment pulse value of pwm signal be 8b1h (with hexadecimal representation) and in a PWM cycle 16s shared time span be 5s, non-pulse part value be 8b0h and in a PWM cycle 16s shared time span be 11s;
206, send the pwm signal that above-mentioned steps obtains to the DAC of described 12Bit device, the DAC device of 12Bit can produce the control signal (as: voltage-controlled signal) that is used for control generator in the phase-locked loop according to this pwm signal afterwards.
As a kind of execution mode, after step 206, also can handle described pwm signal gained analog signal to the DAC device, carry out low-pass filtering treatment (as: resistance capacitance Filtering Processing, i.e. RC Filtering Processing), specifically comprise:
A1, judge whether the modulating frequency of the analog signal of described acquisition reaches pre-set threshold, if then carry out a2;
A2, described analog signal carried out low-pass filtering treatment obtain final analog signal, can with reference to as shown in Figure 4 through the final analog signal (form of this analog signal can be the PWM form) after the RC Filtering Processing.
Implement the processing method of the control data of the embodiment of the invention as shown in Figure 2, divide by the control data that the phase-locked loop median is higher than DAC device figure place, be divided into the high-order control data that figure place equates with described DAC device figure place, the low level control data, calculate described high-order control data value and add the corresponding segment pulse in 1 back, the non-pulse part of high-order control data value correspondence is distinguished shared time span at pwm signal in the cycle, and send described pwm signal to described DAC device and handle, obtain oscillator control signal in the described phase-locked loop, thereby realize adopting the function of PWM function, reduce cost with the DAC device realization seniority top digit DAC device of lower-order digit.
Fig. 5 is the second embodiment schematic diagram of the processing method of control data of the present invention, DAC device control data in this method after resulting phase-locked loop phase demodulation, the Filtering Processing is 16Bit, and the DAC device figure place that is used for producing the phase-locked loop oscillator control signal is 8Bit, this method is to be solved to be to realize that with the DAC device of 8Bit the phase place of the DAC device of 16Bit keeps performance, with reference to this figure, this method mainly comprises:
501, obtain the DAC device control data of the 16Bit in the phase-locked loop, for example the DAC device control data value of 16Bit is 9a11h (with a hexadecimal representation, below flow process all with this example explanation);
502, the DAC device control data of 16Bit is divided into high-order control data (8Bit), the low level control data (8Bit) that figure place equates with DAC device figure place, promptly the high-order control data of 8Bit is that the low level control data of 9ah, 8Bit is 11h;
503, introduce pwm signal cycle 16s, low level control data figure place 8, low level control data value 17 (with decimal representation, hexadecimal corresponds to 11h);
504, calculate the corresponding segment pulse in high-order control data value (set-point that is used for adjusting the pwm signal duty ratio is a natural number 2) gained 9ch (with the hexadecimal representation) back that adds 2 at the shared time span T ' of pwm signal cycle 16s 1:
T 1 = N 2 n 1 × T = 17 2 8 × 16 = 1.0625 ( s ) ,
Wherein, 2 for being used to adjust the set-point of pwm signal duty ratio, because duty ratio equals the ratio in the shared cycle of pwm signal really of pwm signal segment pulse time span, then when the pwm signal cycle is constant, described high-order control data set-point that value adds 2 can be used as and calculates the weight of segment pulse in pwm signal shared time span in the cycle, finally obtains high-order control data value and adds the corresponding segment pulses in 2 backs at pwm signal shared time span 0.53125s in the cycle;
Calculate the corresponding non-pulse part shared time span T in pwm signal cycle 16s of high-order control data value 8b0h (with hexadecimal representation) 2:
T 2＝T-T 1′＝16-0.53125＝15.46875(s)；
So formed pwm signal can be as shown in Figure 3, wherein the segment pulse value of pwm signal be 9ch (with hexadecimal representation) and in a PWM cycle 16s shared time span be 0.53125s, non-pulse part value be 9ah and in a PWM cycle 16s shared time span be 15.46875s;
505, send the pwm signal that above-mentioned steps obtains to the DAC of described 8Bit device, the DAC device of 8Bit can produce the control signal (as: voltage-controlled signal) that is used for control generator in the phase-locked loop according to this pwm signal afterwards.
Implement the processing method of the control data of the embodiment of the invention as shown in Figure 5, divide by the control data that the phase-locked loop median is higher than DAC device figure place, be divided into the high-order control data that figure place equates with described DAC device figure place, the low level control data, calculate described high-order control data value and add the corresponding segment pulse in 2 backs, the non-pulse part of high-order control data value correspondence is distinguished shared time span at pwm signal in the cycle, and send described pwm signal to described DAC device and handle, obtain oscillator control signal in the described phase-locked loop, thereby realize adopting the function of PWM function, reduce cost with the DAC device realization seniority top digit DAC device of lower-order digit.
The following points that are worth explanation:
1, the generation of described pwm signal can realize by software, for the least possible processor resource that takies, can as far as possible the PWM modulating frequency be reduced in conjunction with the regulating cycle of phase-locked loop;
2, the generation of described pwm signal can realize by logic, and the control data that is about to the DAC device writes logic, produces pwm signal by logic, can not take processor resource like this and reaches the purpose of the pwm signal that produces the different modulating frequency;
3, the set-point that is used to adjust the pwm signal duty ratio is not limited only to natural number 2, can also be other natural numbers 3,4 or the like, all can implement according to the principle of second embodiment of the processing method of control data of the present invention.
Correspondingly, below control data processing unit of the present invention is described.
Fig. 6 is the first embodiment schematic diagram of control data processing unit of the present invention, with reference to this figure, this control data processing unit comprises that control data obtains unit 61, division unit 62, judges performance element 63, time span computing unit 64, control signal output unit 65, wherein time span computing unit 64 comprises introducing unit 641, computing unit 642, each unit connection relation and function such as following:
Control data obtains unit 61, judges that performance element 63 links to each other with division unit 62 respectively, judges that performance element 63, control signal output unit 65 link to each other with time span computing unit 64 respectively, introduces unit 641 and links to each other with computing unit 642;
Control data obtains unit 61, is used for obtaining the DAC device control data of the 16Bit of phase-locked loop, and for example the DAC device control data value of 16Bit is 8b05h (with a hexadecimal representation, below flow process all with this example explanation);
Division unit 62, be used for the DAC device control data of 16Bit is divided into high-order control data (12Bit), the low level control data (4Bit) that figure place equates with DAC device figure place, promptly the high-order control data of 12Bit is that the low level control data of 8b0h, 4Bit is 5h;
Judge performance element 63, be used to judge whether the 4Bit low level control data value of being divided is 0, if, then the high-order control data 8b0h that sends described 12Bit to described DAC device handles, obtain oscillator control signal in the described phase-locked loop, otherwise 64 work of triggered time length computation unit;
Introduce unit 641, being used to introduce 16 seconds pwm signal cycles (s), low level control data figure place 4, low level control data value is 5;
Computing unit 642 is used for calculating high-order control data value and adds the corresponding segment pulse in 1 gained 8b1h (with hexadecimal representation) back at the shared time span T of pwm signal cycle 16s 1:
T 1 = N 2 n 1 × T = 5 2 4 × 16 = 5 ( s ) ;
Calculate the corresponding non-pulse part shared time span T in pwm signal cycle 16s of high-order control data value 8b0h (with hexadecimal representation) 2:
T 2＝T-T 1＝16-5＝11(s)；
So formed pwm signal still can be as shown in Figure 3, wherein the segment pulse value of pwm signal be 8b1h (with hexadecimal representation) and in a PWM cycle 16s shared time span be 5s, non-pulse part value be 8b0h and in a PWM cycle 16s shared time span be 11s;
Control signal output unit 65 is used for sending resulting pwm signal to the DAC of described 12Bit device, and the DAC device of 12Bit can produce the control signal (as: voltage-controlled signal) that is used for control generator in the phase-locked loop according to this pwm signal afterwards.
Implement the control data processing unit of the embodiment of the invention as shown in Figure 6, the control data that is higher than DAC device figure place by 62 pairs of phase-locked loop medians of division unit is divided, be divided into the high-order control data that figure place equates with described DAC device figure place, the low level control data, calculate described high-order control data value by time span computing unit 64 and add the corresponding segment pulse in 1 back, the non-pulse part of high-order control data value correspondence is distinguished shared time span at pwm signal in the cycle, and send described pwm signal by control signal output unit 65 to described DAC device and handle, obtain oscillator control signal in the described phase-locked loop, thereby realize adopting the function of PWM function, reduce cost with the DAC device realization seniority top digit DAC device of lower-order digit.
Fig. 7 is the second embodiment schematic diagram of control data processing unit of the present invention, with reference to this figure, this control data processing unit comprises that control data obtains unit 71, division unit 72, time span computing unit 73, control signal output unit 74, each unit connection relation and function such as following:
Control data obtains unit 71, time span computing unit 73 links to each other with division unit 72 respectively, and time span computing unit 73 links to each other with control signal output unit 74;
Control data obtains unit 71, is used for obtaining the DAC device control data of the 16Bit of phase-locked loop, and for example the DAC device control data value of 16Bit is 9a11h (with a hexadecimal representation, below flow process all with this example explanation);
Division unit 72, be used for the DAC device control data of 16Bit is divided into high-order control data (8Bit), the low level control data (8Bit) that figure place equates with DAC device figure place, promptly the high-order control data of 8Bit is that the low level control data of 9ah, 8Bit is 11h;
Time span computing unit 73 is used at first introducing pwm signal cycle 16s, low level control data figure place 8, low level control data value 17 (with decimal representation, hexadecimal corresponds to 11h); Secondly, calculate the corresponding segment pulse in high-order control data value (set-point that is used for adjusting the pwm signal duty ratio is a natural number 2) gained 9ch (with the hexadecimal representation) back that adds 2 at the shared time span T of pwm signal cycle 16s 1':
T 1 = N 2 n 1 × T = 17 2 8 × 16 = 1.0625 ( s ) ,
Wherein, 2 for being used to adjust the set-point of pwm signal duty ratio, because duty ratio equals the ratio in the shared cycle of pwm signal really of pwm signal segment pulse time span, then when the pwm signal cycle is constant, described high-order control data set-point that value adds 2 can be used as and calculates the weight of segment pulse in pwm signal shared time span in the cycle, finally obtains high-order control data value and adds the corresponding segment pulses in 2 backs at pwm signal shared time span 0.53125s in the cycle;
Calculate the corresponding non-pulse part shared time span T in pwm signal cycle 16s of high-order control data value 8b0h (with hexadecimal representation) 2:
T 2＝T-T 1′＝16-0.53125＝15.46875(s)；
So formed pwm signal still can be as shown in Figure 3, wherein the segment pulse value of pwm signal be 9ch (with hexadecimal representation) and in a PWM cycle 16s shared time span be 0.53125s, non-pulse part value be 9ah and in a PWM cycle 16s shared time span be 15.46875s;
Control signal output unit 74 is used for sending resulting pwm signal to the DAC of described 8Bit device, and the DAC device of 8Bit can produce the control signal (as: voltage-controlled signal) that is used for control generator in the phase-locked loop according to this pwm signal afterwards.
Implement the control data processing unit of the embodiment of the invention as shown in Figure 7, the control data that is higher than DAC device figure place by 72 pairs of phase-locked loop medians of division unit is divided, be divided into the high-order control data that figure place equates with described DAC device figure place, the low level control data, calculate described high-order control data value by time span computing unit 73 and add the corresponding segment pulse in 2 backs, the non-pulse part of high-order control data value correspondence is distinguished shared time span at pwm signal in the cycle, and send described pwm signal by control signal output unit 74 to described DAC device and handle, obtain oscillator control signal in the described phase-locked loop, thereby realize adopting the function of PWM function, reduce cost with the DAC device realization seniority top digit DAC device of lower-order digit.
What deserves to be explained is that described control data processing unit can be present among the DAC device, also can have (linking to each other) etc. with the separate equipment form with the DAC device.
In addition, one of ordinary skill in the art will appreciate that all or part of flow process that realizes in the foregoing description method, be to instruct relevant hardware to finish by program, described program can be stored in the computer read/write memory medium, this program can comprise the flow process as the embodiment of above-mentioned each side method when carrying out.Wherein, described storage medium can be magnetic disc, CD, read-only storage memory body (Read-Only Memory, ROM) or at random store memory body (Radom Access Memory, RAM) etc.
The above is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also are considered as protection scope of the present invention.

Claims (10)

1.一种控制数据的处理方法，其特征在于，包括：1. A method for processing control data, comprising: 获得锁相环路中位数高于数模转换器位数的控制数据；Obtain control data with a median of the phase-locked loop higher than the digit of the digital-to-analog converter; 将所述控制数据划分为位数与所述数模转换器位数相等的高位控制数据、以及位数与所述控制数据超出所述数模转换器的位数相等的低位控制数据；dividing the control data into high-order control data having a number of bits equal to the number of bits of the digital-to-analog converter, and low-order control data having a number of bits equal to the number of bits that the control data exceeds the number of bits of the digital-to-analog converter; 判断所述低位控制数据值是否为0；若是，则向所述数模转换器发送所述高位控制数据进行处理，得到所述锁相环路中振荡器控制信号；否则Judging whether the low-order control data value is 0; if so, sending the high-order control data to the digital-to-analog converter for processing, and obtaining the oscillator control signal in the phase-locked loop; otherwise 计算所述高位控制数据值加一给定值后对应的脉冲部分、高位控制数据值对应的非脉冲部分在脉宽调制信号周期中分别所占时间长度，具体包括：引入所述脉宽调制信号周期T、低位控制数据位数n1、低位控制数据值为N；计算所述高位控制数据值加1后对应的脉冲部分在脉宽调制信号周期中所占时间长度
Figure FDA0000095849100000011
计算所述高位控制数据值对应的非脉冲部分在脉宽调制信号周期中所占时间长度T2：T2＝T-T1；Calculating the time lengths of the pulse part corresponding to the high-order control data value plus a given value and the non-pulse part corresponding to the high-order control data value in the pulse width modulation signal cycle, specifically including: introducing the pulse width modulation signal Period T, the number of bits of low-order control data n 1 , and the value of low-order control data are N; calculate the time length of the pulse part corresponding to the value of the high-order control data plus 1 in the pulse width modulation signal cycle
Figure FDA0000095849100000011
Calculate the time length T 2 occupied by the non-pulse part corresponding to the high-order control data value in the pulse width modulation signal period: T 2 = TT 1 ; 发送所述脉宽调制信号到所述数模转换器进行处理，得到所述锁相环路中振荡器控制信号。Sending the pulse width modulation signal to the digital-to-analog converter for processing to obtain an oscillator control signal in the phase-locked loop. 2.如权利要求1所述的控制数据的处理方法，其特征在于，所述给定值为1。2. The method for processing control data according to claim 1, wherein the given value is 1. 3.如权利要求2所述的控制数据的处理方法，其特征在于，所述判断所述低位控制数据值是否为0之后，还包括：3. The processing method of control data as claimed in claim 2, characterized in that, after said judging whether said low control data value is 0, further comprising: 若是，则向所述数模转换器发送所述高位控制数据进行处理，得到所述锁相环路中振荡器控制信号。If so, send the high-order control data to the digital-to-analog converter for processing, and obtain an oscillator control signal in the phase-locked loop. 4.如权利要求1所述的控制数据的处理方法，其特征在于，所述给定值为一自然数，该自然数用于调整所述脉宽调制信号的占空比。4. The method for processing control data according to claim 1, wherein the given value is a natural number, and the natural number is used to adjust the duty ratio of the pulse width modulation signal. 5.如权利要求1至4中任一项所述的控制数据的处理方法，其特征在于，所述向所述数模转换器发送所述脉宽调制信号进行处理，得到所述锁相环路中振荡器控制信号之后还包括：5. The method for processing control data as claimed in any one of claims 1 to 4, wherein said sending said pulse width modulation signal to said digital-to-analog converter is processed to obtain said phase-locked loop After the oscillator control signal in the road also include: 判断所述数模转换器处理所得模拟信号的调制频率是否达到预先设定的阈值，judging whether the modulation frequency of the analog signal processed by the digital-to-analog converter reaches a preset threshold, 若是，则对所述模拟信号进行低通滤波处理得到最终的模拟信号。If yes, low-pass filtering is performed on the analog signal to obtain a final analog signal. 6.如权利要求1至4中任一项所述的控制数据的处理方法，其特征在于，该方法基于逻辑产生所述脉宽调制信号。6. The method for processing control data according to any one of claims 1 to 4, characterized in that the method generates the pulse width modulation signal based on logic. 7.一种控制数据处理装置，其特征在于，包括：7. A control data processing device, characterized in that it comprises: 控制数据获得单元，获得锁相环路中位数高于数模转换器位数的控制数据；A control data obtaining unit, which obtains control data whose median value of the phase-locked loop is higher than that of the digital-to-analog converter; 划分单元，将所述控制数据划分为位数与所述数模转换器位数相等的高位控制数据、以及位数与所述控制数据超出所述数模转换器的位数相等的低位控制数据；a division unit for dividing the control data into high-order control data whose number of bits is equal to the number of bits of the digital-to-analog converter, and low-order control data whose number of bits is equal to the number of bits that the control data exceeds the number of bits of the digital-to-analog converter ; 判断执行单元，判断所述低位控制数据值是否为0，若是，则向所述数模转换器发送所述高位控制数据进行处理，得到所述锁相环路中振荡器控制信号；否则，触发时间长度计算单元工作；Judging the execution unit, judging whether the low-order control data value is 0, if so, sending the high-order control data to the digital-to-analog converter for processing, and obtaining the oscillator control signal in the phase-locked loop; otherwise, triggering Time length calculation unit work; 时间长度计算单元，计算所述高位控制数据值加一给定值后对应的脉冲部分、高位控制数据值对应的非脉冲部分在脉宽调制信号周期中分别所占时间长度；所述时间长度计算单元包括：A time length calculation unit, which calculates the corresponding pulse part after the high-order control data value plus a given value, and the time length corresponding to the non-pulse part corresponding to the high-order control data value in the pulse width modulation signal cycle; the time length calculation Units include: 引入单元，引入所述脉宽调制信号周期T、低位控制数据位数n1、低位控制数据值为N；An introduction unit, which introduces the pulse width modulation signal period T, the number of bits n 1 of the low-order control data, and the value of the low-order control data N; 计算单元，计算所述高位控制数据值加1后对应的脉冲部分在脉宽调制信号周期中所占时间长度T1：The calculation unit calculates the length T 1 of the corresponding pulse part in the pulse width modulation signal cycle after the high-order control data value is added by 1: TT 11 == NN 22 nno 11 ×× TT ;; 计算所述高位控制数据值对应的非脉冲部分在脉宽调制信号周期中所占时间长度T2：Calculate the time length T 2 occupied by the non-pulse part corresponding to the high-order control data value in the pulse width modulation signal cycle: T2＝T-T1；T 2 =TT 1 ; 控制信号输出单元，发送所述脉宽调制信号到所述数模转换器进行处理，得到所述锁相环路中振荡器控制信号。The control signal output unit sends the pulse width modulation signal to the digital-to-analog converter for processing, and obtains the oscillator control signal in the phase-locked loop. 8.如权利要求7所述的控制数据处理装置，其特征在于，所述给定值为1。8. The control data processing device according to claim 7, wherein the given value is 1. 9.如权利要求8所述的控制数据处理装置，其特征在于，判断执行单元，判断所述低位控制数据值是否为0，若是，则发送所述高位控制数据到所述数模转换器进行处理。9. The control data processing device according to claim 8, wherein the judgment execution unit judges whether the low-order control data value is 0, and if so, sends the high-order control data to the digital-to-analog converter for processing. deal with. 10.如权利要求7所述的控制数据处理装置，其特征在于，所述给定值为一自然数，该自然数用于调整所述脉宽调制信号的占空比。10. The control data processing device according to claim 7, wherein the given value is a natural number, and the natural number is used to adjust the duty cycle of the pulse width modulation signal.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355098A (en) * 1992-04-24 1994-10-11 Ricoh Company, Ltd. Phase-locked loop with memory storing control data controlling the oscillation frequency
CN1378739A (en) * 1999-08-10 2002-11-06 通用仪器公司 Method and apparatus for providing clock signal with high freuqency accuracy
CN1815892A (en) * 2005-01-31 2006-08-09 瑞昱半导体股份有限公司 A circuit that detects phase errors and generates control signals
CN101039118A (en) * 2006-03-16 2007-09-19 凌阳科技股份有限公司 A digital-to-analog conversion system and method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3313998B2 (en) * 1997-03-17 2002-08-12 日本プレシジョン・サーキッツ株式会社 Phase locked loop
CN1316746C (en) * 2003-06-24 2007-05-16 松翰科技股份有限公司 Method and device for digital signal processing
CN101202616B (en) * 2007-12-14 2011-12-28 华为技术有限公司 Method and apparatus for controlling data processing

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355098A (en) * 1992-04-24 1994-10-11 Ricoh Company, Ltd. Phase-locked loop with memory storing control data controlling the oscillation frequency
CN1378739A (en) * 1999-08-10 2002-11-06 通用仪器公司 Method and apparatus for providing clock signal with high freuqency accuracy
CN1815892A (en) * 2005-01-31 2006-08-09 瑞昱半导体股份有限公司 A circuit that detects phase errors and generates control signals
CN101039118A (en) * 2006-03-16 2007-09-19 凌阳科技股份有限公司 A digital-to-analog conversion system and method

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