CN221227736U - Clock synchronization device and transceiver - Google Patents
Clock synchronization device and transceiver Download PDFInfo
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- CN221227736U CN221227736U CN202323018475.7U CN202323018475U CN221227736U CN 221227736 U CN221227736 U CN 221227736U CN 202323018475 U CN202323018475 U CN 202323018475U CN 221227736 U CN221227736 U CN 221227736U
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 31
- 239000013078 crystal Substances 0.000 claims abstract description 15
- 238000004891 communication Methods 0.000 abstract description 3
- 238000005457 optimization Methods 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 2
- 230000006870 function Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000011084 recovery Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- HJVCHYDYCYBBQX-HLTLHRPFSA-N (2s,3s,4e,6e,8s,9s)-3-amino-9-methoxy-2,6,8-trimethyl-10-phenyldeca-4,6-dienoic acid Chemical compound OC(=O)[C@@H](C)[C@@H](N)/C=C/C(/C)=C/[C@H](C)[C@@H](OC)CC1=CC=CC=C1 HJVCHYDYCYBBQX-HLTLHRPFSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- PBLZLIFKVPJDCO-UHFFFAOYSA-N omega-Aminododecanoic acid Natural products NCCCCCCCCCCCC(O)=O PBLZLIFKVPJDCO-UHFFFAOYSA-N 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
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Abstract
The utility model relates to the technical field of wireless communication and discloses a clock synchronization device and a transceiver, wherein the device comprises a first phase-locked loop circuit, a second phase-locked loop circuit, a digital-to-analog conversion circuit, a field programmable gate array and a voltage-controlled crystal oscillator; the first phase-locked loop circuit, the second phase-locked loop circuit and the digital-to-analog conversion circuit are sequentially connected; the second phase-locked loop circuit is connected with the voltage-controlled crystal oscillator; the field programmable gate array is respectively connected with the first phase-locked loop circuit, the second phase-locked loop circuit and the digital-to-analog conversion circuit. The utility model realizes SyncE frequency synchronization and 1588V2 time synchronization of data flow between the digital phase-locked loop circuit and the baseband processing unit, ensures that the synchronization precision can reach higher level, realizes the integration phase noise optimization of millimeter wave frequency band through the analog phase-locked loop circuit and the radio frequency phase-locked loop circuit, and meets the application requirement of millimeter waves.
Description
Technical Field
The present utility model relates to the field of wireless communications technologies, and in particular, to a clock synchronization device and a transceiver.
Background
With the evolution of the frequency spectrum, millimeter waves such as n257/n258 are increasingly focused, but in the application scenario of the current open radio access network ORAN, the radio frequency unit mostly adopts the Sub-6GHz frequency band, and although the Sub-6GHz frequency band has extremely strong signal penetrating power, the data transmission rate is lower than that of the millimeter waves, and with the gradual increase of the capacity requirement of the wireless communication system, the application of the millimeter waves gradually enters the field of view of the public, but the radio frequency front end developed and applied to the millimeter wave frequency band is less.
In addition, the current radio frequency front end supporting the millimeter wave frequency band has a certain problem, on one hand, the current radio frequency front end cannot meet the timing standard requirement defined by ORAN organization, namely cannot simultaneously meet the IEEE clock frequency synchronization protocol 1588V2 and the synchronous Ethernet SyncE; on the other hand, the existing radio frequency front end has insufficient timing precision and frequency synchronization precision in the millimeter wave frequency band, so that a clock circuit scheme capable of meeting the timing precision of the NS level and supporting the high performance of the millimeter wave frequency band is needed.
Disclosure of utility model
In order to solve the technical problems, the utility model provides a clock synchronization device and a transceiver, which can solve the problem that the existing radio frequency unit cannot meet the high-precision time service requirement of the current equipment, so as to realize a clock synchronization scheme with high synchronization precision, high performance and low phase noise.
In a first aspect, the present utility model provides a clock synchronizing device, the device comprising:
the digital-to-analog conversion circuit comprises a first phase-locked loop circuit, a second phase-locked loop circuit, a digital-to-analog conversion circuit, a field programmable gate array and a voltage-controlled crystal oscillator;
The first phase-locked loop circuit, the second phase-locked loop circuit and the digital-to-analog conversion circuit are sequentially connected;
The second phase-locked loop circuit is connected with the voltage-controlled crystal oscillator;
The field programmable gate array is respectively connected with the first phase-locked loop circuit, the second phase-locked loop circuit and the digital-to-analog conversion circuit.
Further, the second phase-locked loop circuit comprises a first sub-phase-locked loop circuit and a second sub-phase-locked loop circuit;
The first sub phase-locked loop circuit is respectively connected with the second sub phase-locked loop circuit, the digital-to-analog conversion circuit and the voltage-controlled crystal oscillator.
Further, the second phase-locked loop circuit comprises a first sub-phase-locked loop circuit and a second sub-phase-locked loop circuit;
The first sub phase-locked loop circuit is respectively connected with the second sub phase-locked loop circuit and the voltage-controlled crystal oscillator;
The second sub phase-locked loop circuit is connected with the digital-to-analog conversion circuit.
Further, the first phase-locked loop circuit is a digital phase-locked loop circuit, and the second phase-locked loop circuit is an analog phase-locked loop circuit.
Further, the first sub-phase-locked loop circuit is an analog phase-locked loop circuit, and the second sub-phase-locked loop circuit is a radio frequency phase-locked loop circuit.
In a second aspect, the present utility model provides a transceiver comprising clock synchronizing means as described above.
The utility model provides a clock synchronization device and a transceiver. Through the clock synchronization device, the utility model can realize high-precision SyncE frequency synchronization and 1588V2 time synchronization of data streams, and also realize low-phase noise output of millimeter wave frequency bands, thereby meeting the application requirements of millimeter waves.
Drawings
FIG. 1 is a schematic diagram of a clock synchronization device according to an embodiment of the present utility model;
FIG. 2 is a schematic diagram of a data transmission structure of a clock synchronization device according to an embodiment of the present utility model;
FIG. 3 is a schematic diagram of a third configuration of a clock synchronization device according to an embodiment of the present utility model;
fig. 4 is a schematic diagram of a fourth configuration of a clock synchronization device according to an embodiment of the present utility model.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments of the present utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
Before the technical scheme of the utility model is explained, technical keywords related to the technical scheme are explained, and the technical scheme comprises the following steps: ORAN: an open wireless access network; 1588V2: an IEEE clock frequency synchronization protocol; syncE: a synchronous ethernet network; and (3) FPGA: a field programmable gate array; APLL: an analog phase-locked loop circuit; DPLL: a digital phase-locked loop circuit; RFPLL: a radio frequency phase locked loop circuit; ADDA: a digital-to-analog conversion circuit; VCXO: a voltage controlled crystal oscillator; VCO: a voltage controlled oscillator; BBU: a baseband processing unit; buffer: a memory; FOM: quality factor.
Referring to fig. 1, a clock synchronization apparatus according to a first embodiment of the present utility model includes: the digital-to-analog conversion circuit comprises a first phase-locked loop circuit 1, a second phase-locked loop circuit 2, a digital-to-analog conversion circuit 3, a field programmable gate array 4 and a voltage-controlled crystal oscillator 5, wherein the first phase-locked loop circuit 1, the second phase-locked loop circuit 2 and the digital-to-analog conversion circuit 3 are sequentially connected, the field programmable gate array 4 is respectively connected with the first phase-locked loop circuit 1, the second phase-locked loop circuit 2 and the digital-to-analog conversion circuit 3, and the second phase-locked loop circuit 2 is connected with the voltage-controlled crystal oscillator 5.
Referring to fig. 2, in the present embodiment, the first phase-locked loop circuit 1 is a digital phase-locked loop circuit DPLL, the second phase-locked loop circuit 2 is an analog phase-locked loop circuit APLL, the digital-to-analog conversion circuit 3 is an add conversion circuit, the field programmable gate array 4 is an FPGA chip, and the clock synchronization device can achieve time synchronization and frequency synchronization between the FPGA and an external baseband processing unit BBU. Specifically, the field programmable gate array 4, i.e. the FPGA chip, receives the data stream sent from the external baseband processing unit BBU.
In this embodiment, the device uses a CDR module inside the FPGA chip to perform clock recovery on the data stream, where the CDR module is an important module for generating a recovered clock, and the clock recovery mainly extracts clock information embedded in the data from the received non-return-to-zero code, and generally the CDR is a feedback loop with an oscillator, and tracks the embedded clock in the input data by adjusting the phase of the oscillating clock through the loop. The FPGA chip sends a recovered clock, i.e. a recovered clock, from the data stream of the BBU to the first pll circuit 1, i.e. the DPLL, and the DPLL uses the recovered clock as a reference clock to be provided to the FPGA chip and the second pll circuit 2, i.e. the APLL, respectively, and simultaneously, the APLL provides the reference clock to the digital-to-analog conversion circuit 3, i.e. the add circuit, which performs digital-to-analog conversion processing on the data stream from the FPGA chip after obtaining the reference clock, and the APLL also provides a main working clock to the FPAG chip as a working clock of a logic circuit inside the FPAG chip, that is, in this embodiment, by using the recovered clock from the data stream transmitted from the external BBU as the reference clock of the device, the device can realize time homology, thereby realizing synchronous sync frequency between the FPGA chip and the BBU, and the synchronous precision of which can reach the high precision level of ppb.
In addition, the first phase-locked loop circuit 1, namely the DPLL, also outputs 1588V2 working clock to a logic processing part of the FPGA chip, the FPGA chip adopts the working clock to make a time stamp on the MAC layer, and time synchronization between the FPGA chip and the BBU is realized by exchanging 1588 messages with the BBU, and the synchronization precision can reach a high precision level of sub microsecond level. That is, in this embodiment, the reference clock and the 1588 working clock are provided for the FPGA chip through the DPLL, so that SyncE frequency synchronization and 1588V2 time synchronization of data stream transmission between the FPAG chip and the BBU are achieved. In this embodiment, the functions of clock recovery and time stamping for the data stream by the FPGA chip are all common functions of the FPGA chip, and the corresponding method for using the FPGA chip is referred to, and the description will not be repeated here and in the following.
Furthermore, the synchronization device can realize a time-frequency synchronization function and also can provide good phase noise performance, the second phase-locked loop circuit 2, i.e. the APLL, in the embodiment adopts a more flexible two-stage phase-locked loop, the external high-performance voltage-controlled crystal oscillator 5, i.e. the VCXO, and of course, the voltage-controlled oscillator VCO can also be adopted, since the phase noise of the output clock of the APLL is determined by the reference clock, i.e. the clock source, and the quality factors of the APLL, i.e. the FOM, from the near end, and the phase noise of the VCXO from the far end, the far end and the near end are mainly determined by the loop bandwidth of the selected phase-locked loop, and in the embodiment, not only a high-precision reference clock but also a high-performance external VCXO is provided for the APLL, so that by configuring the loop bandwidth of the APLL at a hundred Hz level, the near-end phase noise and the far-end phase noise of the clock of the APLL output to the FPGA can be at a better level, and the phase-excellent clock of the APLL output to the phase noise circuit is further provided for the reference clock, and the working performance of the circuit is ensured.
Referring to fig. 3, in a preferred embodiment, the second digital phase-locked loop circuit 2 includes a first sub-phase-locked loop circuit 21 and a second sub-phase-locked loop circuit 22, wherein the first sub-phase-locked loop circuit 21 is connected to the second sub-phase-locked loop circuit 22 and the digital-to-analog conversion circuit 3, and specifically, the first sub-phase-locked loop circuit 21 is an analog phase-locked loop circuit APLL, and the second sub-phase-locked loop circuit 22 is a radio frequency phase-locked loop circuit RFPLL.
The difference between the embodiment and the previous embodiment is that a radio frequency phase-locked loop circuit RFPLL is added in the device, the RFPLL has the function of expanding output frequency and is used for supporting the expansion of frequencies such as millimeter wave bands such as n257/n258, in the embodiment, the APLL outputs an external VCXO to the RFPLL through a Buffer inside the external VCXO and is used for providing a reference clock with excellent near-end phase noise for the RFPLL, so that the clock homology of the APLL and the RFPLL is realized, meanwhile, the loop bandwidth of the RFPLL is reasonably configured to MHz level, so that the near-end phase noise and the far-end phase noise of an output clock can be guaranteed to be optimal, namely, the integral phase noise of the whole full frequency band can be guaranteed, and the RFPLL can send the clock to a chip such as a radio frequency chip to be used as a local oscillator, thereby meeting the application requirement of low phase noise of millimeter waves. That is, the clock synchronization device in this embodiment can realize high-precision synchronization of time and frequency of data streams between the FPGA chip and the BBU, and ensure phase noise characteristics of the radio frequency section through the APLL and the RFPLL.
Referring to fig. 4, in another preferred embodiment, the second digital phase-locked loop circuit 2 includes a first sub-phase-locked loop circuit 21 and a second sub-phase-locked loop circuit 22, wherein the second sub-phase-locked loop circuit 22 is respectively connected to the first sub-phase-locked loop circuit 21 and the digital-to-analog conversion circuit 3, and specifically, the first sub-phase-locked loop circuit 21 is an analog phase-locked loop circuit APLL, and the second sub-phase-locked loop circuit 22 is a radio frequency phase-locked loop circuit RFPLL.
In this embodiment, the reference clock of the digital-analog conversion circuit 3, i.e. the add circuit, is not provided by the APLL, but by the RFPLL, so that when the phase noise performance of the internal phase-locked loop of the FPGA chip or the add circuit cannot meet the requirement of low phase noise applied by millimeter waves, the mode of the external clock provided by this embodiment can realize higher performance phase noise, specifically, the APLL outputs the external VCXO to the RFPLL through the Buffer in the external VCXO, so as to provide the RFPLL with the reference clock with excellent near-end phase noise, and by reasonably configuring the loop bandwidth of the RFPLL to MHz level, the near-end phase noise and far-end phase noise of the output clock are both guaranteed to be optimal, i.e. the integrated phase noise of the whole full frequency band is optimal, and the RFPLL sends the clock to the add circuit to be directly used as a local oscillator in addition to the chip such as a radio frequency chip, i.e. by the mode of the external clock, so that the performance of the digital-analog conversion circuit 3, i.e. the add circuit, can meet the application requirement of millimeter waves is guaranteed.
The embodiment of the utility model provides a clock synchronization device, which realizes SyncE frequency synchronization and 1588V2 time synchronization of data flow between the device and a baseband processing unit BBU through a digital phase-locked loop circuit, ensures that the synchronization precision can reach a higher level, and realizes the integration phase noise optimization of a radio frequency section through an analog phase-locked loop circuit and a radio frequency phase-locked loop circuit, thereby meeting the application requirement of millimeter waves. That is, the embodiment of the utility model provides a millimeter wave clock solution with high precision time service and low phase noise under ORAN system. In addition, the digital phase-locked loop circuit DPLL, the analog phase-locked loop circuit APLL, the radio frequency phase-locked loop circuit RFPLL and the voltage-controlled crystal oscillator VCXO which are used in the utility model can all use the existing chips, such as ADI or TI and other integrated chips, and the radio frequency phase-locked loop circuit RFPLL and the field programmable gate array FPGA can adopt an integrated mode or a discrete mode.
Based on the same inventive concept, a transceiver according to a second embodiment of the present invention includes a clock synchronization device as described above, where a radio frequency chip in the transceiver may be provided with a local oscillator by an RFPLL in the clock synchronization device, and the transceiver is connected to a baseband processing unit BBU, so as to implement a function of mobile transceiver.
The technical features and technical effects of the transceiver provided by the embodiment of the present utility model are the same as those of the device provided by the embodiment of the present utility model, and are not described herein. Each of the modules in the transceiver described above may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
In summary, the clock synchronization device and the transceiver provided by the embodiment of the utility model comprise a first phase-locked loop circuit, a second phase-locked loop circuit, a digital-to-analog conversion circuit and a field programmable gate array; the first phase-locked loop circuit, the second phase-locked loop circuit and the digital-to-analog conversion circuit are sequentially connected; the field programmable gate array is respectively connected with the first phase-locked loop circuit, the second phase-locked loop circuit and the digital-to-analog conversion circuit. The utility model realizes SyncE frequency synchronization and 1588V2 time synchronization of data flow between the device and the baseband processing unit BBU through the digital phase-locked loop circuit, ensures that the synchronization precision can reach a higher level, and realizes integral phase noise optimization of millimeter wave frequency bands through the analog phase-locked loop circuit and the radio frequency phase-locked loop circuit, thereby meeting the application requirements of millimeter waves.
In this specification, each embodiment is described in a progressive manner, and all the embodiments are directly the same or similar parts referring to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments. It should be noted that, any combination of the technical features of the foregoing embodiments may be used, and for brevity, all of the possible combinations of the technical features of the foregoing embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples represent only a few preferred embodiments of the present utility model, which are described in more detail and are not to be construed as limiting the scope of the utility model. It should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present utility model, and such modifications and substitutions should also be considered to be within the scope of the present utility model. Therefore, the protection scope of the patent of the utility model is subject to the protection scope of the claims.
Claims (6)
1. A clock synchronization device, comprising:
the digital-to-analog conversion circuit comprises a first phase-locked loop circuit, a second phase-locked loop circuit, a digital-to-analog conversion circuit, a field programmable gate array and a voltage-controlled crystal oscillator;
The first phase-locked loop circuit, the second phase-locked loop circuit and the digital-to-analog conversion circuit are sequentially connected;
The second phase-locked loop circuit is connected with the voltage-controlled crystal oscillator;
The field programmable gate array is respectively connected with the first phase-locked loop circuit, the second phase-locked loop circuit and the digital-to-analog conversion circuit.
2. The clock synchronization device of claim 1, wherein the second phase-locked loop circuit comprises a first sub-phase-locked loop circuit and a second sub-phase-locked loop circuit;
The first sub phase-locked loop circuit is respectively connected with the second sub phase-locked loop circuit, the digital-to-analog conversion circuit and the voltage-controlled crystal oscillator.
3. The clock synchronization device of claim 1, wherein the second phase-locked loop circuit comprises a first sub-phase-locked loop circuit and a second sub-phase-locked loop circuit;
The first sub phase-locked loop circuit is respectively connected with the second sub phase-locked loop circuit and the voltage-controlled crystal oscillator;
The second sub phase-locked loop circuit is connected with the digital-to-analog conversion circuit.
4. The clock synchronization device of claim 1, wherein the first phase-locked loop circuit is a digital phase-locked loop circuit and the second phase-locked loop circuit is an analog phase-locked loop circuit.
5. A clock synchronisation apparatus as claimed in any one of claims 2 or 3, wherein the first sub-phase-locked loop circuit is an analogue phase-locked loop circuit and the second sub-phase-locked loop circuit is a radio frequency phase-locked loop circuit.
6. A transceiver comprising a clock synchronizing device as claimed in any one of claims 1 to 5.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323018475.7U CN221227736U (en) | 2023-11-08 | 2023-11-08 | Clock synchronization device and transceiver |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323018475.7U CN221227736U (en) | 2023-11-08 | 2023-11-08 | Clock synchronization device and transceiver |
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| CN221227736U true CN221227736U (en) | 2024-06-25 |
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| CN202323018475.7U Active CN221227736U (en) | 2023-11-08 | 2023-11-08 | Clock synchronization device and transceiver |
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| CN (1) | CN221227736U (en) |
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- 2023-11-08 CN CN202323018475.7U patent/CN221227736U/en active Active
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