CN204425319U - The fractional frequency division frequency synthesizer with charge pump linearization technique is compensated with DAC - Google Patents
The fractional frequency division frequency synthesizer with charge pump linearization technique is compensated with DAC Download PDFInfo
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- CN204425319U CN204425319U CN201520174430.5U CN201520174430U CN204425319U CN 204425319 U CN204425319 U CN 204425319U CN 201520174430 U CN201520174430 U CN 201520174430U CN 204425319 U CN204425319 U CN 204425319U
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Abstract
The utility model discloses and a kind ofly to compensate and the fractional frequency division frequency synthesizer of charge pump linearization technique with DAC, comprise reference buffer, input parametric frequency divider, phase frequency detector, pulse signal generator, charge pump circuit, loop filter, voltage controlled oscillator, the dual-modulus prescaler able to programme, modulator and the frequency calibration circuit that are made up of prescalar and programmable frequency divider.The utility model is reasonable in design, stability is high, has that frequency synthesizer chip is fully integrated, a feature of high-performance, low cost and miniaturization, significantly reduces quantizing noise and fractional stray.
Description
Technical field
The utility model relates to a kind of frequency synthesizer, and what be specifically related to is a kind of with the fractional frequency division frequency synthesizer of DAC compensation with charge pump linearization technique.
Background technology
Along with the development of wireless communication technology, frequency synthesizer obtains applying more and more widely as local oscillator.Traditional integral frequency divisioil frequency synthesizer frequency resolution is reference clock frequency, and the compromise of loop bandwidth and frequency resolution makes it very limited when taking into account indices.Fractional frequency division frequency synthesizer overcomes above-mentioned restriction, still can provide narrow frequency step when being locked in higher reference frequency.Reference frequency is higher, allows to arrange loop bandwidth wider, thus the loop-locking time is shorter, voltage controlled oscillator is also less to the contribution of in-band phase noise.
But spuious and quantizing noise is the subject matter that fractional frequency division frequency synthesizer faces always, charge pump is as frequency synthesizer important composition unit, in real work, face a series of non-ideal factor impact such as transistor charge injection, clock feedthrough, channel length modulation, produce mismatch current and ripple, cause occurring nonlinear area near null phase error.When being applied to fractional frequency division, phase frequency detector two input phase signal constantly switches near zero phase difference, makes the High-frequency quantization noise after shaping be transformed into low frequency, worsens in-band phase noise, sigma-delta modulator exponent number is higher, and this corruptions is more serious.Three rank MASH1-1-1 structures are owing to realizing simply and not existence and stability problem and being used widely, quantizing noise can be transformed into high frequency by the higher order Sigma-Delta modulator of cascade, low-pass filtering is carried out by the loop filter of frequency synthesizer, filter high-frequency noise, thus reach the object of noise shaping.Quantizing noise after sigma-delta modulator shaping rises with the speed of 40dB/10 frequency multiplication and concentrates on high-frequency region, causes frequency synthesizer to export and produces a large amount of phase noise.Reduce loop bandwidth and can improve this phenomenon, but increase the loop-locking time, reduce and suppress phase noise of voltage controlled oscillator ability.In addition, because sigma-delta modulator is input as fixed value, cause its output sequence to exist periodically, this periodic frequency and harmonic wave thereof make modulator output sequence power spectrum occur the burr being difficult to be low-pass filtered device filtering, and then cause fractional stray.
Utility model content
For the deficiency of above-mentioned technology, the utility model provides and a kind ofly to compensate and the fractional frequency division frequency synthesizer of charge pump linearization technique with DAC, and it has, and frequency synthesizer chip is fully integrated, the feature of high-performance, low cost and miniaturization.
To achieve these goals, the technical solution adopted in the utility model is as follows:
Compensate the fractional frequency division frequency synthesizer with charge pump linearization technique with DAC, comprising:
Reference buffer, for converting external crystal-controlled oscillation signal to square wave;
Input parametric frequency divider, for square wave is carried out frequency division, obtains reference clock frequency;
Voltage controlled oscillator, for output frequency signal;
Dual-modulus prescaler able to programme, the frequency signal for exporting voltage controlled oscillator realizes PN+S frequency division, obtains feedback clock signal, and P, N and S are natural number;
Modulator, for receiving fractional frequency signal, and to the input value of output dynamically regulated program control P and S of dual-modulus prescaler able to programme, changes the frequency dividing ratio of dual-modulus prescaler able to programme;
Phase frequency detector, for comparing the phase difference of reference clock frequency signal and feedback clock signal, and produces the impulse level of respective width;
Loop filter, for converting the input control voltage of voltage controlled oscillator to by the impulse level of phase frequency detector;
Charge pump circuit, under the control of phase frequency detector impulse level, charges to loop filter;
Pulse signal generator, for receiving feedback clock signal, and exporting high level narrow pulse signal to charge pump circuit, controlling the ON time of charge pump circuit;
Frequency calibration circuit, for receiving input control voltage, and the voltage controlled oscillator capacitor array switch that automatically switches, make it reach predeterminated frequency.
Specifically, described charge pump circuit comprises main core charge-discharge circuit, and the DC maladjustment circuit that is connected of all main with this core charge-discharge circuit and D/A converting circuit; Described D/A converting circuit connects pulse signal generator.
Further, described main core charge-discharge circuit comprises reference current circuit, and the charge-discharge circuit, the second operational amplifier and the positive pole that are all connected with this reference current circuit connect first operational amplifier of reference power source Vref; Described first operational amplifier is all connected with charge-discharge circuit with the second operational amplifier, and described DC maladjustment circuit is connected reference current circuit and charge-discharge circuit with D/A converting circuit all simultaneously.
Again further, described reference current circuit comprises grounded-grid GND, and source electrode meets the transistor M1 of power vd D, source electrode drains with this transistor M1 and is connected, drain electrode connection second operational amplifier positive pole, and grid connects the transistor M2 of charge-discharge circuit and the second operational amplifier output terminal and DC maladjustment circuit simultaneously, drain electrode drains with this transistor M2 and is connected, source electrode connects the first operational amplifier negative pole, and grid connects the transistor M3 of the first operational amplifier output terminal and charge-discharge circuit and D/A converting circuit simultaneously, and drain electrode connects transistor M3 source electrode by resistance R1, grid meets power vd D, and the transistor M4 of source ground GND.
Further, described charge-discharge circuit comprises the UP signal of grid for received pulse level, source electrode meets the transistor M5 of power vd D, source electrode is connected with this transistor M5 source electrode, drain electrode connection second operational amplifier negative pole, and grid connects the transistor M6 of transistor M2 grid and DC maladjustment circuit simultaneously, drain electrode drains to be connected and to export as charge pump with transistor M6 and is connected to loop filter, grid connects the transistor M7 of transistor M3 grid and D/A converting circuit and the second operational amplifier output terminal simultaneously, and drain electrode connects transistor M7 source electrode by resistance R2, grid is used for the DN signal of received pulse level, and the transistor M8 of source ground GND.
As preferably, described voltage controlled oscillator is LC voltage controlled oscillator.
As preferably, described modulator is three rank sigma-delta modulators.
Specifically, described frequency calibration circuit comprises the resistance R5 connected successively, resistance R6, resistance R7, resistance R8, resistance R9, be connected to the interrupteur SW 1 between resistance R5 and resistance R6 common port, be connected to the interrupteur SW 2 between resistance R6 and resistance R7 common port, be connected to the interrupteur SW 3 between resistance R7 and resistance R8 common port, be connected to the interrupteur SW 4 between resistance R8 and resistance R9 common port, positive pole connecting valve SW1 or interrupteur SW 2 common port, negative pole is for receiving the first voltage comparator of input control voltage, negative pole connecting valve SW3 or interrupteur SW 4 common port, positive pole is for receiving the second voltage comparator of input control voltage, the NAND gate chip be all connected with the first voltage comparator output and the first reverser, and the second reverser of the second voltage comparator output is connected by NAND gate chip, described resistance R5 mono-termination power vd D, described resistance R9 one end ground connection GND.
Compared with prior art, the utility model has following beneficial effect:
The utility model is by inner integrated automatic frequency calibration function phase-locked loop and voltage controlled oscillator, and add DC maladjustment electric current and digital-to-analogue conversion compensation, significantly reduce fractional stray and quantizing noise, solve the problem existing for prior art, therefore, the utility model has very high practical value and promotional value.
Accompanying drawing explanation
Fig. 1 is circuit theory diagrams of the present utility model.
Fig. 2 is the structure chart of charge pump circuit.
Fig. 3 is the circuit theory diagrams of voltage controlled oscillator.
Fig. 4 is the circuit theory diagrams of modulator.
Fig. 5 is the structure chart of frequency calibration circuit.
Embodiment
Below in conjunction with drawings and Examples, the utility model is described in further detail, and execution mode of the present utility model includes but not limited to the following example.
Embodiment
As shown in Fig. 1 ~ 5, the utility model provides band DAC and compensates the fractional frequency division frequency synthesizer with charge pump linearization technique, can effectively reduce quantizing noise and fractional stray.The utility model comprises reference buffer (OSC Buffer), input parametric frequency divider (R Counter), phase frequency detector (PFD), pulse signal generator (Pulse Generator), charge pump circuit (Charge Pump), voltage controlled oscillator (VCO), the dual-modulus prescaler able to programme be made up of prescalar (Prescaler) and programmable frequency divider (PS Counter), modulator (modulator) and frequency calibration circuit (Calibration), and coupling collar path filter (LPF) and external reference crystal oscillator realize Frequency Locking.Described reference buffer, input parametric frequency divider, phase frequency detector, charge pump circuit, loop filter, voltage controlled oscillator, dual-modulus prescaler able to programme connect successively, and dual-modulus prescaler able to programme also connects phase frequency detector, pulse signal generator and modulator simultaneously, described pulse signal generator connects charge pump circuit.The effect of each components and parts and circuit is as follows respectively:
Reference buffer, for converting external crystal-controlled oscillation signal to square wave;
Input parametric frequency divider, for square wave is carried out frequency division, obtains reference clock frequency;
Voltage controlled oscillator, for output frequency signal;
Dual-modulus prescaler able to programme, the frequency signal for exporting voltage controlled oscillator realizes PN+S frequency division, obtains feedback clock signal, and P, N and S are natural number;
Modulator, for receiving fractional frequency signal, and to the input value of output dynamically regulated program control P and S of dual-modulus prescaler able to programme, changes the frequency dividing ratio of dual-modulus prescaler able to programme;
Phase frequency detector, for comparing the phase difference of reference clock frequency signal and feedback clock signal, and produces the impulse level of respective width;
Loop filter, for converting the input control voltage of voltage controlled oscillator to by the impulse level of phase frequency detector;
Charge pump circuit, under the control of phase frequency detector impulse level, charges to loop filter;
Pulse signal generator, for receiving feedback clock signal, and exporting high level narrow pulse signal to charge pump circuit, controlling the ON time of charge pump circuit;
Frequency calibration circuit, for receiving input control voltage, and the voltage controlled oscillator capacitor array switch that automatically switches, make it reach predeterminated frequency.
As shown in Figure 2, specifically, described charge pump circuit comprises main core charge-discharge circuit (CP), DC maladjustment circuit (OFFSET) and D/A converting circuit (DAC).Described main core charge-discharge circuit comprises reference current circuit, charge-discharge circuit, first operational amplifier (OPA1) and the second operational amplifier (OPA2), wherein, described reference current circuit comprises grounded-grid GND, and source electrode connects the transistor M1 of power vd D, source electrode drains with this transistor M1 and is connected, and grid connects the transistor M2 of DC maladjustment circuit, drain electrode drains with this transistor M2 and is connected, and the transistor M3 of grid linking number analog conversion circuit, and drain electrode connects transistor M3 source electrode by resistance R1, grid meets power vd D, and the transistor M4 of source ground GND, and described charge-discharge circuit comprises the UP signal of grid for received pulse level, source electrode meets the transistor M5 of power vd D, source electrode is connected with this transistor M5 source electrode, and grid connects the transistor M6 of transistor M2 grid and DC maladjustment circuit simultaneously, drain electrode drains to be connected and to export as charge pump with transistor M6 and is connected to loop filter, grid connects the transistor M7 of transistor M3 grid and D/A converting circuit simultaneously, and drain electrode connects transistor M7 source electrode by resistance R2, grid is used for the DN signal of received pulse level, and the transistor M8 of source ground GND.
Due to the grid respectively ground connection GND and power vd D of transistor M1 and M4, thus can the conducting state of analog transistor M5 and M8; And the grid of transistor M5 with M8 is owing to being connected UP and DN signal respectively, the discharge and recharge of charge pump circuit thus can be controlled.The positive pole of described first operational amplifier is for receiving reference power source Vref, negative pole connects transistor M3 source electrode and resistance R1, output connects transistor M3 and M7 grid, and negative feedback makes the change of transistor M3 drain voltage reduce the impact of source electrode, therefore can produce more preferably electric current.Second operational amplifier positive pole connects transistor M2 and M3 drain electrode, and negative pole connects transistor M6 and M7 drain electrode, and output connects transistor M2 and M6 grid.As shown in Figure 2, when the change of charge pump circuit output end voltage, second operational amplifier is by regulating the grid voltage of transistor M3, A point voltage is made to follow B point voltage, if two tree transistors size and resistance completely the same, in wide output voltage range, then flow through transistor M3 equal with M7 electric current, flow through transistor M2 equal with M6 electric current, thus effectively prevent channel-length modulation.
Again as shown in Figure 2, described DC maladjustment circuit is total to S bar charge current branch by transistor M9, M10, M13, M14 etc. and forms, and by identical bias condition mirrored transistor M5, M6 pulse current injectingt to the output of charge pump circuit, forms fixing offset current.And there is negative feedback characteristic due to phase-locked loop, after loop stability, phase frequency detector two input signal can produce constant phase difference and produce opposite polarity Pulsed current injection to exporting to offset the extra offset current introduced to make charge pump, thus makes charge pump circuit functions in the range of linearity.Frequency synthesizer is for obtaining low phase noise, need comparatively large charge pump charging and discharging currents with reduce loop filter and charge-pumped noise contribution, but big current can cause electrical source exchange noise and then be injected into charge pump output current, this impact is the most obvious near null phase error, so need large phase error to avoid being positioned at nonlinear area.But phase error is excessive, charge pump circuit ON time can corresponding lengthening, and its internal transistor flash noise and thermal noise contribution also can increase.Therefore, the utility model DC maladjustment circuit adopts S position control code and DAC pulse jointly to control, and phase error difference is compromised between non-linear and noise contribution at charge pump.
For offsetting the impact of modulator noise, N position noise cancellation component control signal is produced by Digital Signal Processing, the pulse current injectingt of D/A converting circuit, to loop filter, offsets the quantization noise components in charge pump circuit output current, thus the phase noise that reduction fractional frequency division causes worsens.As shown in Figure 2, the D/A converting circuit in the utility model is made up of N bar branch roads such as transistor M11, M12, M15, M16, R3, R4, and cell current mirror-image copies charge pump branch road discharging current is to obtain excellent noise cancellation effect.DAC current ON time also needs compromise, chooses 4 times of voltage controlled oscillator output frequency cycles.This cycle is produced by pulse signal generator, realizes in a digital manner.D type flip flop data-in port is fixed high level, and input clock is provided by feedback clock signal (FCK), output signal through multistage inverter and capacitor stage join be delayed after feed back to zeros data end, finally produce narrow pulse signal.The high level burst pulse co-controlling that the conducting of each bit digit current is exported by signal (BIT<N:1>) and pulse signal generator with shutoff.
As shown in Figure 3, the voltage controlled oscillator in the utility model is LC voltage controlled oscillator, and it comprises transistor M17, M18, M19n, resistance R10, R11n, R12n, electric capacity C1, C2n, C3n, variable capacitance diode C4, C5, reverser INVn and differential inductance L1.Resistance R10 mono-termination power, another termination capacitor C1 and transistor M17, M18 source class.M17 grid connects M18 drain electrode, and M18 grid connects M17 drain electrode formation mutual coupling and provides negative resistance to pipe.While covering wideband frequency range, obtain lower voltage controlled gain, oscillator adopts N position binary array, Central Symmetry switched capacitor array, wherein electric capacity C2n mono-termination M18 grid, another termination transistor M19n source class and resistance R11n; Electric capacity C3n mono-termination M17 grid, another termination transistor M19n drains and resistance R12n.INVn input is connected with M19n grid, meets control signal BIT<n>, exports connecting resistance R11n and R12n common port.The public termination input control voltage (Vtune) of variable capacitance diode C4 and C5 realizes fine frequency and regulates, wherein another termination inductance L 1 of C4 and M18 grid, another termination inductance L 1 of C5 and M17 grid.
As shown in Figure 4, the modulator in the utility model is three rank sigma-delta modulators, and it adopts MASH1-1-1 structure to realize fractional frequency division.Three single order sigma-delta modulators A1, A2 are connected successively with A3, every grade of sigma-delta modulator quantization error after postponing by the process of next stage sigma-delta modulator, every grade of high-order C6, C7, C8 of exporting obtains Y [n], Y [n]=X [n] * Z^ (-2)-E_3*[(1-Z^ (-1) through different the delay with differential process simultaneously)] ^3.Can find out that two-stage quantization error is all cancelled above from Y [n] expression formula, the noise only after the shaping of remaining afterbody high pass.Y [n] connects programmable frequency divider input, and loop feedback frequency dividing ratio is switched between a series of integers of N-3 and N+4, and being averaged by a period of time obtains default fractional frequency division ratio.
As shown in Figure 5, described frequency calibration circuit comprises the resistance R5 connected successively, resistance R6, resistance R7, resistance R8, resistance R9, be connected to the interrupteur SW 1 between resistance R5 and resistance R6 common port, be connected to the interrupteur SW 2 between resistance R6 and resistance R7 common port, be connected to the interrupteur SW 3 between resistance R7 and resistance R8 common port, be connected to the interrupteur SW 4 between resistance R8 and resistance R9 common port, positive pole connecting valve SW1 or interrupteur SW 2 common port, negative pole is for receiving the first voltage comparator Comp1 of input control voltage, negative pole connecting valve SW3 or interrupteur SW 4 common port, positive pole is for receiving the second voltage comparator Comp2 of input control voltage VTUNE, the NAND gate chip be all connected with the first voltage comparator output and the first reverser INV1, and the second reverser INV2 of the second voltage comparator output is connected by NAND gate chip NAND, described resistance R5 mono-termination power vd D, described resistance R9 one end ground connection GND.First voltage comparator output connects the input of NAND gate chip and the first reverser, can given frequency lifting index signal (DIREC).And the second voltage comparator outputs to through the second inverter after NAND gate chip, whether given input control voltage is positioned at predetermined voltage range index signal (INRANGE).Two-way output signal is in conjunction with lock detecting signal, and control figure frequency calibration circuit, regulates voltage controlled oscillator frequency of oscillation, until loop after preset window voltage lockout, closes calibration circuit.
Main operational principle of the present utility model is as follows:
The utility model is accessed external crystal-controlled oscillation, and then outside is inputted crystal oscillation signal and converts square wave to by reference buffer, and obtains reference clock frequency through input parametric frequency divider frequency division.Meanwhile, voltage controlled oscillator output frequency, and realize PN+S frequency division by dual-modulus prescaler able to programme.The output dynamically regulated programmable frequency divider P of modulator and S input value, and then change feedback frequency dividing ration, and obtain default fractional frequency division by counting to average for a long time.Pulse signal generator produces high level narrow pulse signal, controls the ON time of DC maladjustment electric current and DAC current.Phase frequency detector compares reference clock signal and feedback clock signal phase difference, produce respective width impulse level control charge pump circuit and discharge and recharge is carried out to loop filter, and be converted to the input control voltage of voltage controlled oscillator further, thus regulate the frequency of vibration.Frequency calibration circuit is in conjunction with loop feedback characteristics, and automatic switchover voltage controlled oscillator capacitor array switch, makes it reach predeterminated frequency.
The utility model have employed the ripe control technology of existing application and equipment, and improve its circuit structure, then by reasonable manner, these technology are combined, thus achieve that frequency synthesizer chip is fully integrated well, the object of high-performance, low cost and miniaturization, significantly reduce quantizing noise and fractional stray.
Above-described embodiment is only preferred embodiment of the present utility model; it is not the restriction to the utility model protection range; in every case design principle of the present utility model being adopted, and the change carried out non-creativeness work on this basis and make, all should belong within protection range of the present utility model.
Claims (8)
1. be with DAC to compensate the fractional frequency division frequency synthesizer with charge pump linearization technique, it is characterized in that, comprising:
Reference buffer, for converting external crystal-controlled oscillation signal to square wave;
Input parametric frequency divider, for square wave is carried out frequency division, obtains reference clock frequency;
Voltage controlled oscillator, for output frequency signal;
Dual-modulus prescaler able to programme, the frequency signal for exporting voltage controlled oscillator realizes PN+S frequency division, obtains feedback clock signal, and P, N and S are natural number;
Modulator, for receiving fractional frequency signal, and to the input value of output dynamically regulated program control P and S of dual-modulus prescaler able to programme, changes the frequency dividing ratio of dual-modulus prescaler able to programme;
Phase frequency detector, for comparing the phase difference of reference clock frequency signal and feedback clock signal, and produces the impulse level of respective width;
Loop filter, for converting the input control voltage of voltage controlled oscillator to by the impulse level of phase frequency detector;
Charge pump circuit, under the control of phase frequency detector impulse level, charges to loop filter;
Pulse signal generator, for receiving feedback clock signal, and exporting high level narrow pulse signal to charge pump circuit, controlling the ON time of charge pump circuit;
Frequency calibration circuit, for receiving input control voltage, and the voltage controlled oscillator capacitor array switch that automatically switches, make it reach predeterminated frequency.
2. band DAC according to claim 1 compensates the fractional frequency division frequency synthesizer with charge pump linearization technique, it is characterized in that, described charge pump circuit comprises main core charge-discharge circuit, and the DC maladjustment circuit that is connected of all main with this core charge-discharge circuit and D/A converting circuit; Described D/A converting circuit connects pulse signal generator.
3. band DAC according to claim 2 compensates the fractional frequency division frequency synthesizer with charge pump linearization technique, it is characterized in that, described main core charge-discharge circuit comprises reference current circuit, and the charge-discharge circuit, the second operational amplifier and the positive pole that are all connected with this reference current circuit connect first operational amplifier of reference power source Vref; Described first operational amplifier is all connected with charge-discharge circuit with the second operational amplifier, and described DC maladjustment circuit is connected reference current circuit and charge-discharge circuit with D/A converting circuit all simultaneously.
4. band DAC according to claim 3 compensates the fractional frequency division frequency synthesizer with charge pump linearization technique, it is characterized in that, described reference current circuit comprises grounded-grid GND, and source electrode meets the transistor M1 of power vd D, source electrode drains with this transistor M1 and is connected, drain electrode connection second operational amplifier positive pole, and grid connects the transistor M2 of charge-discharge circuit and the second operational amplifier output terminal and DC maladjustment circuit simultaneously, drain electrode drains with this transistor M2 and is connected, source electrode connects the first operational amplifier negative pole, and grid connects the transistor M3 of the first operational amplifier output terminal and charge-discharge circuit and D/A converting circuit simultaneously, and drain electrode connects transistor M3 source electrode by resistance R1, grid meets power vd D, and the transistor M4 of source ground GND.
5. band DAC according to claim 4 compensates the fractional frequency division frequency synthesizer with charge pump linearization technique, it is characterized in that, described charge-discharge circuit comprises the UP signal of grid for received pulse level, source electrode meets the transistor M5 of power vd D, source electrode is connected with this transistor M5 source electrode, drain electrode connection second operational amplifier negative pole, and grid connects the transistor M6 of transistor M2 grid and DC maladjustment circuit simultaneously, drain electrode drains to be connected and to export as charge pump with transistor M6 and is connected to loop filter, grid connects the transistor M7 of transistor M3 grid and D/A converting circuit and the second operational amplifier output terminal simultaneously, and drain electrode connects transistor M7 source electrode by resistance R2, grid is used for the DN signal of received pulse level, and the transistor M8 of source ground GND.
6. band DAC according to claim 5 compensates the fractional frequency division frequency synthesizer with charge pump linearization technique, and it is characterized in that, described voltage controlled oscillator is LC voltage controlled oscillator.
7. band DAC according to claim 6 compensates the fractional frequency division frequency synthesizer with charge pump linearization technique, and it is characterized in that, described modulator is three rank sigma-delta modulators.
8. band DAC according to claim 7 compensates the fractional frequency division frequency synthesizer with charge pump linearization technique, it is characterized in that, described frequency calibration circuit comprises the resistance R5 connected successively, resistance R6, resistance R7, resistance R8, resistance R9, be connected to the interrupteur SW 1 between resistance R5 and resistance R6 common port, be connected to the interrupteur SW 2 between resistance R6 and resistance R7 common port, be connected to the interrupteur SW 3 between resistance R7 and resistance R8 common port, be connected to the interrupteur SW 4 between resistance R8 and resistance R9 common port, positive pole connecting valve SW1 or interrupteur SW 2 common port, negative pole is for receiving the first voltage comparator of input control voltage, negative pole connecting valve SW3 or interrupteur SW 4 common port, positive pole is for receiving the second voltage comparator of input control voltage, the NAND gate chip be all connected with the first voltage comparator output and the first reverser, and the second reverser of the second voltage comparator output is connected by NAND gate chip, described resistance R5 mono-termination power vd D, described resistance R9 one end ground connection GND.
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| CN109936361A (en) * | 2019-04-03 | 2019-06-25 | 杭州城芯科技有限公司 | A kind of fractional frequency division frequency synthesizer containing PFD/DAC quantizing noise technology for eliminating |
| CN112953515A (en) * | 2021-01-26 | 2021-06-11 | 北京金迈捷科技有限公司 | Fractional phase-locked loop |
| CN112953515B (en) * | 2021-01-26 | 2024-05-10 | 北京金迈捷科技有限公司 | Fractional phase-locked loop |
| CN113452366A (en) * | 2021-07-22 | 2021-09-28 | 海能达通信股份有限公司 | PLL circuit and electronic equipment |
| CN115800999A (en) * | 2022-11-15 | 2023-03-14 | 泛升云微电子(苏州)有限公司 | Phase-locked loop system and chip |
| CN116667846A (en) * | 2023-08-01 | 2023-08-29 | 牛芯半导体(深圳)有限公司 | Frequency synthesis circuit |
| CN116667846B (en) * | 2023-08-01 | 2024-02-23 | 牛芯半导体(深圳)有限公司 | Frequency synthesis circuit |
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