CN206211980U - A kind of fully integrated fractional frequency-division phase-locked loop of adaptive bandwidth - Google Patents
A kind of fully integrated fractional frequency-division phase-locked loop of adaptive bandwidth Download PDFInfo
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Abstract
The utility model discloses a kind of fully integrated fractional frequency-division phase-locked loop of adaptive bandwidth, including phase frequency detector, the first charge pump and the second charge pump being connected with phase frequency detector, the loop filter being all connected with the first charge pump and the second charge pump, the LC voltage controlled oscillators being connected with loop filter, the prescalar being connected with LC voltage controlled oscillators, with the programmable frequency divider that prescalar and phase frequency detector are all connected with constituting closed loop, the ∑ Delta modulator being connected with programmable frequency divider, and the automatic frequency calibration circuit being connected with LC voltage controlled oscillators.The utility model sets passive loop filter, realize identical capacitor equivalent enlarging function, improve phase noise performance in phase-locked loop, simultaneously using the LC voltage controlled oscillators with voltage controlled gain regulatory function, effectively reduce excursion of the voltage controlled gain with frequency of oscillation, be conducive to PLL loop bandwidth to keep relative stability, be highly suitable for the fully integrated fractional frequency-division phase-locked loop in broadband.
Description
Technical field
The utility model is related to technical field of integrated circuits, is to be related to a kind of adaptive bandwidth fully integrated small specifically
Number frequency dividing phase-locked loop.
Background technology
The progressive of wireless communication technology promotes RF transceiver chip towards high-performance, high integration, low-power consumption, it is low into
This direction is developed.Phaselocked loop as radio receiving-transmitting unit key modules, play offer local oscillation signal carry out frequency conversion and letter
The function of road selection, in various phase-locked loop structures, charge pump type phaselocked loop has high stability, big catching range, zero because of it
The advantages of static phase error, turns into current the most widely used structure.
The subject matter that high-performance fully integrated phase-locked loop faces is the integrated of low-pass loop filter.Passive filter knot
Structure is simple, be easily achieved, and influences smaller to in-band phase noise, and Active filter is complicated, and active device can be introduced
Extra noise penalty phase noise performance.Therefore if without particular/special requirement in Design of PLL, usual prioritizing selection without
Source filter structure.Fig. 1 show three rank passive loop filters, including electric capacity C1, C2, C3 and resistance R1, R2.Charge pump is defeated
Go out Icp and connect resistance R1, R2 and electric capacity C2 respectively, signal exports Vout to next stage circuit after resistance R2.Overall transfer letter
Number Vout (s)=(1+sT1)/((sA) (1+sT2) (1+sT3)), wherein A=C1+C2+C3, zero crossing time
Constant T1=R1C1, pole time constant T2=R1C1C2/ (C1+C2+C3), T3=R2C3, also one limit
Positioned at zero frequency.
To meet cycle of phase-locked loop stability requirement, for producing the electric capacity C1 values of zero point generally very big, in chip
Realize that substantial amounts of area can be taken in portion.In order to keep reducing minimum capacity C1 while identical loop bandwidth as far as possible, only lead to
Cross increase loop filter resistance R1 and R2, reduce charge pump charging and discharging currents Icp.On the one hand, resistance is bigger, accordingly
Thermal noise is also bigger, the voltage controlled oscillator of thermal noise meeting directly modulation rear class cascade；On the other hand, phaselocked loop charge-pumped noise
Transfer function is inversely proportional with charging and discharging currents, and charging and discharging currents are smaller, and it is also brighter to phaselocked loop entirety phase noise contribution
It is aobvious.Therefore, for the ease of the Embedded of loop filter, reduction capacitor's capacity is relied solely on, inevitably causes phase
The deterioration of noise.
More current method is using double loop filter construction at present.The structure exports the proportional charge pump of two-way
Electric current, is added by after different branch treatment, can reach the effect of capacitance multiplication, to obtain the electricity of the zero point after equivalent amplification
Hold.As shown in Fig. 2 bicyclic path filter includes operational amplifier OPA1, OPA2, electric capacity C1, C2, C3 and resistance R1, R2.Electric charge
The output current of pump 1 is Icp, and the output current of charge pump 2 is K*Icp, K ＞ 1.Electric capacity C2 one end connects the output end of charge pump 1 and fortune
Amplifier OPA1 inverting inputs are calculated, other end concatenation operation amplifier OPA1 output ends and operational amplifier OPA2 positives are input into
End；The output connection resistance of charge pump 2 R1, electric capacity C1 and operational amplifier OPA2 inverting inputs；Reference voltage Vref connects respectively
Meet operational amplifier OPA1 normal phase input ends, resistance R1 and electric capacity C1.Operational amplifier OPA2 output ends are finally defeated through resistance R2
Go out, and be connected to ground by electric capacity C3.
The electric current Icp of charge pump 1 is exported through the integration branch road that operational amplifier OPA1 and electric capacity C2 is constituted, and is produced and is located at zero-frequency
Limit at rate, transfer function V1=-Icp/ (sC2).The electric current K*Icp of charge pump 2 is constituted by resistance R1 and electric capacity C1
Parallel branch is exported, transfer function V2=KIcpR1/ (1+sR1C1).Due to V1 signals reverses, two bars branch roads
By the subtracter that operational amplifier OPA2 is constituted, signal addition is equivalent to, constitutes transfer function V3 ≈-Icp (1+sK
R1C2)/((sC2) (1+sR1C1)), output signal obtains final bicyclic again by resistance R2 and electric capacity C3
Path filter overall transfer function Vout=-Icp (1+sT1)/((sC2) (1+sT2) (1+sT3)).Its
Middle zero crossing time constant T1=R1KC2, pole time constant T2=R1C1, T3=R2C3, also one limit position
In origin.In phaselocked loop actual design, minimum capacity capacitance is much larger than electric capacity C2, C3, therefore bicyclic path filter can be realized
The pole frequency equal with passive filter structure proximate, while minimum capacity can be according to two-way charge pump charging and discharging currents times
Number equal proportion reduces, and the 1/K that need to only reach original capacitance just can obtain identical zero frequency, and then realize consistent transmission letter
Number.
This double loop filter construction can effectively reduce capacity area needed for Embedded wave filter, but still have one
It is a little not enough.Integration and subtraction function are realized as a result of operational amplifier OPA1, OPA2, active circuit can consume extra electricity
Stream increases power consumption, the voltage controlled oscillator input control while the adjoint filter transfer function of operational amplifier output noise meeting is added to
Voltage, causes phase noise performance reduction in phase-locked loop.
Utility model content
To overcome above mentioned problem of the prior art, the utility model provides a kind of fully integrated fractional frequency division of adaptive bandwidth
Phaselocked loop, by low-power consumption, low noise, loop filter easy of integration, combining adaptive bandwidth technologies are complete to meet high-performance
The actual demand of integrated fractional frequency-division phase-locked loop, realizes fully integrated frequency synthesizer chip, high-performance, low cost and miniaturization.
To achieve these goals, the technical solution adopted in the utility model is as follows：
A kind of fully integrated fractional frequency-division phase-locked loop of adaptive bandwidth, including receive the mirror of reference signal Fref and fractional frequency signal
Frequency phase discriminator PFD, receives the control signal of phase frequency detector PFD and the first charge pump CP1 and the second charge pump of parallel connection respectively
CP2, the loop filter LPF being all connected with the first charge pump CP1 and the second charge pump CP2, receive loop filter LPF outputs
Signal simultaneously provides the LC voltage controlled oscillator VCOs of signal output Vout, from before the output end collection signal of LC voltage controlled oscillator VCOs
Put frequency divider Prescaler, receive the output signal of prescalar Prescaler and feed back prescalar and be simultaneously mirror
Frequency phase discriminator PFD provides the programmable frequency divider PSCounter of fractional frequency signal, is connected with programmable frequency divider PSCounter
Sigma-delta modulator, and the automatic frequency calibration circuit being connected with LC voltage controlled oscillator VCOs；
The loop filter LPF includes resistance R10, R20, and electric capacity C10, C20 and C30, wherein, the first charge pump
CP1 output end connection resistance R10, R20 and electric capacity C20, the second charge pump CP2 output end connection the resistance R10 other ends and
Electric capacity C10, resistance the R20 other end connect electric capacity C30 and connect LC voltage controlled oscillator VCO inputs, electric capacity C10, C20 and C30
Other end ground connection, wherein, electric capacity C10 values are much larger than electric capacity C20 values.
When charge pump is in charging and discharging state, electric capacity C10 and C20 output current of the accumulation from charge pump, and turn
It is changed to voltage；When charge pump output services are in high-impedance state, electric capacity C10 and C20 carry out electric charge and share.Because electric capacity C10 takes
Value is much larger than C20, and electric capacity C10 will absorb most of output current from charge pump.First charge pump CP1 output currents are
Icp1, the second charge pump output current is k*Icp1, wherein k<1.Because both input signals receive phase frequency detector co- controlling
And opposite polarity, it will while being charged and discharged to loop filter, the first charge pump CP1 output currents Icp1 flows through electricity
Shunted after resistance R10, wherein k*Icp1 flows through the second charge pump CP2, and (1-k) * Icp1 flow through electric capacity C10, cause electric capacity C10
On voltage changing rate slow down, produce new loop filter zero crossing time constant R1C1/ (1-k).Therefore, it is not change
Loop transient response, keeps and single charge pump loop filter structure identical transfer function and output voltage change, the ring
Path filter minimum capacity C10 need to only meet 1-k times of original capacitance.
PLL loop bandwidth is directly proportional to voltage controlled oscillator voltage controlled gain and output frequency is inversely proportional.It is voltage-controlled in broadband
In oscillator design, voltage controlled gain excursion is more than working frequency tuning range so that become in whole frequency band inner ring road bandwidth
Change scope excessive, be unfavorable for the optimization of fully integrated phase-locked loop phase noise and locking time.Therefore become to improve voltage controlled gain
Change the influence to PLL loop bandwidth, the variable capacitor array and frequency coarse adjustment electricity of numerical control are set in the LC voltage controlled oscillators
Hold array.
Specifically, the LC voltage controlled oscillator VCOs include transistor M1, M2, M3, M4, resistance R1, R2, R3, electric capacity C1,
C2, variable capacitance Cvar1, Cvar2, differential inductance L1, and shared bias voltage vb and input control signal BIT<N:1>And
The variable capacitor array and frequency coarse adjustment capacitor array of output port outp and outn are connected respectively, wherein, control signal BIT<
N:1>From automatic frequency calibration circuit, output port outp and outn composite signal output Vout；Wherein, transistor M1 and M2
Source electrode power supply vdd is accessed by resistance R1, it is mutually symplectic that the grid of transistor M1 and M2 and drain electrode are interconnected to form PMOS
Pipe provides negative resistance；The source grounding of transistor M3 and M4, its grid and drain electrode are interconnected to form NMOS, and mutually symplectic pipe is provided
Negative resistance；The drain electrode of transistor M1 and M3 is all connected with output port outp, and the drain electrode of transistor M2 and M4 is all connected with output port
Outn, differential inductance L1 two ends connect output port outp and outn respectively；Biased electrical is accessed in the resistance R2 and R3 one end
Pressure vb, resistance R2 other ends connection electric capacity C1 and variable capacitance Cvar1, the resistance R3 other ends connection electric capacity C2 and variable capacitance
Cvar2, electric capacity the C1 other end connect output port outp, electric capacity C2 other ends connection output port outn；Variable capacitance Cvar1
Input control voltage vtune is accessed jointly with the Cvar2 other ends.
To reduce voltage controlled gain, oscillator realizes oscillation frequency using N binary array, Central Symmetry switched capacitor array
The coarse tuning of rate, specially described frequency coarse adjustment capacitor array include transistor M5n, resistance R4n and R5n, electric capacity C3n and C4n,
And phase inverter INV1n, wherein, mantissa n and control signal BIT<N:1>In N matching；The phase inverter INV1n inputs
Incoming control signal BIT equal with transistor M5n grids<N:1>, phase inverter INV1n output ends connect resistance R4n and R5n respectively；
The resistance R4n other ends connect electric capacity C3n and transistor M5n source electrodes, the connection electric capacity C4n and transistor M5n leakages of the resistance R5n other ends
Pole, electric capacity C3n other ends connection output port outp, electric capacity C4n other ends connection output port outn.
In order to meet requirement of the broadband fully integrated phase-locked loop to voltage controlled gain, the LC voltage controlled oscillators are entered using N two
Make arrangement variable capacitor array, further reduce voltage controlled gain with working frequency excursion, it is specially described can power transformation
Holding array includes that resistance R6n and R7n, electric capacity C5n and C6n, variable capacitance Cvar3n and Cvar4n, phase inverter INV2n, first pass
Defeated door TG1 and the second transmission gate TG2, wherein, mantissa n and control signal BIT<N:1>In N matching；The resistance R6n and R7n
Bias voltage vb is accessed in one end, and resistance R6n other ends connection electric capacity C5n and variable capacitance Cvar3n, the resistance R7n other ends connect
Connect electric capacity C6n and variable capacitance Cvar4n, electric capacity C5n other ends connection output port outp, the connection output of the electric capacity C6n other ends
Port outn；Phase inverter INV2n, the first transmission gate TG1 and the second transmission gate TG2 constitute alternative path, phase inverter INV2n's
Input and output end respectively connect the first transmission gate TG1 and the second transmission gate TG2, and phase inverter INV2n inputs are accessed
Control signal BIT<N:1>, the first transmission gate TG1 access input control voltage vtune, the second transmission gate TG2 access power supply vdd,
First transmission gate TG1 and the second transmission gate TG2 also connect the common end of variable capacitance Cvar3n and Cvar4n simultaneously.Shaken when voltage-controlled
When swinging device and being operated in low-limit frequency, the whole connection vtune of the input control voltage of variable capacitor array, as working frequency is continuous
Raise, input control voltage starts to be sequentially connected supply voltage vdd so that increase tendency of the voltage controlled gain in high frequency is pressed down
System, finally reduces the excursion of voltage controlled gain in whole frequency band.
Compared with prior art, the utility model has the advantages that：
The loop filter without active circuit that the utility model passes through ingehious design, realizes identical capacitor equivalent
Enlarging function, effectively reduces power consumption, has saved filter capacity, and improves phase noise performance in phase-locked loop, together
Shi Caiyong has the LC voltage controlled oscillators of voltage controlled gain regulatory function, coordinates the variable capacitance of automatic frequency calibration circuit and numerical control
Array, effectively reduces excursion of the voltage controlled gain with frequency of oscillation, is conducive to PLL loop bandwidth to keep relative stability,
It is highly suitable for the application requirement of the fully integrated fractional frequency-division phase-locked loop in broadband, is with a wide range of applications, is adapted to popularization and application.
Brief description of the drawings
Fig. 1 is the circuit theory diagrams of three rank passive loop filters in the prior art.
Fig. 2 is the circuit theory diagrams of bicyclic path filter in the prior art.
Fig. 3 is circuit theory diagrams of the present utility model.
Fig. 4 is the utility model loop filter discharge and recharge equivalent schematic.
Fig. 5 is the circuit theory diagrams of LC voltage controlled oscillators in the utility model.
Fig. 6 is the circuit theory diagrams of frequency coarse adjustment capacitor array in Fig. 5.
Fig. 7 is the circuit theory diagrams of variable capacitor array in Fig. 5.
Specific embodiment
The utility model is described in further detail with reference to the accompanying drawings and examples, and implementation method of the present utility model includes
But it is not limited to the following example.
Embodiment
As shown in Fig. 3 to Fig. 7, the fully integrated fractional frequency-division phase-locked loop of the adaptive bandwidth, including receive reference signal Fref
With the phase frequency detector PFD of fractional frequency signal, the control signal of phase frequency detector PFD and the first charge pump of parallel connection are received respectively
CP1 and the second charge pump CP2, the loop filter LPF being all connected with the first charge pump CP1 and the second charge pump CP2, reception ring
Path filter LPF output signals simultaneously provide the LC voltage controlled oscillator VCOs of signal output Vout, from the defeated of LC voltage controlled oscillator VCOs
Go out the prescalar Prescaler of end collection signal, receive the output signal of prescalar Prescaler and feed back preposition
Frequency divider and the programmable frequency divider PSCounter of fractional frequency signal is provided for phase frequency detector PFD simultaneously, with programmable frequency divider
The sigma-delta modulator of PSCounter connections, and the automatic frequency calibration circuit being connected with LC voltage controlled oscillator VCOs.
Specifically, the output signal Q of the phase frequency detector PFD connects the input control signal UP of the first charge pump CP1
Output signal QN with input the control signal DOWN, phase frequency detector PFD of the second charge pump CP2 connects the first charge pump CP1
Input control signal DOWN and the second charge pump CP2 input control signal UP.
The loop filter LPF includes resistance R10, R20, and electric capacity C10, C20 and C30, wherein, the first charge pump
CP1 output end connection resistance R10, R20 and electric capacity C20, the second charge pump CP2 output end connection the resistance R10 other ends and
Electric capacity C10, resistance the R20 other end connect electric capacity C30 and connect LC voltage controlled oscillator VCO inputs, electric capacity C10, C20 and C30
Other end ground connection, wherein, electric capacity C10 values are much larger than electric capacity C20 values.
When charge pump is in charging and discharging state, electric capacity C10 and C20 output current of the accumulation from charge pump, and turn
It is changed to voltage；When charge pump output services are in high-impedance state, electric capacity C10 and C20 carry out electric charge and share.Because electric capacity C10 takes
Value is much larger than C20, and electric capacity C10 will absorb most of output current from charge pump.First charge pump CP1 output currents are
Icp1, the second charge pump output current is k*Icp1, wherein k<1.Because both input signals receive phase frequency detector co- controlling
And opposite polarity, it will while being charged and discharged to loop filter, the first charge pump CP1 output currents Icp1 flows through electricity
Shunted after resistance R10, wherein k*Icp1 flows through the second charge pump CP2, and (1-k) * Icp1 flow through electric capacity C10, cause electric capacity C10
On voltage changing rate slow down, produce new loop filter zero crossing time constant R1C1/ (1-k).Therefore, it is not change
Loop transient response, keeps and single charge pump loop filter structure identical transfer function and output voltage change, the ring
Path filter minimum capacity C10 need to only meet 1-k times of original capacitance.
PLL loop bandwidth is directly proportional to voltage controlled oscillator voltage controlled gain and output frequency is inversely proportional.It is voltage-controlled in broadband
In oscillator design, voltage controlled gain excursion is more than working frequency tuning range so that become in whole frequency band inner ring road bandwidth
Change scope excessive, be unfavorable for the optimization of fully integrated phase-locked loop phase noise and locking time.Therefore become to improve voltage controlled gain
Change the influence to PLL loop bandwidth, the variable capacitor array and frequency coarse adjustment electricity of numerical control are set in the LC voltage controlled oscillators
Hold array.
Specifically, the LC voltage controlled oscillator VCOs include transistor M1, M2, M3, M4, resistance R1, R2, R3, electric capacity C1,
C2, variable capacitance Cvar1, Cvar2, differential inductance L1, and shared bias voltage vb and input control signal BIT<N:1>And
The variable capacitor array and frequency coarse adjustment capacitor array of output port outp and outn are connected respectively, wherein, control signal BIT<
N:1>From automatic frequency calibration circuit, output port outp and outn composite signal output Vout；Wherein, transistor M1 and M2
Source electrode power supply vdd is accessed by resistance R1, it is mutually symplectic that the grid of transistor M1 and M2 and drain electrode are interconnected to form PMOS
Pipe provides negative resistance；The source grounding of transistor M3 and M4, its grid and drain electrode are interconnected to form NMOS, and mutually symplectic pipe is provided
Negative resistance；The drain electrode of transistor M1 and M3 is all connected with output port outp, and the drain electrode of transistor M2 and M4 is all connected with output port
Outn, differential inductance L1 two ends connect output port outp and outn respectively；Biased electrical is accessed in the resistance R2 and R3 one end
Pressure vb, resistance R2 other ends connection electric capacity C1 and variable capacitance Cvar1, the resistance R3 other ends connection electric capacity C2 and variable capacitance
Cvar2, electric capacity the C1 other end connect output port outp, electric capacity C2 other ends connection output port outn；Variable capacitance Cvar1
Input control voltage vtune is accessed jointly with the Cvar2 other ends.
To reduce voltage controlled gain, oscillator realizes oscillation frequency using N binary array, Central Symmetry switched capacitor array
The coarse tuning of rate, specially described frequency coarse adjustment capacitor array include transistor M5n, resistance R4n and R5n, electric capacity C3n and C4n,
And phase inverter INV1n, wherein, mantissa n and control signal BIT<N:1>In N matching；The phase inverter INV1n inputs and
The equal incoming control signal BIT of transistor M5n grids<N:1>, phase inverter INV1n output ends connect resistance R4n and R5n respectively；Electricity
Resistance the R4n other end connection electric capacity C3n and transistor M5n source electrodes, the connection electric capacity C4n and transistor M5n leakages of the resistance R5n other ends
Pole, electric capacity C3n other ends connection output port outp, electric capacity C4n other ends connection output port outn.
In order to meet requirement of the broadband fully integrated phase-locked loop to voltage controlled gain, the LC voltage controlled oscillators are entered using N two
Make arrangement variable capacitor array, further reduce voltage controlled gain with working frequency excursion, it is specially described can power transformation
Holding array includes that resistance R6n and R7n, electric capacity C5n and C6n, variable capacitance Cvar3n and Cvar4n, phase inverter INV2n, first pass
Defeated door TG1 and the second transmission gate TG2, wherein, mantissa n and control signal BIT<N:1>In N matching；The resistance R6n and R7n
Bias voltage vb is accessed in one end, and resistance R6n other ends connection electric capacity C5n and variable capacitance Cvar3n, the resistance R7n other ends connect
Connect electric capacity C6n and variable capacitance Cvar4n, electric capacity C5n other ends connection output port outp, the connection output of the electric capacity C6n other ends
Port outn；Phase inverter INV2n, the first transmission gate TG1 and the second transmission gate TG2 constitute alternative path, phase inverter INV2n's
Input and output end respectively connect the first transmission gate TG1 and the second transmission gate TG2, and phase inverter INV2n inputs are accessed
Control signal BIT<N:1>, the first transmission gate TG1 access input control voltage vtune, the second transmission gate TG2 access power supply vdd,
First transmission gate TG1 and the second transmission gate TG2 also connect the common end of variable capacitance Cvar3n and Cvar4n simultaneously.Shaken when voltage-controlled
When swinging device and being operated in low-limit frequency, the whole connection vtune of the input control voltage of variable capacitor array, as working frequency is continuous
Raise, input control voltage starts to be sequentially connected supply voltage vdd so that increase tendency of the voltage controlled gain in high frequency is pressed down
System, finally reduces the excursion of voltage controlled gain in whole frequency band.
Above-described embodiment is only preferred embodiment of the present utility model, not to the limitation of the utility model protection domain,
In every case design principle of the present utility model, and the change for carrying out non-creativeness work on this basis and making are used, all should
Belong within protection domain of the present utility model.
Claims (4)
1. the fully integrated fractional frequency-division phase-locked loop of a kind of adaptive bandwidth, it is characterised in that including receive reference signal Fref and point
The phase frequency detector PFD of frequency signal, receive respectively phase frequency detector PFD control signal and the first charge pump CP1 of parallel connection and
Second charge pump CP2, the loop filter LPF being all connected with the first charge pump CP1 and the second charge pump CP2, receive loop filter
Ripple device LPF output signals simultaneously provide the LC voltage controlled oscillator VCOs of signal output Vout, from the output end of LC voltage controlled oscillator VCOs
The prescalar Prescaler of signal is gathered, the output signal of prescalar Prescaler is received and is fed back prescale unit
Device and the programmable frequency divider PSCounter of fractional frequency signal is provided for phase frequency detector PFD simultaneously, with programmable frequency divider
The sigma-delta modulator of PSCounter connections, and the automatic frequency calibration circuit being connected with LC voltage controlled oscillator VCOs；
The loop filter LPF includes resistance R10, R20, and electric capacity C10, C20 and C30, wherein, the first charge pump CP1
Output end connection resistance R10, R20 and electric capacity C20, the second charge pump CP2 output end connection the resistance R10 other ends and electric capacity
C10, resistance the R20 other end connect electric capacity C30 and connect LC voltage controlled oscillator VCO inputs, and electric capacity C10, C20 and C30's is another
One end is grounded, wherein, electric capacity C10 values are much larger than electric capacity C20 values.
2. a kind of fully integrated fractional frequency-division phase-locked loop of adaptive bandwidth according to claim 1, it is characterised in that the LC
Voltage controlled oscillator VCO include transistor M1, M2, M3, M4, resistance R1, R2, R3, electric capacity C1, C2, variable capacitance Cvar1,
Cvar2, differential inductance L1, and shared bias voltage vb and input control signal BIT<N:1>And output port is connected respectively
The variable capacitor array and frequency coarse adjustment capacitor array of outp and outn, wherein, control signal BIT<N:1>From automatic frequency
Calibration circuit；Wherein, the source electrode of transistor M1 and M2 by resistance R1 access power supply vdd, the grid of transistor M1 and M2 and
Drain electrode is interconnected to form PMOS, and mutually symplectic pipe provides negative resistance；The source grounding of transistor M3 and M4, its grid and drain electrode phase
Connect to form NMOS mutually symplectic pipe offer negative resistances；The drain electrode of transistor M1 and M3 is all connected with output port outp, transistor M2
Output port outn is all connected with the drain electrode of M4, differential inductance L1 two ends connect output port outp and outn respectively；The electricity
Resistance R2 and R3 accesses one end bias voltage vb, and electric capacity C1 and variable capacitance Cvar1, resistance R3 are another for the connection of the resistance R2 other ends
End connection electric capacity C2 and variable capacitance Cvar2, electric capacity C1 other ends connection output port outp, electric capacity C2 other ends connection is defeated
Exit port outn；Variable capacitance Cvar1 and the Cvar2 other end access input control voltage vtune jointly.
3. a kind of fully integrated fractional frequency-division phase-locked loop of adaptive bandwidth according to claim 2, it is characterised in that the frequency
Rate coarse adjustment capacitor array includes transistor M5n, resistance R4n and R5n, electric capacity C3n and C4n and phase inverter INV1n, wherein, tail
Number n and control signal BIT<N:1>In N matching；The phase inverter INV1n inputs and the equal Access Control of transistor M5n grids
Signal BIT<N:1>, phase inverter INV1n output ends connect resistance R4n and R5n respectively；The resistance R4n other ends connect electric capacity C3n and
Transistor M5n source electrodes, the connection electric capacity C4n and transistor M5n drain electrodes of the resistance R5n other ends, electric capacity C3n other ends connection output end
Mouth outp, electric capacity C4n other ends connection output port outn.
4. the fully integrated fractional frequency-division phase-locked loop of a kind of adaptive bandwidth according to claim 2, it is characterised in that it is described can
Becoming capacitor array includes resistance R6n and R7n, electric capacity C5n and C6n, variable capacitance Cvar3n and Cvar4n, phase inverter INV2n, the
One transmission gate TG1 and the second transmission gate TG2, wherein, mantissa n and control signal BIT<N:1>In N matching；The resistance R6n
Bias voltage vb is accessed with R7n one end, electric capacity C5n and variable capacitance Cvar3n, resistance R7n are another for the connection of the resistance R6n other ends
One end connects electric capacity C6n and variable capacitance Cvar4n, and electric capacity C5n other ends connection output port outp, the electric capacity C6n other ends connect
Meet output port outn；Phase inverter INV2n, the first transmission gate TG1 and the second transmission gate TG2 constitute alternative path, phase inverter
The input and output end of INV2n respectively connect the first transmission gate TG1 and the second transmission gate TG2, and phase inverter INV2n is input into
Hold incoming control signal BIT<N:1>, it is electric that the first transmission gate TG1 accesses input control voltage vtune, the second transmission gate TG2 access
Source vdd, the first transmission gate TG1 and the second transmission gate TG2 also connect the common end of variable capacitance Cvar3n and Cvar4n simultaneously.
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| CN108111146A (en) * | 2018-01-30 | 2018-06-01 | 上海航天芯锐电子科技有限公司 | The auto-calibration circuits of the time constant of active filter |
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