CN213426145U - Phase-locked loop circuit with high power supply noise rejection ratio - Google Patents
Phase-locked loop circuit with high power supply noise rejection ratio Download PDFInfo
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- CN213426145U CN213426145U CN202022764074.6U CN202022764074U CN213426145U CN 213426145 U CN213426145 U CN 213426145U CN 202022764074 U CN202022764074 U CN 202022764074U CN 213426145 U CN213426145 U CN 213426145U
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Abstract
The utility model discloses a phase-locked loop circuit with high power noise rejection ratio, include: phase frequency detector, charge pump, loop filter and frequency divider still include: the output end of the phase frequency detector is connected with the input end of the charge pump; the output end of the charge pump is connected with the input end of the loop filter and the first input end of the power supply noise suppression voltage-controlled oscillator; the output end of the power supply noise suppression voltage-controlled oscillator is used as a circuit signal output end and is connected with the input end of the frequency divider; the output end of the frequency divider outputs a feedback clock to one input end of the phase frequency detector, and the other input end of the phase frequency detector receives a reference clock. The utility model provides a too much consumption area consumption power consumption and the narrower problem of tuning range among the current suppression power noise technique.
Description
Technical Field
The utility model relates to a phase-locked loop circuit.
Background
Phase-locked loop technology has been widely used in the field of communications and in almost all digital systems to generate clocks. With the improvement of process technology and the reduction of power supply voltage, the design of a phase-locked loop is more and more strict, mainly comprises low jitter output, small occupied area, wide tuning range and high power supply noise suppression capability so as to be used in a very large scale integrated circuit system.
As shown in fig. 2, a conventional phase-locked loop circuit mainly includes a Phase Frequency Detector (PFD), a Charge Pump (CP), a loop filter (LPF), a Voltage Controlled Oscillator (VCO), and a frequency Divider (Divider). The specific working principle is that the phase frequency detector can discriminate the frequency and phase difference between the input reference clock (REFCLK) and the feedback clock (FBCLK). The difference can be converted into a charge-discharge current by a charge pump, and then a voltage control signal VCTRL of a voltage controlled oscillator is output through a loop filter, and the voltage controlled oscillator generates a clock signal CKOUT based on loop parameters according to an input voltage signal.
In a chip having a large-scale digital circuit, in order to realize a smaller output Jitter (Jitter) characteristic in the case of a poor power supply noise, two methods are often employed to design a phase-locked loop circuit. The first is to employ an LC oscillator with a low jitter output, but a VCO based on an LC architecture needs to consume a large amount of area and power consumption. The other method is to adopt a power supply modulation phase-locked loop technology based on a linear voltage regulator, but the tuning range is narrower due to the limited input control voltage range, and the requirement of the wide tuning range in the current large-scale integrated circuit is not met.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a phase-locked loop circuit with high power noise rejection ratio solves the narrower problem of too much consumption area consumption and tuning range in the current suppression power noise technique.
The technical scheme for realizing the purpose is as follows:
a phase locked loop circuit having a high power supply noise rejection ratio, comprising: phase frequency detector, charge pump, loop filter and frequency divider still include: self-calibrating frequency circuitry and power supply noise rejection voltage controlled oscillators,
the output end of the phase frequency detector is connected with the input end of the charge pump;
the output end of the charge pump is connected with the input end of the loop filter and the first input end of the power supply noise suppression voltage-controlled oscillator;
the output end of the power supply noise suppression voltage-controlled oscillator is used as a circuit signal output end and is connected with the input end of the frequency divider;
the output end of the frequency divider outputs a feedback clock to one input end of the phase frequency detector, and the other input end of the phase frequency detector receives a reference clock;
two input ends of the self-calibration frequency circuit respectively receive a feedback clock and a reference clock, and an output end of the self-calibration frequency circuit is connected with a second input end of the power supply noise suppression voltage-controlled oscillator.
Preferably, the self-calibration frequency circuit includes: a frequency detector and a state machine control unit,
two input ends of the frequency detector respectively receive a feedback clock and a reference clock, an output end of the frequency detector is connected with an input end of the state machine control unit, and an output end of the state machine control unit is connected with a second input end of the power supply noise suppression voltage-controlled oscillator.
Preferably, the power supply noise suppression voltage-controlled oscillator includes: operational amplifier, PMOS pipe, K bit current source array circuit, resistance, capacitance and delay unit (DELAY CELL), wherein,
the inverting input end of the operational amplifier is used as the first input end of the power supply noise suppression voltage-controlled oscillator, and the positive phase input end of the operational amplifier is grounded through the resistor;
the output end of the operational amplifier is respectively connected with the grid electrode of the PMOS tube and the first input end of the K-bit current source array circuit;
a second input end of the K-bit current source array circuit is used as a second input end of the power supply noise suppression voltage-controlled oscillator;
the source electrode of the PMOS tube is connected with the grid electrode of the PMOS tube through the capacitor on one hand and is connected with a power supply on the other hand; the drain electrode of the PMOS tube is grounded through the resistor;
and the output end of the K-bit current source array circuit is connected with the input end of the delay unit, and the output end of the delay unit is used as the output end of the power supply noise suppression voltage-controlled oscillator.
Preferably, the inverting input terminal of the operational amplifier receives the output of the loop filter;
the K-bit current source array circuit receives the code K output by the self-calibration frequency circuit and switches the wave band of the VCO;
the delay unit outputs a clock signal.
The utility model has the advantages that: the utility model discloses based on traditional phase-locked loop circuit framework, combine self calibration frequency circuit (AFC) and power noise suppression voltage controlled oscillator (SRVCO) circuit design, can have less KVCO (VCO's gain) under the condition that realizes wide tuning range, adapted to the demand to the wide output range of phase-locked loop among the latest large-scale integrated circuit. Compared with the traditional architecture, the performance of improving the output Jitter (Jitter) by about 2-5 times is realized by the voltage-controlled oscillator with the power supply noise suppression capability, and the voltage-controlled oscillator has great advantage in the aspect of suppressing the power supply noise.
Drawings
FIG. 1 is a prior art phase locked loop circuit configuration diagram;
fig. 2 is a block diagram of a phase-locked loop circuit of the present invention;
FIG. 3 is a graph comparing the characteristics of a voltage controlled oscillator KVCO using AFC technology with the voltage controlled oscillator without AFC technology;
fig. 4 is a circuit diagram of the voltage-controlled oscillator with power supply noise suppression according to the present invention.
Detailed Description
The present invention will be further explained with reference to the accompanying drawings.
Referring to fig. 1 and 3, a pll circuit with high power noise rejection ratio of the present invention includes: the phase frequency detector comprises a phase frequency detector 1, a charge pump 2, a loop filter 3, a frequency divider 4, a self-calibration frequency circuit 5 and a power supply noise suppression voltage-controlled oscillator 6.
The output end of the phase frequency detector 1 is connected with the input end of the charge pump 2; the output end of the charge pump 2 is connected with the input end of the loop filter 3 and the first input end of the power supply noise suppression voltage-controlled oscillator 6; the output of the power supply noise suppression voltage-controlled oscillator 6 serves as the circuit signal output and is connected to the input of the frequency divider 4.
The output terminal of the frequency divider 4 outputs the feedback clock FBCLK to one input terminal of the phase frequency detector 1, and the other input terminal of the phase frequency detector 1 receives the reference clock REFCLK.
The self-calibration frequency circuit 5 has two input terminals receiving the feedback clock FBCLK and the reference clock REFCLK, respectively, and an output terminal connected to a second input terminal of the power supply noise suppression voltage-controlled oscillator 6.
The self-calibration frequency circuit 5 includes: a Frequency Detector (FD) and a State Machine control (State Machine) unit. Two input ends of the frequency detector respectively receive the feedback clock FBCLK and the reference clock REFCLK, an output end of the frequency detector is connected with an input end of the state machine control unit, and an output end of the state machine control unit is connected with a second input end of the power supply noise suppression voltage-controlled oscillator 6.
For a phase-locked loop applied in a large-scale digital integrated circuit system, power supply noise is a main factor limiting the performance of a ring oscillator type phase-locked loop, and as the process advances, the phase-locked loop is expected to cover a wider tuning range, so that a larger KVCO is required, and the increased KVCO directly affects the power supply noise suppression capability of the whole phase-locked loop, as shown in formula 1, and as can be easily obtained from the formula, the reduction of the KVCO can directly reduce the influence of the power supply noise on the output clock jitter performance.
Wherein KVCO represents the gain of the VCO; icp represents the charge and discharge current of the charge pump; n represents a Divider frequency dividing ratio; hLPF(s) represents the transfer function of the loop filter; vDD(s) means supply voltage outputInputting a signal; phiout(s) refers to the phase signal of the output clock.
The present invention thus allows the tuning range of the entire voltage controlled oscillator to be extended using self-calibrating frequency technology (AFC) and a smaller KVCO to be implemented in a single BAND, as shown in fig. 3. Because the suppression capability of the KVCO and the power supply noise of the phase-locked loop is in an inverse relation, namely the smaller the KVCO is, the stronger the suppression capability of the phase-locked loop on the power supply noise is, and the better the clock performance of the whole phase-locked loop is.
As shown in fig. 4, the power supply noise suppression voltage-controlled oscillator 6 includes: the circuit comprises an operational amplifier A1, a PMOS tube M1, a K-bit current source array circuit M2, a resistor R1, a capacitor C1 and a delay unit 61.
The inverting input terminal of the operational amplifier a1 serves as the first input terminal of the power supply noise suppression voltage-controlled oscillator 6, and the non-inverting input terminal is grounded through a resistor R1. The output end of the operational amplifier a1 is connected to the gate of the PMOS transistor M1 and the first input end of the current source array circuit M2 for K bits, respectively. A second input of the K-bit current source array circuit M2 serves as a second input of the supply noise suppression voltage controlled oscillator 6. The source electrode of the PMOS tube M1 is connected with the grid electrode of the PMOS tube M1 through a capacitor C1 on one hand and is connected with a power supply VDD on the other hand; the drain of the PMOS transistor M1 is grounded through a resistor R1. The output terminal of the current source array circuit M2 for K bits is connected to the input terminal of the delay unit 61, and the output terminal of the delay unit 61 serves as the output terminal of the power supply noise suppression voltage-controlled oscillator 6.
The inverting input of operational amplifier a1 receives the output VCTRL of the loop filter. The delay unit 61 outputs a clock signal CKOUT. The operational amplifier a1, the PMOS transistor M1, the resistor R1 and the capacitor C1 constitute a voltage-to-current circuit for generating the supply current of the delay unit 61. The K-bit current source array circuit M2 receives the code K output from the self-calibration frequency circuit 5 to implement Band switching of multiple VCOs, which can effectively reduce the whole power supply noise to suppress the KVCO of the voltage controlled oscillator 6. In the figure, VICOThe output of current source array circuit M2 for K bits.
The basic principle is to ensure that the gate-source voltage of the linear regulator is kept constant by a feedforward capacitance coupling mode, so that the output drain current is not influenced by power supply noise, the current mirrored to DELAYCELL is not influenced by the power supply voltage, and a better high-frequency power supply rejection capability can be achieved, and meanwhile, the low-frequency power supply noise capability is determined by the loop gain of the whole linear regulator. The specific formula is as follows:
wherein K represents the gain control bit of the AFC output; gm2 represents the transconductance value of a single MOS tube of the current array; rICORepresents the equivalent output resistance of the delay unit 61 during oscillation; loop(s) represents the loop gain of the linear regulator with feedforward cancellation technique.
Compared with the traditional voltage-controlled oscillator technology of a linear modulator, the voltage-controlled oscillator with the power supply suppression capability can attenuate power supply noise by a factor of gain, the suppression capability of the VCO on the power supply noise is improved, and the suppression effect of the power supply noise of more than 30dB can be realized through simulation.
To sum up, the utility model discloses combine self calibration frequency technique and have the circuit structure of power suppression ability voltage controlled oscillator, can effectively improve output clock signal's jitter performance 2-5 times, have great advantage in the aspect of suppressing the power noise, the simulation result is shown as the following table.
The above embodiments are provided only for the purpose of illustration, not for the limitation of the present invention, and those skilled in the relevant art can make various changes or modifications without departing from the spirit and scope of the present invention, therefore, all equivalent technical solutions should also belong to the scope of the present invention, and should be defined by the claims.
Claims (4)
1. A phase locked loop circuit having a high power supply noise rejection ratio, comprising: phase frequency detector, charge pump, loop filter and frequency divider, its characterized in that still includes: self-calibrating frequency circuitry and power supply noise rejection voltage controlled oscillators,
the output end of the phase frequency detector is connected with the input end of the charge pump;
the output end of the charge pump is connected with the input end of the loop filter and the first input end of the power supply noise suppression voltage-controlled oscillator;
the output end of the power supply noise suppression voltage-controlled oscillator is used as a circuit signal output end and is connected with the input end of the frequency divider;
the output end of the frequency divider outputs a feedback clock to one input end of the phase frequency detector, and the other input end of the phase frequency detector receives a reference clock;
two input ends of the self-calibration frequency circuit respectively receive a feedback clock and a reference clock, and an output end of the self-calibration frequency circuit is connected with a second input end of the power supply noise suppression voltage-controlled oscillator.
2. The phase-locked loop circuit with high power-to-noise rejection ratio of claim 1, wherein the self-calibrating frequency circuit comprises: a frequency detector and a state machine control unit,
two input ends of the frequency detector respectively receive a feedback clock and a reference clock, an output end of the frequency detector is connected with an input end of the state machine control unit, and an output end of the state machine control unit is connected with a second input end of the power supply noise suppression voltage-controlled oscillator.
3. The phase-locked loop circuit with a high power supply noise rejection ratio of claim 1, wherein the power supply noise rejection voltage-controlled oscillator comprises: operational amplifier, PMOS pipe, K bit current source array circuit, resistance, capacitance and delay unit, wherein,
the inverting input end of the operational amplifier is used as the first input end of the power supply noise suppression voltage-controlled oscillator, and the positive phase input end of the operational amplifier is grounded through the resistor;
the output end of the operational amplifier is respectively connected with the grid electrode of the PMOS tube and the first input end of the K-bit current source array circuit;
a second input end of the K-bit current source array circuit is used as a second input end of the power supply noise suppression voltage-controlled oscillator;
the source electrode of the PMOS tube is connected with the grid electrode of the PMOS tube through the capacitor on one hand and is connected with a power supply on the other hand; the drain electrode of the PMOS tube is grounded through the resistor;
and the output end of the K-bit current source array circuit is connected with the input end of the delay unit, and the output end of the delay unit is used as the output end of the power supply noise suppression voltage-controlled oscillator.
4. The phase-locked loop circuit with a high power supply noise rejection ratio of claim 3, wherein an inverting input of said operational amplifier receives an output of said loop filter;
the K-bit current source array circuit receives the code K output by the self-calibration frequency circuit and switches the wave band of the VCO;
the delay unit outputs a clock signal.
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| CN202022764074.6U CN213426145U (en) | 2020-11-25 | 2020-11-25 | Phase-locked loop circuit with high power supply noise rejection ratio |
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