CN111211776B - Phase-locked loop circuit - Google Patents
Phase-locked loop circuit Download PDFInfo
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- CN111211776B CN111211776B CN202010103999.8A CN202010103999A CN111211776B CN 111211776 B CN111211776 B CN 111211776B CN 202010103999 A CN202010103999 A CN 202010103999A CN 111211776 B CN111211776 B CN 111211776B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
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Abstract
The application provides a phase-locked loop circuit, which is used for charging or discharging a loop filter according to up pulse or dn pulse by a self-calibration charge pump, and regulating control voltage output by the loop filter; the self-calibration charge pump is used for improving the current mismatch problem of the traditional charge pump according to the fact that the current pumped in or pumped out by the UP pulse or the DN pulse is the same, matching of the UP current and the DN current of the charge pump is achieved, and therefore the problem of output jitter increase caused by static phase difference and current mismatch when the analog phase-locked loop is locked is reduced.
Description
Technical Field
The application relates to the technical field of electronic circuits, in particular to a phase-locked loop circuit.
Background
In the prior art, in order to make the adjustable range of the output frequency of the phase-locked loop larger, the sensitivity of the output frequency of the voltage-controlled oscillator to the control voltage Vctrl needs to be improved, but if the voltage noise on the control voltage Vctrl is larger, the phase-locked loop output clock will have larger phase noise and jitter; in order to reduce noise, the sensitivity of the output frequency of the voltage controlled oscillator to the control voltage Vctrl has to be reduced, so that this contradicts the requirement for a large output frequency range. Second, when the control voltage Vctrl approaches power or ground, a serious mismatch occurs in the charge pump in the analog pll to the charge-discharge current of the loop filter, resulting in degradation of the pll performance.
Disclosure of Invention
In view of the above, the present application provides a pll circuit to solve the problem that the charge pump in the existing pll circuit is not matched with the charge-discharge current of the loop filter.
The technical scheme adopted by the application is as follows:
the present application provides a phase-locked loop circuit comprising: a frequency phase comparator, a self-calibrating charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider; the frequency phase comparator, the self-calibration charge pump, the loop filter and the voltage-controlled oscillator are connected in sequence; the voltage-controlled oscillator is also connected with the frequency phase comparator through the frequency divider;
the frequency divider is used for dividing the clock signal output by the voltage-controlled oscillator to generate a feedback clock and transmitting the feedback clock to the frequency phase comparator;
the frequency phase comparator is used for comparing the feedback clock with a reference clock and outputting an up pulse or a dn pulse to the self-calibration charge pump;
the self-calibration charge pump pumps current to the loop filter according to the up pulse, and is further used for controlling the loop filter to pump current according to the dn pulse, wherein the pump current is matched with the pump current;
the loop filter is used for adjusting the control voltage output to the voltage-controlled oscillator according to the pumping current or the pumping current so that the voltage-controlled oscillator outputs a clock signal synchronous with the reference clock phase according to the control voltage.
Further, the self-calibration charge pump comprises a self-calibration module and a charge pump module, wherein the self-calibration module is electrically connected with the charge pump module;
the charge pump module is used for generating pumping current according to the up pulse so as to charge the loop filter, so that the control voltage is increased; the charge pump module is further configured to generate a pump-out current to discharge the loop filter from the dn pulse to reduce the control voltage;
the self-calibration module is used for adjusting and controlling the charge pump module so as to enable the pumping current to be matched with the pumping current.
Further, the charge pump includes: the first PMOS tube, the first NMOS tube, the first switch group and the second switch group;
the first switch group and the second switch group are connected in parallel between the first PMOS tube and the first NMOS tube;
the first switch group comprises a second PMOS tube and a second NMOS tube; the second PMOS tube is connected with the second NMOS tube in series, wherein the second PMOS tube is connected with the first PMOS tube; the second NMOS tube is connected with the first NMOS tube;
the second switch group comprises a third PMOS tube and a third NMOS tube; the third PMOS tube is connected with the third NMOS tube in series; the third PMOS tube is connected with the first PMOS tube; the third NMOS tube is connected with the first NMOS tube;
the first switch group and the second switch group are used for being alternately conducted according to the up pulse or the dn pulse so as to generate the pumping current or the pumping current.
Further, the gate of the first PMOS is configured to be connected to a preset dc signal Vbp, so that the pumping current is generated when the second switch group is turned on.
Further, the self-calibration module comprises an amplifier and a capacitor Cd;
the inverting terminal of the amplifier is connected between the third PMOS tube and the third NMOS tube, and the non-inverting terminal of the amplifier is connected between the second PMOS tube and the second NMOS tube;
the first end of the capacitor Cd is connected with the in-phase end of the amplifier, and the second end of the capacitor Cd is grounded;
the output end of the amplifier is connected with the grid electrode of the first NMOS tube, so that the pumping current matched with the pumping current is generated when the first switch group is conducted.
Further, when the reference clock phase advances, the frequency phase comparator outputs the up pulse, and the self-calibrating charge pump controls the loop filter to charge according to the up pulse.
Further, when the reference clock phase lags, the frequency phase comparator outputs the dn pulse; the self-calibrating charge pump controls the loop filter pump discharge according to the dn pulse.
Further, the voltage-controlled oscillator comprises a cross-coupled MOS tube and an LC resonant circuit;
the LC resonance circuit is connected with the cross-coupling MOS tube and comprises an inductor L VCO The first capacitor group C1 and the second capacitor C2;
the LC resonance circuit comprises an inductance L VCO First capacitor group C1 and the first capacitor groupThe two capacitors C2 are connected in parallel, wherein the first capacitor group C1 comprises a plurality of digital switch capacitors connected in parallel, and the second capacitor C2 is an analog regulating capacitor;
the output frequency of the voltage-controlled oscillator and the inductance L VCO The first capacitance set C1 and the second capacitance C2 satisfy the following formula:
wherein said f LCVCO Representing the output frequency of the voltage-controlled oscillator, the L VCO And C1 is the first capacitor group, and C2 is the second capacitor.
Further, the second capacitor C2 is configured to implement fine tuning of the output frequency of the voltage-controlled oscillator;
the first capacitor set C1 is configured to implement coarse adjustment of an output frequency of the voltage-controlled oscillator.
Further, the phase-locked loop circuit is preset with a low-voltage threshold value and a high-voltage threshold value;
when the control voltage is smaller than the low-voltage threshold value, increasing the capacitance value of the first capacitance set C1 to realize phase-locked loop locking;
when the control voltage is larger than or equal to the low-voltage threshold and smaller than the high-voltage threshold, keeping the capacitance value of the first capacitor group C1 unchanged, and realizing phase-locked loop locking by adjusting the capacitance value of the second capacitor C2;
and when the control voltage is larger than or equal to the high-voltage threshold value and smaller than the power supply voltage, reducing the capacitance value of the first capacitance set C1 to realize phase-locked loop locking.
Compared with the prior art, the phase-locked loop circuit provided by the application has the following beneficial effects:
according to the phase-locked loop circuit provided by the application, the self-calibration charge pump charges or discharges the loop filter according to the up pulse or the dn pulse so as to regulate the control voltage output by the loop filter; the voltage-controlled oscillator outputs a clock signal phase-synchronized with the reference clock according to a control voltage output from the loop filter. The self-calibration charge pump is utilized to improve the current mismatch problem of the traditional charge pump, and the matching of the UP current and the DN current of the charge pump is realized, so that the problems of static phase difference and output jitter increase caused by current mismatch when the analog phase-locked loop is locked are reduced. Meanwhile, the phase-locked loop circuit provided by the application adopts the voltage-controlled oscillator with analog and digital double regulation, and can meet the requirement of lower phase noise of an output clock while realizing large-scale adjustable output frequency.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some examples of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a schematic diagram of a prior art phase locked loop.
Fig. 2 shows another prior art phase locked loop schematic.
Fig. 3 shows a schematic diagram of a phase locked loop circuit according to the present application.
Fig. 4 shows a schematic diagram of a self-calibrating charge pump provided by the present application.
Fig. 5 shows a schematic diagram of a voltage controlled oscillator provided by the present application.
Fig. 6 shows a control voltage region division schematic diagram provided by the present application.
Fig. 7 shows a schematic diagram of a finite state machine provided by the present application.
Icon: p1-a first PMOS tube; p2-a second PMOS tube; p3-a third PMOS tube; n1-a first NMOS tube; n2-a second NMOS tube; n3-third NMOS tube.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present application, it should also be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
Phase locked loops are a generating module for clock signals in a number of digital chips. The input reference clock of the phase locked loop is typically a clock signal with low phase noise, typically generated by a crystal oscillator, at a relatively low frequency, but the frequency of the output clock of the phase locked loop is relatively high. Fiber optic communication physical layer chips are typically required to generate clock frequencies of 10-28 GHz and output clock jitter of less than 1 ps.
Two types of conventional pll schemes are typically used, one is an analog pll, as shown in fig. 1, a frequency-phase comparator (PFD) is first used to compare a phase difference between a reference clock and an output clock that is divided by N times, where the comparison result is used to control a charge pump to charge and discharge a loop filter, so as to generate a control voltage Vctrl, and a voltage-controlled oscillator (VCO) outputs an N-frequency clock signal locked with the reference clock phase under the action of the control voltage Vctrl.
Another common type is a digital phase-locked loop, as shown in fig. 2, in which, compared to an analog phase-locked loop, a time-to-digital conversion module (Time to Digital Convertor, TDC) and a digital filter are used to replace a charge pump and a loop filter in the analog phase-locked loop, and a digital signal Dctrl generated by the digital filter is used to adjust the output frequency of a digitally controlled oscillator, and the output of the digitally controlled oscillator also provides a clock signal to the TDC.
Because the high-speed signal transmitting end needs a phase-locked loop with large output frequency adjustable range (10-28 GHz) and small phase noise (jitter is less than 1 ps), in the analog phase-locked loop, in order to make the output frequency adjustable range of the phase-locked loop larger, the sensitivity of the output frequency of the voltage-controlled oscillator to the control voltage Vctrl needs to be improved, but if the voltage noise on the control voltage Vctrl is larger, the phase-locked loop output clock will have larger phase noise and jitter; in order to reduce noise, the sensitivity of the output frequency of the voltage-controlled oscillator to the control voltage Vctrl must be reduced, so this contradicts the requirement for a large output frequency range, and in addition, when the control voltage Vctrl is close to the power supply or ground, a serious mismatch occurs between the charge pump in the analog phase-locked loop and the charge-discharge current of the loop filter, resulting in a reduced performance of the phase-locked loop. Although the digital phase-locked loop is not affected by the analog noise, the TDC is a time measurement circuit, and quantization errors occur, so that deviation is generated on the output clock frequency of the phase-locked loop, and jitter of the output clock is affected.
In order to improve the above-mentioned problems, the present application provides a new pll circuit, please refer to fig. 3, fig. 3 shows a schematic diagram of the circuit provided by the embodiment of the present application.
The phase-locked loop circuit provided by the embodiment of the application comprises: a frequency phase comparator, a self-calibrating charge pump, a loop filter, a voltage controlled oscillator, a buffer, and a divider.
The frequency phase comparator, the self-calibration charge pump are electrically connected, the loop filter and the voltage-controlled oscillator are sequentially connected. The voltage-controlled oscillator is also connected with the frequency phase comparator through a buffer and a frequency divider.
The frequency divider is used for dividing a clock signal (VCO clock) output by the voltage-controlled oscillator to generate a feedback clock and transmitting the feedback clock to the frequency phase comparator; the frequency phase comparator is used for comparing the feedback clock with a reference clock and outputting an up pulse or a dn pulse to the self-calibration charge pump; the self-calibrating charge pump charges or discharges the loop filter according to the up pulse or the dn pulse so as to adjust the control voltage output by the loop filter; wherein the charge and discharge amounts of electricity are the same; the voltage-controlled oscillator outputs a clock signal phase-synchronized with the reference clock according to the control voltage output from the loop filter.
The frequency phase comparator first compares the reference clock with the divided-by-N VCO clock phase, and outputs three states, the first UP, the second DN, and the third idle. When the reference clock phase is advanced, the frequency phase comparator outputs up pulse, when the reference clock phase is retarded, the frequency phase comparator outputs dn pulse, if the phases are the same, the idle state is output.
The self-calibrating charge pump controls the loop filter charge according to the up pulse or the loop filter discharge according to the dn pulse. When the reference clock phase advances and the frequency phase comparator outputs an up pulse, self-calibrating the charge pump current to the loop filter to charge the loop filter, and increasing the control voltage Vctrl; when the reference clock phase lags, the frequency phase comparator outputs dn pulses; the self-calibrating charge pump controls the loop filter to pump out the current discharge according to the dn pulse, and the control voltage Vctrl is reduced in voltage.
Typically, the current pumped in by the charge pump according to the up pulse and pumped out by the dn pulse is the same, which reduces the static phase error. However, if the control voltage Vctrl is raised close to the power supply Vdd or lowered close to ground, the current pumped in by the charge pump according to the up pulse and pumped out by the dn pulse will be severely mismatched. At higher control voltage Vctrl, the pumping current is much smaller than the pumping current, and at lower control voltage Vctrl, the pumping current is much larger than the pumping current. In this way, if the control voltage Vctrl is just too high or too low when the phase-locked loop is locked, the charge pump may have a current mismatch, resulting in a poor ability of the phase-locked loop to suppress phase noise, and a reduced quality of the output clock signal.
For this reason, the self-calibration charge pump is adopted in this embodiment, referring to fig. 4, the self-calibration charge pump includes a self-calibration module and a charge pump module, and the self-calibration module is electrically connected with the charge pump module.
The charge pump module is used for generating UP current (i.e. pumping current) according to the UP pulse so as to charge the loop filter; the charge pump module is also used for generating DN current (i.e. pump-out current) according to DN pulse so as to discharge the loop filter; the self-calibration module is used for adjusting and controlling the charge pump module so as to enable the UP current to be matched with the DN current.
In one possible implementation, the charge pump module is composed of six field effect transistors, P-type metal oxide field effect transistors (PMOS) P1-P3 and N-type metal oxide field effect transistors (NMOS) N1-N3. For example, the charge pump includes: the first PMOS tube P1, the first NMOS tube N1, the first switch group and the second switch group; the first switch group and the second switch group are connected in parallel between the first PMOS tube P1 and the first NMOS tube N1; the first switch group comprises a second PMOS tube P2 and a second NMOS tube N2; the second PMOS tube P2 is connected with the second NMOS tube N2 in series, wherein the second PMOS tube P2 is connected with the first PMOS tube P1; the second NMOS tube N2 is connected with the first NMOS tube N1; the second switch group comprises a third PMOS tube P3 and a third NMOS tube N3; the third PMOS tube P3 is connected in series with the third NMOS tube N3; the third PMOS tube P3 is connected with the first PMOS tube P1; the third NMOS transistor N3 is connected to the first NMOS transistor N1.
The grid electrode of the first PMOS tube P1 is used for being connected with a preset direct current signal Vbp so as to generate UP current when the second switch group is conducted. The gate of the first NMOS transistor N1 is used to access Vbn.
The connection point of the third PMOS tube P3 and the third NMOS tube N3 which are connected in series is set as the E point, and the connection point of the second PMOS tube P2 and the second NMOS tube N2 is set as the F point. The output of the charge pump is point E, and the magnitudes of the current of the charge pumps UP and DN are determined by the gate voltages Vbp and Vbn of the first PMOS transistor P1 and the first NMOS transistor N1, respectively, where Vbp is an externally preset dc voltage, and Vbn is generated by the self-calibration module, so that the current of DN is automatically matched with the current of UP.
The first switch group and the second switch group are respectively controlled by UP and DN pulses generated by the frequency phase comparator and inverse signals ub and db of the UP and DN pulses, and are used for being alternately conducted according to the UP pulse or the DN pulse so as to generate UP current or DN current. And the E point performs charge and discharge operation on the subsequent loop filter through a third PMOS tube P3 and a third NMOS tube N3, and Vctrl (VCO control voltage) is finally generated at the E point. The second PMOS tube P2 and the third PMOS tube P3, the second NMOS tube N2 and the third NMOS tube N3 are symmetrical circuits, namely the first switch group and the second switch group are symmetrical circuits, so that the current at the point F is the complementary current at the point E, namely when the point E is the UP pumping current, the current at the point F is the DN pumping current; when the E point is DN pumping current, the F point is UP pumping current; when point E is idle, neither pumping current nor pumping current is present, and point F is the simultaneous pumping and pumping current.
The self-calibration module comprises an amplifier and a capacitor Cd; the inverting terminal of the amplifier is connected between the third PMOS tube P3 and the third NMOS tube N3, namely E point, and the non-inverting terminal of the amplifier is connected between the second PMOS tube P2 and the second NMOS tube N2; i.e. point F. The first end of the capacitor Cd is connected with the same-phase end of the amplifier, and the second end of the capacitor Cd is grounded; the output end of the amplifier is connected with the grid electrode of the first NMOS tube N1 so as to generate DN current matched with UP current when the first switch group is conducted.
The capacitor Cd is used as a redundant capacitor, the amplifier is used as an error amplifier, if the UP current and DN current generated by the charge pump module are not matched, the F point current can continuously accumulate error charges on the redundant capacitor Cd, and finally the voltage of the redundant capacitor Cd is Vdd or ground; if the UP current and DN current are matched, no charge accumulation occurs on the redundant capacitor Cd, and the voltage of the redundant capacitor Cd is constant at a certain direct current voltage.
Based on the above-mentioned earnest, the present embodiment adopts an amplifier to sense the difference between the control voltage Vctrl and the voltage of the redundant capacitor Cd, and amplifies and feeds back the difference to the gate of the first NMOS transistor N1, so as to change the magnitude of DN current, and realize elimination of the difference between the control voltage Vctrl and the voltage of the redundant capacitor Cd. When the voltage of the redundant capacitor Cd is the same as the control voltage Vctrl, the voltage of the redundant capacitor Cd is neither Vdd nor ground, thereby determining that the DN current is equal to the UP current.
The relation between the output frequency of the voltage controlled oscillator VCO and the control voltage Vctrl satisfies the following formula:
f VCO ＝K VCO *Vctrl；
wherein K is VCO For the regulation gain of the voltage controlled oscillator VCO, vctrl is the control voltage output by the loop filter to the voltage controlled oscillator.
Aiming at the application scene with a large adjustable frequency range of the phase-locked loop, K needs to be adjusted VCO Designed to be larger so that a larger range of adjustable frequencies can still be output when the control voltage Vctrl varies over a smaller range.
For application scenarios requiring low clock jitter applications, K needs to be set VCO Designed to be small so as to reduce the phase noise contribution of noise on the control voltage Vctrl to the output clock.
For the high-speed signal transmitting end, the phase-locked loop is required to provide a frequency output with a larger adjustable range, and the phase noise of the output clock is required to be kept low, so that K is caused VCO The values of (2) are relatively difficult to design.
In order to solve the above problems, the embodiment of the present application adopts a voltage-controlled oscillator using analog fine tuning and digital coarse tuning, referring to fig. 5, the voltage-controlled oscillator includes a cross-coupled MOS transistor and an LC resonant circuit. The LC resonance circuit is connected with the cross-coupling MOS tube and comprises an inductor L VCO The first capacitor group C1 and the second capacitor C2; the LC resonance circuit includes an inductance L VCO The first capacitor group C1 and the second capacitor C2 are connected in parallel, wherein the first capacitor group C1 includes a plurality of digital switch capacitors connected in parallel, the capacitance value of the digital switch capacitors is controlled by the input digital signal, and the second capacitor C2 is an analog adjustment capacitor, and the capacitance value of the second capacitor C2 changes along with the input control voltage Vctrl.
Output frequency and inductance L of voltage-controlled oscillator VCO The first capacitor group C1 and the second capacitor C2 satisfy the following formula:
wherein f LCVCO Representing the output frequency of the voltage-controlled oscillator, L VCO The capacitor is an inductor, C1 is a first capacitor group, and C2 is a second capacitor.
The second capacitor C2 is used for realizing fine tuning of the output frequency of the voltage-controlled oscillator; the first switch group C1 is used for realizing coarse adjustment of the output frequency of the voltage-controlled oscillator. In this embodiment, the second capacitor C2 is an analog fine tuning capacitor, and the tuning range is smaller when the control voltage Vctrl is changed, but the accuracy is high. The first capacitor group C1 is a digital coarse capacitor, and has a wide adjustable range but low resolution.
When the phase lock loop circuit is phase locked, the capacitance of the first capacitor set C1 is unchanged, and only the control voltage Vctrl finely changes the output phase of the voltage-controlled oscillator through the second capacitor C2, namely analog fine tuning, at this time, K VCO The value is smaller, and clock output with lower phase noise is realized.
When the output frequency of the voltage-controlled oscillator needs to be changed, the phase-locked loop adjusts the first capacitor set C1, so as to realize a larger range of frequency adjustment, namely digital coarse adjustment, wherein the digital control signal of the first capacitor set C1 is determined by the magnitude of the control voltage Vctrl.
In this embodiment, the pll circuit presets a low voltage threshold and a high voltage threshold; wherein, the low voltage threshold is vdd×3/8, the high voltage threshold is vdd×5/8, and Vdd refers to the power supply voltage. When Vctrl is below the low voltage threshold or above the voltage threshold, it is assumed that the analog fine tuning second capacitance C2 is insufficient to achieve phase locked loop lock, and the coarse tuning capacitor first capacitance set C1 is required to be adjusted.
In one possible implementation, the voltage region of the control voltage Vctrl is divided into three region ranges, as shown in fig. 6.
Region S1: when the control voltage is smaller than the low-voltage threshold value, increasing the capacitance value of the first capacitance set C1 to realize phase-locked loop locking;
region S2: when the control voltage is larger than or equal to the low-voltage threshold value and smaller than the high-voltage threshold value, keeping the capacitance value of the first capacitor group C1 unchanged, and realizing phase-locked loop locking by adjusting the capacitance value of the second capacitor C2;
region S3: when the control voltage is greater than or equal to the high voltage threshold and is smaller than the direct current voltage Vdd, the capacitance of the first capacitor group C1 is reduced to realize phase-locked loop locking.
The phase-locked loop circuit compares the control voltage Vctrl with the voltages of the low voltage threshold and the high voltage threshold using a threshold decision module, and then feeds the results into a finite state machine. The workflow of the finite state machine is as shown in fig. 7, when the voltage range of the control voltage Vctrl is in the region S1, the capacitance value of the first capacitor group C1 needs to be increased; when the voltage range area S2 of the control voltage Vctrl is controlled, the first capacitor group C1 is not required to be changed, and the locking of the phase-locked loop can be realized by simulating and finely adjusting the capacitance value of the second capacitor C2; when the voltage range of the control voltage Vctrl is in the region S3, the capacitance of the first capacitor group C1 is larger, and the decrease of C1 is required.
It should be noted that each adjustment needs a delay module to prevent the problem of unstable phase-locked loop. The clock of the finite state machine is provided by a signal of the VCO clock after N frequency division, and the voltage range of the control unit Vctrl is in S2 when the phase-locked loop is locked finally through the adjustment of the first capacitor bank C1 by the finite state machine, and is in a range between the low voltage threshold and the high voltage threshold, so that the influence of the control voltage Vctrl on the mismatch of the charge pump current due to too high or too low voltage can be reduced.
In summary, in the pll circuit provided by the present application, the self-calibration charge pump charges or discharges the loop filter according to the up pulse or the dn pulse to adjust the control voltage output by the loop filter; the voltage-controlled oscillator outputs a clock signal phase-synchronized with the reference clock according to the control voltage output from the loop filter. The self-calibration charge pump is utilized to improve the current mismatch problem of the traditional charge pump, and the matching of the UP current and the DN current of the charge pump is realized, so that the problems of static phase difference and output jitter increase caused by current mismatch when the analog phase-locked loop is locked are reduced. Meanwhile, the phase-locked loop circuit provided by the application adopts the voltage-controlled oscillator with analog and digital double regulation, and can meet the requirement of lower phase noise of an output clock while realizing large-scale adjustable output frequency. In addition, the application of the finite state machine ensures that the voltage-controlled oscillator control voltage does not exceed the limit of the charge pump when the phase-locked loop stably works, thereby further reducing the influence of current mismatch of the charge pump. Meanwhile, the time measurement module TDC is not needed, so that the problem of clock jitter caused by TDC errors does not occur.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (8)
1. A phase-locked loop circuit, the phase-locked loop circuit comprising:
a frequency phase comparator, a self-calibrating charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider;
the frequency phase comparator, the self-calibration charge pump, the loop filter and the voltage-controlled oscillator are connected in sequence;
the voltage-controlled oscillator is also connected with the frequency phase comparator through the frequency divider;
the frequency divider is used for dividing the clock signal output by the voltage-controlled oscillator, generating a feedback clock and transmitting the feedback clock to the frequency phase comparator;
the frequency phase comparator is used for comparing the feedback clock with a reference clock and outputting an up pulse or a dn pulse to the self-calibration charge pump;
the self-calibration charge pump pumps current to the loop filter according to the up pulse, and is further used for controlling the loop filter to pump current according to the dn pulse, wherein the pump current is matched with the pump current;
the loop filter is used for adjusting the control voltage output to the voltage-controlled oscillator according to the pumping current or the pumping current so as to enable the voltage-controlled oscillator to output a clock signal synchronous with the reference clock phase according to the control voltage;
the self-calibration charge pump comprises a self-calibration module and a charge pump module, and the self-calibration module is electrically connected with the charge pump module;
the charge pump module is used for generating pumping current according to the up pulse so as to charge the loop filter, so that the control voltage is increased; the charge pump module is further configured to generate a pump-out current to discharge the loop filter from the dn pulse to reduce the control voltage;
the self-calibration module is used for adjusting and controlling the charge pump module so as to enable the pumping current to be matched with the pumping current;
the charge pump includes: the first PMOS tube, the first NMOS tube, the first switch group and the second switch group;
the first switch group and the second switch group are connected in parallel between the first PMOS tube and the first NMOS tube;
the first switch group comprises a second PMOS tube and a second NMOS tube; the second PMOS tube is connected with the second NMOS tube in series, wherein the second PMOS tube is connected with the first PMOS tube; the second NMOS tube is connected with the first NMOS tube;
the second switch group comprises a third PMOS tube and a third NMOS tube; the third PMOS tube is connected with the third NMOS tube in series; the third PMOS tube is connected with the first PMOS tube; the third NMOS tube is connected with the first NMOS tube;
the first switch group and the second switch group are used for being alternately conducted according to the up pulse or the dn pulse so as to generate the pumping current or the pumping current.
2. The pll circuit of claim 1, wherein a gate of the first PMOS is configured to be connected to a preset dc signal Vbp, so that the pumping current is generated when the second switch set is turned on.
3. The phase-locked loop circuit of claim 2, wherein the self-calibration module comprises an amplifier and a capacitor Cd;
the inverting terminal of the amplifier is connected between the third PMOS tube and the third NMOS tube, and the non-inverting terminal of the amplifier is connected between the second PMOS tube and the second NMOS tube;
the first end of the capacitor Cd is connected with the in-phase end of the amplifier, and the second end of the capacitor Cd is grounded;
the output end of the amplifier is connected with the grid electrode of the first NMOS tube, so that the pumping current matched with the pumping current is generated when the first switch group is conducted.
4. The phase locked loop circuit of claim 1 wherein the frequency phase comparator outputs the up pulse when the reference clock phase advances, the self-calibrating charge pump controlling the loop filter to charge in accordance with the up pulse.
5. The phase locked loop circuit of claim 4 wherein the frequency phase comparator outputs the dn pulse when the reference clock phase lags; the self-calibrating charge pump controls the loop filter pump discharge according to the dn pulse.
6. The phase-locked loop circuit of claim 1, wherein the voltage-controlled oscillator comprises a cross-coupled MOS transistor and an LC resonant circuit;
the LC resonance circuit is connected with the cross-coupling MOS tube and comprises an inductor L VCO The first capacitor group C1 and the second capacitor C2;
the LC resonance circuit comprises an inductance L VCO The first capacitor group C1 and the second capacitor C2 are connected in parallel, wherein the first capacitor group C1 comprises a plurality of digital switch capacitors connected in parallel, and the second capacitor C2 is an analog regulating capacitor;
the output frequency of the voltage-controlled oscillatorRate and the inductance L VCO The first capacitance set C1 and the second capacitance C2 satisfy the following formula:
wherein said f LCVCO Representing the output frequency of the voltage-controlled oscillator, the L VCO And C1 is the first capacitor group, and C2 is the second capacitor.
7. The phase-locked loop circuit of claim 6, wherein the second capacitor C2 is configured to achieve fine tuning of the output frequency of the voltage-controlled oscillator;
the first capacitor set C1 is configured to implement coarse adjustment of an output frequency of the voltage-controlled oscillator.
8. The phase-locked loop circuit of claim 7, wherein the phase-locked loop circuit is pre-set with a low voltage threshold and a high voltage threshold;
when the control voltage is smaller than the low-voltage threshold value, increasing the capacitance value of the first capacitance set C1 to realize phase-locked loop locking;
when the control voltage is larger than or equal to the low-voltage threshold and smaller than the high-voltage threshold, keeping the capacitance value of the first capacitor group C1 unchanged, and realizing phase-locked loop locking by adjusting the capacitance value of the second capacitor C2;
and when the control voltage is larger than or equal to the high-voltage threshold value and smaller than the power supply voltage, reducing the capacitance value of the first capacitance set C1 to realize phase-locked loop locking.
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| CN202010103999.8A CN111211776B (en) | 2020-02-20 | 2020-02-20 | Phase-locked loop circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1481076A (en) * | 2002-07-17 | 2004-03-10 | 威盛电子股份有限公司 | Circuit of phase locked loop of charge pump |
| CN101483434A (en) * | 2008-01-11 | 2009-07-15 | 上海锐协微电子科技有限公司 | Voltage control oscillator with low tuning gain variance |
| CN102545600A (en) * | 2010-12-13 | 2012-07-04 | 立锜科技股份有限公司 | Power supply circuit capable of adaptively adjusting input and power supply method |
| JP2014204533A (en) * | 2013-04-03 | 2014-10-27 | 学校法人福岡大学 | Voltage adjusting device and motor driver having the same |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1481076A (en) * | 2002-07-17 | 2004-03-10 | 威盛电子股份有限公司 | Circuit of phase locked loop of charge pump |
| CN101483434A (en) * | 2008-01-11 | 2009-07-15 | 上海锐协微电子科技有限公司 | Voltage control oscillator with low tuning gain variance |
| CN102545600A (en) * | 2010-12-13 | 2012-07-04 | 立锜科技股份有限公司 | Power supply circuit capable of adaptively adjusting input and power supply method |
| JP2014204533A (en) * | 2013-04-03 | 2014-10-27 | 学校法人福岡大学 | Voltage adjusting device and motor driver having the same |
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