CN113452366B - PLL circuit and electronic equipment - Google Patents

PLL circuit and electronic equipment Download PDF

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Publication number
CN113452366B
CN113452366B CN202110832568.XA CN202110832568A CN113452366B CN 113452366 B CN113452366 B CN 113452366B CN 202110832568 A CN202110832568 A CN 202110832568A CN 113452366 B CN113452366 B CN 113452366B
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current
pll circuit
charge pump
voltage
input module
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CN113452366A (en
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田辉群
宋康
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Hytera Communications Corp Ltd
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Hytera Communications Corp Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

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Abstract

The invention provides a PLL circuit and an electronic device, the PLL circuit includes: a charge pump and a current input module; the charge pump is used for receiving a control signal, and the control signal is used for controlling the charging current and the discharging current of the charge pump; one end of the current input module is connected with the voltage input end, and the other end of the current input module is connected with the output end of the charge pump; the current input module is used for outputting target current. That is, the PLL circuit is connected to a current input module externally to the output end of the charge pump, so as to change the on/off time sequence of the charge pump of the PLL circuit, and further change the fractional modulation mode, thereby achieving the purpose of optimizing fractional spurious.

Description

PLL circuit and electronic equipment
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a PLL circuit and an electronic device.
Background
In digital logic circuit design, a frequency divider is a basic circuit; which is typically used to divide a given frequency to obtain the desired target frequency.
Based on the integer frequency divider, the implementation mode is simpler, and the method can be realized by adopting a standard counter or adopting a programmable logic device design.
However, in some cases, when the clock source is not an integer multiple of the desired target frequency, it is necessary to divide the clock source by a fractional divider. For example, the frequency division coefficients are half integer frequency dividers of 2.5, 3.5, 7.5, etc.
Further, in the PLL (Phase Locked Loop, phase-locked loop) frequency synthesis technique, in order to reduce frequency steps while ensuring low in-band internal noise, it is also necessary to use a PLL circuit including a fractional divider. However, the use of fractional division necessarily creates fractional spurs, which severely degrade the received and transmitted metrics.
How to suppress the fractional spurious of the PLL circuit is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a PLL circuit and an electronic device, which have the following technical solutions:
a PLL circuit, the PLL circuit comprising: a charge pump and a current input module;
the charge pump is used for receiving a control signal, and the control signal is used for controlling the charging current and the discharging current of the charge pump;
one end of the current input module is connected with the voltage input end, and the other end of the current input module is connected with the output end of the charge pump;
the current input module is used for outputting target current.
Preferably, in the PLL circuit, a difference between the discharge current and the charge current is equal to the target current.
Preferably, in the PLL circuit, the current input module is a constant current source.
Preferably, in the PLL circuit, the current input module is a load resistor;
wherein, the first end of the load resistor is connected with the voltage input end;
and the second end of the load resistor is connected with the output end of the charge pump.
Preferably, in the PLL circuit, the current input module includes: a triode, a first resistor, a second resistor, and first to third capacitors;
the first end of the first resistor is connected with the first end of the first capacitor, and the connecting node is connected with the base electrode of the triode;
the second end of the first resistor and the second end of the first capacitor are grounded respectively;
the first end of the second capacitor and the first end of the third capacitor are respectively connected with the first end of the second resistor, and the connecting node is connected with the emitter of the triode;
the second end of the second capacitor and the second end of the third capacitor are grounded respectively;
the second end of the second resistor is connected with the voltage input end;
and the collector electrode of the triode is connected with the output end of the charge pump.
Preferably, in the PLL circuit described above, the PLL circuit further includes: a loop filter;
the input end of the loop filter is connected with the output end of the charge pump;
the loop filter is used for generating a loop control voltage based on the sum value of the charging current, the discharging current and the target current.
Preferably, in the PLL circuit described above, the PLL circuit further includes: a voltage controlled oscillator;
the input end of the voltage-controlled oscillator is connected with the output end of the loop filter;
the output end of the voltage-controlled oscillator is used as the output end of the PLL circuit;
the loop control voltage is used to control the frequency of the output signal of the voltage controlled oscillator.
Preferably, in the PLL circuit described above, the PLL circuit further includes: a fractional divider;
the input end of the fractional frequency divider is connected with the output end of the voltage-controlled oscillator;
the fractional divider is used for receiving the output signal of the voltage-controlled oscillator and generating a feedback signal.
Preferably, in the PLL circuit described above, the PLL circuit further includes: a phase frequency detector;
the first input end of the phase frequency detector is used for receiving a phase frequency detection signal;
the second input end of the phase frequency detector is connected with the output end of the fractional frequency divider and is used for receiving the feedback signal;
the output end of the phase frequency detector is connected with the control end of the charge pump;
the phase frequency detector is used for generating the control signal according to the phase frequency detection signal and the feedback signal.
An electronic device comprising the PLL circuit of any of the above.
Compared with the prior art, the invention has the following beneficial effects:
the PLL circuit provided by the present invention includes: a charge pump and a current input module; the charge pump is used for receiving a control signal, and the control signal is used for controlling the charging current and the discharging current of the charge pump; one end of the current input module is connected with the voltage input end, and the other end of the current input module is connected with the output end of the charge pump; the current input module is used for outputting target current. That is, the PLL circuit is connected to a current input module externally to the output end of the charge pump, so as to change the timing sequence of the charge pump of the PLL circuit, and further change the fractional modulation mode, thereby achieving the purpose of optimizing fractional spurious. The charge pump and the frequency divider in the PLL circuit are integrated on a phase-locked loop chip, and the loop filter and the voltage-controlled oscillator are arranged outside the phase-locked loop chip; in general, the optimization of fractional spurious is required to depend on a phase-locked loop chip, but the PLL circuit provided by the invention is added with a current input module, so that the time sequence of a charge pump of the PLL circuit can be changed, and then the fractional modulation mode is changed, so that the PLL circuit does not need to modify a fractional frequency division modulation method in the phase-locked loop chip, and the fractional spurious can be improved through the current input module connected with the output end of the charge pump of the phase-locked loop chip, so that the optimization of the fractional spurious of the PLL circuit is independent of the phase-locked loop chip.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a PLL circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of another PLL circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a PLL circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of still another PLL circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of still another PLL circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of still another PLL circuit according to an embodiment of the present invention;
fig. 7 is a schematic diagram of still another PLL circuit according to an embodiment of the present invention;
fig. 8 is a schematic diagram of still another PLL circuit according to an embodiment of the present invention;
fig. 9 is a schematic diagram of still another PLL circuit according to an embodiment of the present invention;
FIG. 10 is a waveform diagram illustrating a conventional PLL circuit locked;
FIG. 11 is a diagram illustrating spurious analysis during locking of a conventional PLL circuit;
fig. 12 is a schematic waveform diagram of a PLL circuit according to an embodiment of the present invention;
fig. 13 is a schematic diagram of spurious analysis during locking of a PLL circuit according to an embodiment of the present invention;
FIG. 14 is another equivalent schematic diagram of the spurious analysis schematic diagram of FIG. 13.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides a novel PLL circuit structure, which can effectively inhibit decimal spurious of the PLL circuit and further improve the performance of the PLL circuit.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 1, fig. 1 is a schematic diagram of a PLL circuit according to an embodiment of the invention.
The PLL circuit includes: the charge pump CP and the current input module 11.
The charge pump CP is configured to receive a control signal, and the control signal is configured to control a charging current and a discharging current of the charge pump CP.
One end of the current input module 11 is connected to the voltage input end VCC, and the other end is connected to the output end of the charge pump CP.
The current input module 11 is configured to output a target current.
In this embodiment, the control signal is configured to control an operation state of the charge pump CP, where the operation state of the charge pump CP includes at least a charging state and a discharging state; the charge pump CP is in a charging state and is used for conveying charging current; the charge pump CP is in a discharge state for delivering a discharge current.
Further, based on the PLL circuit structure of the current charge pump CP, the output end of the charge pump CP is externally connected with a current input module 11, so as to change the timing sequence of the PLL circuit charge pump, and further change the decimal modulation mode, thereby achieving the purpose of optimizing decimal spurious.
In addition, the charge pump of the PLL circuit is integrated on the phase-locked loop chip, and in general, the optimization of the fractional spurious is required to depend on the phase-locked loop chip, and the current input module is added at the current pump output end of the phase-locked loop chip, so that the time sequence of the charge pump of the PLL circuit can be changed, and the fractional modulation mode is changed, so that the PLL circuit does not need to change the fractional frequency division modulation method of the frequency divider integrated in the phase-locked loop chip, the fractional spurious can be improved through the current control module connected with the charge pump output end of the phase-locked loop chip, and the optimization of the fractional spurious is not dependent on the phase-locked loop chip.
Further, according to the above embodiment of the present invention, a difference between the discharging current and the charging current is equal to the target current. It should be noted that, in one working period, the discharge current has at least one current value which is not 0, the ratio of the product of the absolute value of the current value and the maintaining time of the current value to the working period is a first ratio, in one working period, the charge current has at least one current value which is not 0, the ratio of the product of the absolute value of the current value and the maintaining time of the current value to the working period is a second ratio, and the difference between the discharge current and the charge current is the difference between the first ratio and the second ratio, that is, the difference between the first ratio and the second ratio is equal to the target current. It should be further noted that, in one working period, the discharge current may further have a plurality of current values other than 0, and when in one working period, the discharge current has a plurality of current values other than 0, the obtaining the first ratio includes: obtaining products of absolute values of current values which are not 0 and maintaining time of the absolute values, and obtaining sum values of the products, wherein the first ratio is a ratio of the sum values to a working period; similarly, when there are a plurality of currents other than 0 in the charging current in one operation period, a second ratio can be obtained according to the above calculation method.
Specifically, as shown in FIG. 12, I in FIG. 10 SOURCE Representing a charging current, in one working cycle, the charging current having 6 current values other than 0, the obtaining a first ratio value comprising: obtaining products of the absolute values of the 6 currents which are not 0 and the respective maintaining time of the currents, and obtaining sum values of the products, wherein the first ratio is a ratio of the sum values to a working period; FIG. 10I SINX Representing the charge current, in one operating cycle, the discharge current has 6 current values other than 0, the second ratio being obtained comprising: obtaining the products of the absolute values of the 6 current values which are not 0 and the respective maintaining time, and obtaining the sum value of the products, wherein the second ratio is the ratio of the sum value to the working period.
In this embodiment, the current finally output by the charge pump and the current input module is: and a current after the discharge current, the charge current and the target current are superimposed.
Further, according to the above embodiment of the present invention, referring to fig. 2, fig. 2 is a schematic diagram of another PLL circuit according to the embodiment of the present invention.
The PLL circuit further includes: loop filter LPF.
The input end of the loop filter LPF is connected to the output end of the charge pump CP.
The loop filter LPF is configured to generate a loop control voltage based on the charge current, the discharge current, and a current after the target current is superimposed.
In this embodiment, the loop filter LPF performs a filtering process on the current finally output from the charge pump CP and the current input module 11, and generates a loop control voltage CV.
Optionally, referring to fig. 3, fig. 3 is a schematic diagram of still another PLL circuit according to an embodiment of the invention.
The loop filter LPF is an RC filter or a linear filter.
As shown in fig. 3, the loop filter LPF is an RC filter that is composed of a plurality of capacitors C and a plurality of resistors R.
Further, according to the above embodiment of the present invention, referring to fig. 4, fig. 4 is a schematic diagram of still another PLL circuit according to the embodiment of the present invention.
The PLL circuit further includes: a voltage controlled oscillator VCO.
The input end of the voltage controlled oscillator VCO is connected to the output end of the loop filter LPF.
The loop control voltage CV is used to control the frequency of the output signal of the voltage controlled oscillator VCO.
In this embodiment, the loop control voltage CV is used to control the frequency of the output signal of the VCO, and in general, when the loop control voltage CV is at a high level, the frequency of the output signal of the VCO increases; when the loop control voltage CV is low, the frequency of the output signal of the voltage controlled oscillator VCO decreases.
Further, according to the above embodiment of the present invention, referring to fig. 5, fig. 5 is a schematic diagram of still another PLL circuit according to the embodiment of the present invention.
The PLL circuit further includes: and the fractional frequency divider DIV and the current pump CP are integrated in a phase-locked loop chip.
An input terminal of the fractional divider DIV is connected to an output terminal of the voltage controlled oscillator VCO.
The fractional divider DIV is configured to receive an output signal of the voltage controlled oscillator VCO and generate a feedback signal.
In this embodiment, the frequency division coefficient of the fractional frequency divider DIV depends on the actual requirement, and further performs frequency division processing on the output signal of the voltage-controlled oscillator VCO according to the frequency division coefficient, so as to generate the feedback signal.
Further, according to the above embodiment of the present invention, referring to fig. 6, fig. 6 is a schematic diagram of still another PLL circuit according to the embodiment of the present invention.
The PLL circuit further includes: and the phase frequency detector PFD, the fractional frequency divider and the current pump are integrated in a phase-locked loop chip.
A first input terminal of the phase frequency detector PFD is used for receiving a phase frequency signal V REF 。
A second input end of the phase frequency detector PFD is connected with an output end of the fractional frequency divider DIV for receiving the feedback signal V FB 。
The output end of the phase frequency detector PFD is connected to the control end of the charge pump CP.
The phase frequency detector PFD is used for detecting the phase frequency signal V REF And the feedback signal V FB And generating the control signal.
In this embodiment, the control signal is configured to control an operation state of the charge pump CP, where the operation state of the charge pump CP includes at least a charging state and a discharging state; in a charging state, for delivering a charging current; in the discharge state, for delivering a discharge current. And thus the magnitude of the loop control voltage CV.
Further, according to the above embodiment of the present invention, referring to fig. 7, fig. 7 is a schematic diagram of still another PLL circuit according to the embodiment of the present invention.
The current input module 11 is a constant current source 12.
In this embodiment, the constant current source 12 is a constant current source for outputting a preset target current.
Further, according to the above embodiment of the present invention, referring to fig. 8, fig. 8 is a schematic diagram of still another PLL circuit according to the embodiment of the present invention.
The current input module 11 is a load resistor Rs.
Wherein a first terminal of the load resistor Rs is connected to the voltage input terminal VCC.
A second terminal of the load resistor Rs is connected to the output terminal of the charge pump CP.
In this embodiment, the resistance of the load resistor Rs depends on the magnitude of the target current and the voltage of the voltage input terminal.
Further, according to the above embodiment of the present invention, referring to fig. 9, fig. 9 is a schematic diagram of still another PLL circuit according to the embodiment of the present invention.
The current input module 11 includes: transistor Q, first resistance R1, second resistance R2, first through third electric capacity C1-C3.
The first end of the first resistor R1 is connected to the first end of the first capacitor C1, and the connection node is connected to the base of the triode Q.
The second end of the first resistor R1 and the second end of the first capacitor C1 are grounded respectively.
The first end of the second capacitor C2 and the first end of the third capacitor C3 are respectively connected with the first end of the second resistor R2, and the connection node is connected with the emitter of the triode Q.
The second end of the second capacitor C2 and the second end of the third capacitor C3 are grounded respectively.
The second end of the second resistor R2 is connected to the voltage input VCC.
The collector of the triode Q is connected with the output end of the charge pump CP.
Further, based on all the above embodiments of the present invention, the principle of the PLL circuit provided by the present invention is explained again below:
first, analysis is based on the fractional spur condition of a conventional PLL circuit.
For example, to achieve n+1/6 frequency division, among 6 frequency divisions, 5 times are divided by N and 1 time is divided by n+1, and then the cumulative frequency is (5·n+ (n+1))/6=n+1/6.
Referring to fig. 10, fig. 10 is a waveform diagram of a conventional PLL circuit in a locked state.
Wherein V is REF Representing a phase-discriminating reference frequency waveform; v (V) FB An output signal waveform representing the fractional divider; i SOURCE A waveform representing a charge state of the charge pump; i SINX A waveform representing a discharge state of the charge pump; i CP Representing the final output current waveform of the charge pump.
Referring to fig. 11, fig. 11 is a schematic diagram illustrating spurious analysis during locking of a conventional PLL circuit.
Assuming that the period of the phase discrimination reference frequency of the phase discriminator is T, for the convenience of analysis, a time constant T is set 0 The time constant t 0 The basic unit of the abscissa of the spurious component diagram is t 1 、t 2 、t 3 、t 4 、t 5 、t 6 At t 0 For 1/6 division, the fractional spurious distribution period is 6*T, the spurious caused by fractional division is low, the influence on the whole PLL circuit is the greatest, and the filtering is the most difficult.
As shown in fig. 11, for each spurious point phase, the following relationship exists:
θ 1 ＝θ(t 1 )＝θ(t 4 )-π；
θ 2 ＝θ(t 2 )＝θ(t 5 )-π；
θ 3 ＝θ(t 3 )＝θ(t 6 )-π。
then, the spurious signal with the period of 6*T is subjected to Fourier transform to have the frequency of omega 0 Only fundamental wave items are taken to obtain:
f(t)＝I cp ·K·6·t 0 ·[sin(ω 0 ·t+θ 1 )+sin(ω 0 ·t+θ 2 )+sin(ω 0 ·t+θ 3 )]
wherein K represents the Fourier transform coefficient of the square wave, I cp Is based on locksFixed value, t of frequency setting output by phase loop circuit 0 Is also a fixed value that is set.
Thus, fractional spurious conditions of conventional PLL circuits are available.
And secondly, analyzing decimal spurious conditions of the PLL circuit provided by the embodiment of the invention.
Referring to fig. 12, fig. 12 is a waveform diagram of a PLL circuit lock state according to an embodiment of the present invention.
For example, a constant current source is added to the output end of the charge pump, and the output target current is set as follows: 4.t 0 ·I CP T; the locking waveform is shown in fig. 12.
Wherein V is REF Representing a phase-discriminating reference frequency waveform; v (V) FB An output signal waveform representing the fractional divider; i SOURCE A waveform representing a charge state of the charge pump; i SINX A waveform representing a discharge state of the charge pump; i CP Representing the final output current waveform of the charge pump.
At this time, I SINX Ratio I SOURCE Big 4. T 0 ·I CP and/T. It should be noted that the stability conditions of the conventional PLL circuit are: in a period T, the current of the current pump CP needs to meet that the difference between the charging current and the discharging current is 0, but in the embodiment of the present application, a constant current source is added to the output end of the current pump, and the target current is as follows: 4.t 0 ·I CP T, thereby to ensure the stability of PLL circuit, I SINX Ratio I SOURCE Big 4. T 0 ·I CP /T。
Referring to fig. 13, fig. 13 is a schematic diagram showing spurious analysis during locking of PLL circuit according to an embodiment of the present invention, I 11 Representing the waveform of a constant current source, in effect I CP Become I CP1 And I CP -I CP1 ＝4·t 0 ·I CP /T。
Referring to fig. 14, fig. 14 is another equivalent schematic diagram of the spurious analysis schematic diagram of fig. 13.
The same method as above is adopted for the pair I CP1 Fourier transform can be performed to obtain:
f 1 '(t)＝I CP ·K·6·t 0 ·[(1-8·t 0 /(3·T))Sin(ω 0 ·t+θ 1 )+(1-4·t 0 /T)Sin(ω 0 ·t+θ 2 )+(1-4·t 0 /T)Sin(ω 0 ·t+θ 3 )]
then by comparing f (t) and f 1 (t) it can be seen that for the same phase signal amplitude, f 1 (t) is lower than f (t), i.e.:
for the fundamental wave of spurious signals, the amplitude of the PLL circuit provided by the invention is lower than that of a traditional PLL circuit.
In some specific practices, it was found that about 15dB could be optimized.
As can be seen from the above description, the PLL circuit provided by the present invention is configured to change the on/off timing of the charge pump of the PLL circuit by externally connecting a current input module to the output end of the charge pump, thereby changing the fractional modulation mode, and achieving the purpose of optimizing fractional spurious emissions.
Moreover, the improved mode has no dependence on the PLL circuit, does not need the PLL circuit to open any authority, and has low improved cost.
Based on all the above embodiments of the present invention, in another embodiment of the present invention, there is also provided an electronic device including the PLL circuit described in the above embodiment.
The PLL circuit and the electronic device provided by the present invention are described in detail, and specific examples are applied to illustrate the principles and embodiments of the present invention, where the above description of the embodiments is only for helping to understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include, or is intended to include, elements inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (9)

1. A PLL circuit, the PLL circuit comprising: a charge pump and a current input module;
the charge pump is used for receiving a control signal, and the control signal is used for controlling the charging current and the discharging current of the charge pump;
one end of the current input module is connected with the voltage input end, and the other end of the current input module is connected with the output end of the charge pump;
the current input module is used for outputting target current;
the difference value of the first ratio corresponding to the discharging current and the second ratio corresponding to the charging current is equal to the target current; the first ratio is the ratio of the product of the absolute value of one current value which is at least not 0 in the discharge current and the maintaining time of one current value which is at least not 0 in the discharge current to the working period; the second ratio is the ratio of the product of the absolute value of one current value which is at least not 0 in the charging current and the maintenance time of one current value which is at least not 0 in the charging current to the working period;
wherein, the electric current input module includes: a triode, a first resistor, a second resistor, and first to third capacitors;
the first end of the first resistor is connected with the first end of the first capacitor, and the connecting node is connected with the base electrode of the triode;
the second end of the first resistor and the second end of the first capacitor are grounded respectively;
the first end of the second capacitor and the first end of the third capacitor are respectively connected with the first end of the second resistor, and the connecting node is connected with the emitter of the triode;
the second end of the second capacitor and the second end of the third capacitor are grounded respectively;
the second end of the second resistor is connected with the voltage input end;
and the collector electrode of the triode is connected with the output end of the charge pump.
2. The PLL circuit of claim 1, wherein a difference between the discharge current and the charge current is equal to the target current.
3. The PLL circuit of claim 1, wherein the current input module is a constant current source.
4. The PLL circuit of claim 1 wherein the current input module is a load resistor;
wherein, the first end of the load resistor is connected with the voltage input end;
and the second end of the load resistor is connected with the output end of the charge pump.
5. The PLL circuit of claim 1, wherein the PLL circuit further comprises: a loop filter;
the input end of the loop filter is connected with the output end of the charge pump;
the loop filter is used for generating a loop control voltage based on the sum value of the charging current, the discharging current and the target current.
6. The PLL circuit of claim 5, wherein the PLL circuit further comprises: a voltage controlled oscillator;
the input end of the voltage-controlled oscillator is connected with the output end of the loop filter;
the output end of the voltage-controlled oscillator is used as the output end of the PLL circuit;
the loop control voltage is used to control the frequency of the output signal of the voltage controlled oscillator.
7. The PLL circuit of claim 6, wherein the PLL circuit further comprises: a fractional divider;
the input end of the fractional frequency divider is connected with the output end of the voltage-controlled oscillator;
the fractional divider is used for receiving the output signal of the voltage-controlled oscillator and generating a feedback signal.
8. The PLL circuit of claim 7, wherein the PLL circuit further comprises: a phase frequency detector;
the first input end of the phase frequency detector is used for receiving a phase frequency detection signal;
the second input end of the phase frequency detector is connected with the output end of the fractional frequency divider and is used for receiving the feedback signal;
the output end of the phase frequency detector is connected with the control end of the charge pump;
the phase frequency detector is used for generating the control signal according to the phase frequency detection signal and the feedback signal.
9. An electronic device, characterized in that it comprises the PLL circuit of any of claims 1-8.
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