CN107104666B - Phase noise optimization device for phase-locked loop - Google Patents

Phase noise optimization device for phase-locked loop Download PDF

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CN107104666B
CN107104666B CN201710200248.6A CN201710200248A CN107104666B CN 107104666 B CN107104666 B CN 107104666B CN 201710200248 A CN201710200248 A CN 201710200248A CN 107104666 B CN107104666 B CN 107104666B
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controlled oscillator
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CN107104666A (en
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王冬春
刘渭
王祥炜
郑羽
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GUANGZHOU RUNXIN INFORMATION TECHNOLOGY CO LTD
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Abstract

The invention discloses an optimization device for phase noise of a phase-locked loop, which comprises a voltage bias circuit, a voltage-controlled oscillator, a frequency divider, a phase detection discriminator, a charge pump, a low-pass loop filter, a switch S1 and a switch S2, wherein the voltage-controlled oscillator, the frequency divider, the phase detection discriminator, the charge pump, the low-pass loop filter and the switch S1 form a closed loop; when the chip is powered on, the switch S2 is used for being closed under the control of the enable signal enb, so that the voltage bias circuit provides an initial input voltage signal to the voltage-controlled oscillator; the low-pass loop filter further comprises an offset current controller for providing an offset current signal to the low-pass loop filter for a period of time within a reference period, so that the low-pass loop filter provides the filtered signal Vtune to the voltage-controlled oscillator under the action of the offset current signal. The invention improves and realizes the optimization of the phase noise of the phase-locked loop on the prior phase-locked loop circuit, and has simple design and convenient use.

Description

Phase noise optimization device for phase-locked loop
Technical Field
The present invention relates to phase-locked loop circuits, and more particularly, to phase noise optimization in phase-locked loop circuits.
Background
The existing phase-locked loop is a typical feedback control circuit, the frequency and the phase of an internal oscillation signal of the loop are controlled by using an externally input reference signal, and the automatic tracking of the frequency of an output signal to the frequency of an input signal is realized, and the existing phase-locked loop is generally used for a closed-loop tracking circuit. But it is prone to phase noise at the output signal affecting the entire closed loop. A phase-locked loop circuit typically includes a voltage controlled oscillator, a frequency divider, a phase detector, a charge pump, and a low-pass loop filter. However, when the charge pump charges and discharges the low-pass loop filter to generate the output signal Vtune, noise generated by the MOS transistors in the charge pump and the phase detection discriminator may have a large influence on the output result. In order to reduce the phase noise, a constant offset current is added when the charge pump charges and discharges the low-pass loop filter, as shown in fig. 1, but the phase noise still exists.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide an optimization device of phase noise of a phase-locked loop, which solves the problem of high phase noise in a phase-locked loop circuit in the prior art.
The purpose of the invention is realized by adopting the following technical scheme:
a phase noise optimization device of a phase-locked loop comprises a voltage bias circuit, a voltage-controlled oscillator, a frequency divider, a phase detection discriminator, a charge pump, a low-pass loop filter, a switch S1 and a switch S2, wherein the voltage bias circuit is connected with the input end of the voltage-controlled oscillator through the switch S2, the output end of the voltage-controlled oscillator is connected with the input end of the phase detection discriminator through the frequency divider, the output end of the phase detection discriminator is connected with the input end of the low-pass loop filter through the charge pump, and the output end of the low-pass loop filter is connected with the input end of the voltage-controlled oscillator through the switch S1; the voltage-controlled oscillator, the frequency divider, the phase detection discriminator, the charge pump, the low-pass loop filter and the switch S1 form a closed loop; when the chip is powered on, the switch S2 is used for being closed under the control of the enable signal enb, so that the voltage bias circuit provides an initial input voltage signal to the voltage-controlled oscillator;
the voltage-controlled oscillator is used for generating an output signal A according to the initial input voltage signal and generating a feedback clock Fdiv from the output signal A through the frequency divider; the phase detection discriminator is used for controlling the charge pump to charge and discharge the low-pass loop filter according to the feedback clock Fdiv and an externally input reference clock Fref; the low-pass loop filter is used for providing a filtering signal Vtune to the voltage-controlled oscillator after the switch S1 is closed under the control of the enabling signal en;
the low-pass loop filter further comprises an offset current controller, wherein the offset current controller is used for providing an offset current signal to the low-pass loop filter for a period of time within a reference period, so that the low-pass loop filter provides the filtering signal Vtune to the voltage-controlled oscillator under the action of the offset current signal.
Preferably, the phase detection discriminator is further configured to generate an output signal UP and an output signal DN according to a reference clock Fref and a feedback clock Fdiv, where the output signal UP is used to control on or off of a charging current of the charge pump, and the output signal DN is used to control on or off of a discharging current of the charge pump; the output signal UP is also used for controlling the on or off of the current of the offset current controller in the charging mode, and the output signal DN is also used for controlling the on or off of the current of the offset current controller in the discharging mode.
Preferably, the enable signal en and the enable signal enb are a pair of inverted signals, the enable signal en is used for controlling the switch S1 to be turned on or off, and the enable signal enb is used for controlling the switch S2 to be turned on or off; when switch S1 is open, switch S2 is closed; when switch S1 is closed, switch S2 is open.
Preferably, the frequency divider is further used for generating another feedback signal B according to the output signal A generated by the voltage-controlled oscillator and sending the feedback signal B to the automatic frequency controller; the automatic frequency controller is used for enabling the voltage-controlled oscillator to select different switched capacitor arrays according to the reference clock Fref and the feedback signal B so as to adjust the frequency of the output signal A.
Preferably, the power supply further comprises a voltage comparison circuit and a relock control circuit, wherein the input end of the voltage comparison circuit is connected with the switch S1, and the output end of the voltage comparison circuit is connected with the input end of the relock control circuit; the output end of the relocking control circuit is connected with the input end of the voltage-controlled oscillator; the voltage comparison circuit is used for obtaining an output result according to the filtering signal Vtune; and the relocking control circuit controls the work of the voltage-controlled oscillator according to the output result, so that the frequency of the output signal A generated by the voltage-controlled oscillator is changed.
Preferably, the voltage comparison circuit is provided with a high voltage VH and a low voltage VL;
when the voltage comparison circuit detects that the voltage value of the filtering signal Vtune is between the high voltage VH and the low voltage VL, the output result is a two-bit signal control word "00";
when the voltage comparison circuit detects that the voltage value of the filtering signal Vtune is higher than the high voltage VH, the output result is a two-bit signal control word '01';
when the voltage comparison circuit detects that the voltage value of the filtered signal Vtune is lower than the low voltage VL, the output result is a two-bit signal control word "10".
Compared with the prior art, the invention has the beneficial effects that: the invention controls the input time of the constant offset current when the charge pump charges and discharges the low-pass loop filter by adopting the output signal of the phase discrimination discriminator, thereby reducing the phase noise in the phase-locked loop circuit and achieving the optimization of the phase noise of the phase-locked loop.
Drawings
FIG. 1 is a schematic diagram of a prior art PLL circuit according to the present invention;
FIG. 2 is a schematic diagram of a phase-locked loop circuit according to the present invention;
FIG. 3 is a schematic diagram of a charging current with constant offset current according to the prior art;
FIG. 4 is a schematic diagram of a discharge current with constant offset current according to the prior art;
FIG. 5 is a schematic diagram of a charging current of the offset current controller according to the present invention;
fig. 6 is a schematic diagram of a discharge current of the offset current controller according to the present invention.
In the figure: 202. a phase detection discriminator; 203. a charge pump; 204. a low-pass loop filter; 205. a frequency divider; 206. a voltage controlled oscillator; 207. an automatic frequency controller; 208. a relock control circuit; 209. a voltage comparison circuit; 210. a voltage bias circuit; 301. an offset current controller.
Detailed Description
The invention will be further described with reference to the accompanying drawings and the detailed description below:
as shown in fig. 2, the present invention provides an apparatus for optimizing phase noise of a pll, which is optimized and improved based on the existing pll circuit. The phase locked loop circuit includes a phase detection discriminator 202, a charge pump 203, a low pass loop filter 204, a switch S1, a switch S2, a voltage controlled oscillator 206, and a frequency divider 205. The switch S1, the voltage controlled oscillator 206, the frequency divider 205, the phase detection discriminator 202, the charge pump 203, and the low pass loop filter 204 form a phase locked loop closed circuit.
The switch S2 has one end electrically connected to the voltage bias circuit 210 and the other end electrically connected to the input end of the vco 206, wherein the voltage bias circuit 210 is used to provide an initial voltage for the pll circuit. When the chip is powered on, the switch S1 is in an open state, the switch S2 is in a closed state, and the voltage bias circuit 210 generates a bias voltage and transmits the bias voltage to the vco 206, so that the vco 206 operates. Where the bias voltage is half the voltage value of the power supply that powers the entire pll circuit, providing an initial voltage input to the input of the vco 206.
When the bias voltage is input to the vco 206, the vco 206 starts operating, the switch S2 is opened, and the switch S1 is closed, so that the pll circuit enters a closed loop. The switch S1 is controlled to be turned on or off by an enable signal en, and the switch S2 is controlled to be turned on or off by an enable signal enb; the enable signal en and the enable signal enb are a pair of inverted signals. That is, when switch S1 is open, switch S2 must be closed; when switch S1 is closed, switch S2 must be open.
After the chip is powered on, the vco 206 is configured to generate an output signal a, generate a feedback clock Fdiv under the action of the frequency divider 205, and send the feedback clock Fdiv to the phase detection discriminator 202; the phase detection discriminator 202 is used for controlling the working state of the charge pump 203 according to the phase difference between the feedback clock Fdiv and the externally input reference clock Fref. That is, when the phase detection discriminator 202 detects that the phase of the reference clock Fref leads Fdiv, the charge pump 203 is in a charging state, i.e., charges the low-pass loop filter 204, the low-pass loop filter 204 will generate a higher filtering signal Vtune, and input the higher filtering signal Vtune to the voltage-controlled oscillator 206 through the switch S1, so that the frequency of the output signal a of the voltage-controlled oscillator 206 is increased, the phase of the feedback clock Fdiv is advanced, and the phase difference between the feedback clock Fdiv and the reference clock Fref is reduced; on the contrary, when the phase detection discriminator 202 detects that the phase of the reference clock Fref lags behind Fdiv, and the charge pump 203 is in a discharging state, that is, the low-pass loop filter 204 is discharged, the low-pass loop filter 204 will generate a lower filtered signal Vtune, and the lower filtered signal Vtune is input to the voltage-controlled oscillator 206 through the switch S1, so that the frequency of the output signal a of the voltage-controlled oscillator 206 is reduced, the phase of the feedback clock Fdiv lags, and the phase difference between the feedback clock Fdiv and the reference clock Fref is reduced. That is, when the phase difference between the feedback clock Fdiv and the reference clock Fref is small and the filter signal Vtune tends to be stable, the phase-locked loop circuit enters the locked state. In addition, when the phase difference between the feedback clock Fdiv and the reference clock Fref is larger, the charging and discharging speed of the charge pump 203 is faster, so that the change speed of the filtering signal Vtune generated by the low-pass loop filter 204 is faster, and the filtering signal Vtune tends to be stable until the phase difference between the feedback clock Fdiv and the reference clock Fref is smaller, so that the phase-locked loop circuit is locked.
Generally, due to the existence of the phase detection discriminator 202 and the charge pump 203, the generated current may interfere with the phase-locked loop circuit, and the main sources of the noise are flicker noise, thermal noise, and the like generated by MOS transistors, resistors, and the like in the phase detection discriminator 202 and the charge pump 203. And MOS tube flicker noise
Figure BDA0001257903390000061
Comprises the following steps:
Figure BDA0001257903390000062
wherein g ismIs the small-signal transconductance of the MOS tube,
Figure BDA0001257903390000071
μnelectron or mass mobility of the MOS tube; coxIs the gate oxide dielectric constant of the MOS tube; w and L are respectively the gate width and the channel length of the MOS tube; i isDThe current is the channel current of the MOS tube; f is the frequency; k is a constant related to the process. And MOS tube thermal noise
Figure BDA0001257903390000072
Figure BDA0001257903390000073
k is the boltzmann physical constant and T is the thermodynamic temperature, and is known.
From the above equations (1) and (2), the flicker noise of MOS transistor can be seen
Figure BDA0001257903390000074
And IDIs in direct proportion; thermal noise of MOS transistor
Figure BDA0001257903390000075
And
Figure BDA0001257903390000076
is in direct proportion. That is, the noise generated by the charge pump 203 and the phase detection discriminator 202 is related to the magnitude of the MOS channel current; for example, flicker noise is mainly generated at a frequency offset of 1KHz, and thermal noise is mainly generated at a frequency offset of 100 KHz.
And for phase-locked loop open loop transfer function HOLIn a word: (ii) a Wherein HifFor passive loop transfer function, KvcoIndicating the gain of a voltage-controlled oscillator, IcpIs the charge pump charging current, s refers to the laplace function variable. Phase locked loop charge pump noise transfer function Ntf，cpComprises the following steps:
Figure BDA0001257903390000077
wherein N indicates the loop division ratio. At lower frequency offset, the open loop gain HOLFar greater than 1, then
Figure BDA0001257903390000078
That is, the pll charge pump noise is inversely proportional to the magnitude of the charge and discharge current of the charge pump.
For example, in actual operation, the current of the charge pump 203 is set to 100uA and 200uA respectively, and corresponding current output point noise is obtained, and the current near-end noise in the latter condition is deteriorated by 2dB to 5 dB. However, the larger the charge-discharge current of the charge pump 203 is, the improved contribution of the phase detection discriminator 202 and the charge pump 203 to the near-end phase noise of the phase-locked loop is about 3 dB. In fact, a smaller charge pump 203 current results in a smaller loop bandwidth, which suppresses more noise in the band; the phase detection discriminator 202 and the charge pump 203 contribute more to the near-end phase noise of the phase locked loop if they are under the same bandwidth condition.
At present, as shown in fig. 1, a scheme of improving noise by using a constant offset current is generally adopted, that is, when the charge pump 203 charges and discharges the low-pass loop filter 204, the charge pump 203 charges and discharges under the action of the constant offset current, but the charge and discharge current of the charge pump 203 is not reduced, which also increases noise.
Therefore, based on the principle, the invention enables the input offset current to be input only in a period of a certain reference period, not in the whole reference period. That is, the phase-locked loop circuit further includes an offset current controller 301, wherein one end of the offset current controller 301 is connected to the input end of the low-pass loop filter 204, and the other end of the offset current controller 301 is connected to a pulse signal for controlling the offset current controller 301 to be turned on or off. The pulse signal may be the UP output signal or the DN output signal of the phase detection discriminator 202. Meanwhile, the output signal UP is also used for controlling the charging current of the charge pump 203 to be turned on or off, and the output signal DN is also used for controlling the discharging current of the charge pump 203 to be turned on or off. Even if the phase locked loop is in a locked state, the phase detection discriminator 202 still has the output signal UP and the output signal DN, and the pulse width thereof is sufficient to open the switch. Therefore, the output signal UP is used in the present invention to control the on or off of the offset current controller 301 in the charging state; the output signal DN is used to control the on or off of the offset current controller 301 in the discharge state.
In use, when in the charging mode, the offset current controller 301 is controlled to be closed by the output signal UP within a preset time within a reference period, so that the charge pump 203 provides an offset current to the low-pass loop filter 204 when charging the low-pass loop filter 204; when the preset time is reached, the output signal UP controls the offset current controller 301 to turn off, and no offset current is supplied to the low-pass loop filter 204. Similarly, when in the discharging mode, the output signal DN may be used to control the offset current controller 301 to be turned on or off within a reference period, so as to input the offset current to the low-pass loop filter 204 within a predetermined time. Fig. 3 and 4 are schematic diagrams of charging and discharging currents with constant offset current added in the prior art, and fig. 5 and 6 are schematic diagrams of charging and discharging currents with offset current controller added after improvement. That is, in fig. 3 and 4, there is no switch to control the added constant offset current, that is, the constant offset current is continuously input during the charging and discharging process; in fig. 5 and 6, the input time of the offset current is controlled during the charging and discharging process by adding a switch such as S3 or S4 to the offset current controller 301.
In addition, in the invention, the average offset current in one reference period is set to be consistent with the constant offset current added before the improvement, so that the charging and discharging current of the charge pump 203 after the improvement is much larger than that before the improvement, and the phase noise of the phase-locked loop is less degraded. For example, the relationship between the offset current before and after improvement is: i isoffset·Tr＝I′offset·twIn which IoffsetFor constant offset current magnitude, l 'in the pre-scheme'offsetTo improve the magnitude of the offset current in the latter case, TrFor reference period size, twThe pulse width of the signal generated by the phase detection discriminator 202 in the scheme is improved. From the above equation, since twLess than TrTherefore, when the charge pump 203 charges and discharges, the offset current is significantly larger than before the improvement, i.e. the deterioration of the phase-locked loop noise is smaller.
In order to make the pll enter the locked state, the capacitance in the oscillating loop of the vco 206 is usually changed to change the oscillating frequency of the output signal a, so as to reduce the phase difference between the feedback clock Fdiv and the reference clock Fref. Generally, there are two types of capacitors connected to the oscillation loop of the vco 206, one is a MOS capacitor or a MIM capacitor, which is commonly used in a switched capacitor array, and a group of different capacitor arrays are connected to the oscillation loop by closing or opening a switch; the other is a varactor diode, which is controlled by different voltages to produce different capacitance values. The selective adjustment processes of the two types of capacitors are the 'coarse tuning' of the whole phase-locked loop and the 'fine tuning' of the whole phase-locked loop. To implement the tuning process, the phase locked loop circuit further comprises an automatic frequency controller 207, one end of the automatic frequency controller 207 being connected to the output of the frequency divider 205 and the other end being connected to the input of the voltage controlled oscillator 206. The output signal a of the vco 206 is further processed by the divider 205 to generate another feedback signal B and sent to the afc 207. The automatic frequency controller 207 is used for controlling switches connected into the oscillation loop according to the feedback signal B and the reference clock Fref, and further selecting a proper switch capacitor array in the oscillation loop of the voltage-controlled oscillator 206; then, after finding the proper switched capacitor array, the phase-locked loop circuit enters the self fine tuning. The loop of the pll circuit is closed, and a small change in the filtering signal Vtune changes the frequency of the output signal a of the vco 206, that is, the phases of the feedback clock Fdiv and the reference clock Fref are close to each other, so that the pll is finally locked.
In addition, after the chip is powered on, the phase-locked loop may lose lock due to temperature or other accidental factors during the operation process of the chip in the process that the phase-locked loop locks the phase-locked loop circuit through the coarse tuning and the fine tuning. Therefore, the phase-locked loop circuit also has a re-lock mechanism, i.e. these out-of-lock conditions need to be detected and corrected. Preferably, the phase-locked loop circuit further includes a voltage comparison circuit 209 and a relock control circuit 208. Wherein, the input end of the voltage comparison circuit 209 is connected with the switch S1, and the output end of the voltage comparison circuit 209 is connected with the input end of the relock control circuit 208; the output terminal of the relock control circuit 208 is connected to the input terminal of the vco 206; the voltage comparison circuit 209 is used for comparing the filtered signal with a preset signal and obtaining an output result; the relock control circuit 208 controls and adjusts the frequency of the output signal a of the vco 206 according to the output result.
That is, the voltage comparator 209 has a fixed low voltage VL and a fixed high voltage VH. When the voltage value of the filter signal Vtune is between the low voltage VL and the high voltage VH, the voltage comparison circuit 209 outputs a two-bit signal control word "00"; when Vtune > VH, the voltage comparison circuit 209 outputs a two-bit signal control word "01"; when Vtune < VL, the voltage comparison circuit 209 outputs a two-bit signal control word "10". The relock control circuit 208 increases or decreases a fixed capacitance value to the vco 206 according to the two-bit signal control word output by the voltage comparator 209 to adjust the frequency of the output signal a of the vco 206, so that the phase of the feedback clock Fdiv is close to that of the reference clock Fref, and the pll circuit is relocked.
Various other modifications and changes may be made by those skilled in the art based on the above-described technical solutions and concepts, and all such modifications and changes should fall within the scope of the claims of the present invention.

Claims (6)

1. The phase noise optimization device of the phase-locked loop comprises a voltage bias circuit, a voltage-controlled oscillator, a frequency divider, a phase detection discriminator, a charge pump, a low-pass loop filter, a switch S1 and a switch S2, wherein the voltage bias circuit is connected with the input end of the voltage-controlled oscillator through the switch S2, the output end of the voltage-controlled oscillator is connected with the input end of the phase detection discriminator through the frequency divider, the output end of the phase detection discriminator is connected with the input end of the low-pass loop filter through the charge pump, and the output end of the low-pass loop filter is connected with the input end of the voltage-controlled oscillator through the switch S1; the voltage-controlled oscillator, the frequency divider, the phase detection discriminator, the charge pump, the low-pass loop filter and the switch S1 form a closed loop; when the chip is powered on, the switch S2 is used for being closed under the control of the enable signal enb, so that the voltage bias circuit provides an initial input voltage signal to the voltage-controlled oscillator;
the voltage-controlled oscillator is used for generating an output signal A according to the initial input voltage signal and generating a feedback clock Fdiv from the output signal A through the frequency divider; the phase detection discriminator is used for controlling the charge pump to charge and discharge the low-pass loop filter according to the feedback clock Fdiv and an externally input reference clock Fref; the low-pass loop filter is used for providing a filtering signal Vtune to the voltage-controlled oscillator after the switch S1 is closed under the control of the enabling signal en;
the low-pass filter circuit further comprises an offset current controller, wherein the offset current controller is used for providing an offset current signal to the low-pass loop filter at a time in a reference period, so that the low-pass loop filter provides the filtering signal Vtune to the voltage-controlled oscillator under the action of the offset current signal.
2. The phase noise optimizer of phase locked loop according to claim 1 wherein the phase discriminator is further configured to generate an output signal UP and an output signal DN according to a reference clock Fref and a feedback clock Fdiv, the output signal UP is configured to control the charging current of the charge pump to be turned on or off, and the output signal DN is configured to control the discharging current of the charge pump to be turned on or off; the output signal UP is also used for controlling the on or off of the current of the offset current controller in the charging mode, and the output signal DN is also used for controlling the on or off of the current of the offset current controller in the discharging mode.
3. The apparatus for optimizing phase noise of a phase locked loop according to claim 1 or 2, wherein the enable signal en and the enable signal enb are a pair of inverted signals, the enable signal en is used for controlling the switch S1 to be turned on or off, and the enable signal enb is used for controlling the switch S2 to be turned on or off; when switch S1 is open, switch S2 is closed; when switch S1 is closed, switch S2 is open.
4. A device for phase noise optimization in a phase locked loop according to claim 1 or 2, further comprising an automatic frequency controller, wherein the frequency divider is further adapted to generate a further feedback signal B based on the output signal a generated by the voltage controlled oscillator and to send it to the automatic frequency controller; the automatic frequency controller is used for enabling the voltage-controlled oscillator to select different switched capacitor arrays according to the reference clock Fref and the feedback signal B so as to adjust the frequency of the output signal A.
5. The apparatus for optimizing phase noise of a phase locked loop according to claim 1 or 2, further comprising a voltage comparison circuit and a re-lock control circuit, wherein an input terminal of the voltage comparison circuit is connected to the switch S1, and an output terminal thereof is connected to an input terminal of the re-lock control circuit; the output end of the relocking control circuit is connected with the input end of the voltage-controlled oscillator; the voltage comparison circuit is used for obtaining an output result according to the filtering signal Vtune; and the relocking control circuit controls the work of the voltage-controlled oscillator according to the output result, so that the frequency of the output signal A generated by the voltage-controlled oscillator is changed.
6. The apparatus for optimizing phase noise of a phase locked loop of claim 5, wherein the voltage comparison circuit has a high voltage VH and a low voltage VL;
when the voltage comparison circuit detects that the voltage value of the filtering signal Vtune is between the high voltage VH and the low voltage VL, the output result is a two-bit signal control word "00";
when the voltage comparison circuit detects that the voltage value of the filtering signal Vtune is higher than the high voltage VH, the output result is a two-bit signal control word '01';
when the voltage comparison circuit detects that the voltage value of the filtered signal Vtune is lower than the low voltage VL, the output result is a two-bit signal control word "10".
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