TWI395410B - Method for adjusting oscillator in a phased-locked loop and related frequency synthesizer - Google Patents

Description

Method for adjusting the oscillator of a phase-locked loop and associated frequency synthesizer

The present invention relates to techniques for phase-locked loops, and more particularly to methods of adjusting an oscillator of a phase-locked loop and associated frequency synthesizers.

For many communication devices (such as mobile phones), the application of Multi-Mode/Multi-Band has become more and more important. In such applications, the mobile communication device typically uses a frequency synthesizer with a wide range of frequency adjustments to provide the desired clock signal.

Frequency synthesizers are typically implemented in a phase-locked loop (PLL) architecture. In order to meet the stringent requirements for phase noise in the mobile communication standard, the oscillator gain in the phase-locked loop of the frequency synthesizer should be kept at a low level. To achieve this goal, most of the oscillators in the frequency synthesizer are implemented using a switched ca-pacitor (VCO) to increase the frequency adjustment range of the frequency synthesizer.

It is well known that the locking speed of a phase-locked loop has a large effect on the overall performance of the frequency synthesizer. Therefore, how to effectively improve the locking speed of the phase-locked loop using the switched capacitor oscillator architecture is a problem to be solved.

In view of the above, it is an object of the present invention to provide a method of adjusting an oscillator of a phase locked loop and a related frequency synthesizer to solve the above problems.

The present specification provides an embodiment of a frequency synthesizer, comprising: a phase locked loop having an oscillator; a switching unit for switching the phase locked loop to an open loop state or a closed loop state; and a setting The device is configured to adjust the frequency of the oscillator according to a reference clock and an oscillation signal output by the oscillator when the phase locked loop is in an open loop state; wherein when the phase locked loop is in an open loop state, the The control signal of the oscillator is substantially fixed.

The present specification further provides an embodiment of a frequency synthesizer, comprising: a phase locked loop, comprising: an oscillator for generating an oscillation signal, and for dividing the oscillation signal to generate a first a first frequency dividing device of the frequency dividing signal; a switching unit for switching the phase locked loop to an open loop state or a closed loop state, wherein the oscillator control signal is when the phase locked loop is in an open loop state Is substantially fixed; a second frequency dividing unit is configured to divide a reference clock to generate a second frequency dividing signal; and a counter is used when the phase locked loop is in an open loop state, according to the first 1. The second frequency dividing signal is counted to generate a count value; a comparator is configured to compare the count value with a predetermined value to generate a comparison result; and a determining unit is configured to adjust according to the comparison result The frequency of this oscillator.

The present specification further provides a method for adjusting an oscillator in a phase locked loop, comprising: switching the phase locked loop to an open loop state, and maintaining a control signal of the oscillator; when the phase locked loop is open In the loop state, the frequency of the oscillator is adjusted according to a reference clock and an oscillation signal output by the oscillator; when the frequency of the oscillator reaches a preset target, the phase locked loop is switched to a closed loop state; And when the phase locked loop is in a closed loop state, the control signal of the oscillator is adjusted according to the reference clock and the oscillation signal.

Please refer to FIG. 1 , which is a simplified block diagram of the frequency synthesizer 100 according to the first embodiment of the present invention. The frequency synthesizer 100 includes a phase locked loop (PLL) 102, a setting device 104, and a switching unit 106. The phase-locked loop 102 of the present embodiment includes a detector 110 for detecting a frequency difference and/or a phase difference between the reference clock Sref and the frequency-divided signal Sf; and a charge pump 120 for detecting according to the detector 110 As a result, a control current is generated; a loop filter 130 for generating a control signal Vc according to the control current; an oscillator 140 for generating an oscillation signal Sosc according to the control signal Vc; and a frequency dividing device 150 The oscillating signal Sosc is divided to generate a divisor signal Sf. In practice, the detector 110 can be implemented by a phase frequency detector (PFD), the loop filter 130 can be various active filters or passive filters, and the oscillator 140 can be switched by capacitive switching. Implemented by a switched capacitor VCO.

In the frequency synthesizer 100, the setting device 104 is used to adjust the oscillation frequency of the oscillator 140, and the switching unit 106 is used to switch the phase locked loop 102 to an open loop status or a closed loop state (close Loop status). The tuning process of the oscillator 140 in the phase locked loop 102 can be divided into two modes, a coarse tuning mode and a fine tuning mode. In the coarse adjustment mode, the switching unit 106 switches the phase locked loop 102 to the open loop state, and in the fine tuning mode, the switching unit 106 switches the phase locked loop 102 to the closed loop state. Hereinafter, the adjustment method of the oscillator 140 will be further described with reference to FIG.

FIG. 2 is a flow chart 200 showing an embodiment of a method for adjusting the oscillator 140 of the phase locked loop 102 of the present invention. The steps included in the flowchart 200 are described as follows: In step 210, the switching unit 106 switches the phase locked loop 102 to an open loop state, and causes the input control signal of the oscillator 140 to remain fixed to enter the coarse adjustment mode. . As shown in FIG. 1 , the switching unit 106 is coupled between the loop filter 130 of the phase locked loop 102 and the oscillator 140 in this embodiment. When the switching unit 106 switches the control signal of the oscillator 140 to the substantially fixed reference voltage Vref, the phase locked loop 102 forms an open loop state. Please note that this is only an embodiment, and does not limit the actual setting of the switching unit 106.

For example, FIG. 3 illustrates another embodiment of the manner in which the switching unit 106 is disposed. As shown in FIG. 3, the loop filter 130 in this embodiment is an op amp-resistor-capacitor (OP-RC) filter (OP-RC filter), and the switching unit 106 is coupled to Between the input and output of the operational amplifier of loop filter 130. When the switching unit 106 is turned on and the charge pump 120 is disabled, the control signal Vc outputted by the loop filter 130 is equal to the substantially fixed reference voltage Vref, which is equivalent to the phase-locked loop. 102 becomes an open circuit state.

When the phase locked loop 102 is in the open loop state, the setting device 104 adjusts the frequency/band of the oscillator 140 according to the reference clock Sref and the oscillation signal Sosc generated by the oscillator 140 according to the reference voltage Vref (step 220).

As shown in FIG. 1, the setting device 104 of the present embodiment includes a comparison device 170 and a determination unit 180. The comparing means 170 is for comparing the oscillation signal Sosc with the reference clock Sref, and the determining unit 180 determines how to adjust the frequency of the oscillator 140 according to the comparison result of the comparing means 170. For example, the comparing device 170 compares the frequency of the oscillation signal Sosc and the reference clock Sref, and outputs a comparison result, and the determining unit 180 can adjust the frequency of the oscillator 140 according to the comparison result to reach the oscillator. 140 for the purpose of rough adjustment.

The block diagram of the first embodiment of the comparison device 170 is as shown in FIG. The comparing device 170 of this embodiment includes two frequency dividing devices 410 and 420, a counter 430, and a comparator 440. The frequency dividing device 410 is configured to divide the oscillating signal Sosc to generate a first frequency dividing signal FD1, and the frequency dividing device 420 divides the reference clock Sref to generate a second frequency dividing signal FD2. . The counter 430 counts according to the first frequency-divided signal FD1 and the second frequency-divided signal FD2, and the comparator 440 compares the count result of the counter 430 with a predetermined value, and outputs a comparison result.

Under normal circumstances, the target frequency of the oscillation signal Sosc should be the frequency of the reference clock Sref multiplied by the divisor value of the frequency dividing device 150 of the phase locked loop 102. For example, assuming that the frequency of the reference clock Sref is 100 MHz and the divisor value of the frequency dividing device 150 is 4, the target frequency of the oscillation signal Sosc should be 400 MHz. If the dividing value of the frequency dividing device 410 in the comparing device 170 is 5, and the dividing value of the frequency dividing device 420 is 10, the frequency of the second frequency dividing signal FD2 is 10 MHz, and the first frequency dividing signal FD1 is ideal. The frequency should be 80 MHz. Therefore, the counter 430 can count the rising edge (or falling edge) of the first frequency dividing signal FD1 in one cycle of the second frequency dividing signal FD2, and the comparator 440 can obtain the counting value obtained by the counter 430. A predetermined value of 8 (= 80/10) is compared to determine whether the oscillation frequency of the oscillator 140 is the desired value.

If the count value is greater than the predetermined value 8, the oscillation frequency of the oscillator 140 is too fast; if the count value is less than the predetermined value 8, the oscillation frequency of the oscillator 140 is too slow; and if the count value is equal to the predetermined value 8, it represents The current setting of the oscillator 140 conforms to the desired frequency adjustment range, i.e., the frequency band selected by the oscillator 140 at the time is appropriate. In practice, the divisor values of both the frequency dividing devices 410 and 420 are preferably integers, and the predetermined value is 2 ^N (where N is a positive integer) to reduce the complexity of subsequent circuits.

It can be seen from the foregoing description that the comparison device 170 of the setting device 104 can determine whether the setting of the oscillator 140 is appropriate by comparing the oscillation signal Sosc with the reference clock Sref, but this is only an embodiment, not a limitation. Practical embodiments of the invention. For example, FIG. 5 is a block diagram of a second embodiment of the comparison device 170. In this embodiment, the counter 430 counts according to the second frequency-divided signal FD2 and the frequency-divided signal Sf output by the frequency-dividing device 150 of the phase-locked loop 102, and the comparator 440 counts the counter 430 with a predetermined value. Compare and output the comparison result. Similarly, the counter 430 can count the rising edge (or falling edge) of the divisor signal Sf in one cycle of the second divisor signal FD2, and the comparator 440 only needs to divide the counter value obtained by the counter 430. The divisor value of the frequency device 420 is compared to determine whether the setting of the oscillator 140 is appropriate. In other words, the comparing means 170 of the setting means 104 can also determine whether the setting of the oscillator 140 is appropriate by comparing the divisor signal Sf with the reference clock Sref. In practice, the divisor values of both the frequency dividing devices 150 and 420 are preferably integers, and the predetermined value is preferably 2 ^N (where N is a positive integer) to reduce the complexity of subsequent circuits. In a preferred embodiment, the comparison device 170 and the phase locked loop 102 can share the same frequency dividing device 150 to reduce the area of the overall circuit. Next, the comparison means 170 transmits the comparison result to the decision unit 180, causing the decision unit 180 to adjust the set value of the oscillator 140 accordingly. Specifically, when the oscillator 140 is implemented by a switched capacitor oscillator, when the oscillation frequency of the switched capacitor oscillator is too fast, the determining unit 180 increases the total capacitance of the switched capacitor oscillator to reduce its Oscillation frequency. When the oscillation frequency of the switched capacitor oscillator is too slow, the decision unit 180 reduces the total capacitance of the switched capacitor oscillator to speed up its oscillation frequency. In practice, the determining unit 180 may adopt a linear search, a binary search, or a successive approximation algorithm in adjusting the varactor setting value of the switched capacitor oscillator.

It can be seen from the foregoing description that the setting device 104 can be designed to adjust the frequency of the oscillator 140 according to the reference clock Sref and the oscillation signal Sosc, and can also be designed to adjust the frequency of the oscillator 140 according to the reference clock Sref and the frequency-divided signal Sf.

In a preferred embodiment, when the oscillator 140 is implemented by a switched capacitor oscillator, the setting means 104 also selects in step 220 with reference to the varactor tuning characteris-tics of the switched capacitor oscillator. Switch the frequency band of the capacitive oscillator. Further, if the determining unit 180 of the setting device 104 cannot adjust the varactor setting value of the switched capacitor oscillator, the counter value of the counter 430 of the comparing device 170 and the predetermined value used by the comparator 440 are both When the equal state is reached, the determining unit 180 in this embodiment determines the appropriate frequency band for the switched capacitor oscillator according to the varactor adjustment characteristic of the switched capacitor oscillator.

Please refer to FIG. 6 , which is a schematic diagram 600 showing an embodiment of a varactor adjustment characteristic of a switched capacitor oscillator. In Fig. 6, 610, 620 and 630 represent three frequency bands selectable by the switched capacitor oscillator, and the reference voltage Vref corresponds to the midpoint of these bands. It is assumed that the currently selected frequency band of the switched capacitor oscillator is the frequency band 630. When the frequency synthesizer 100 enters the fine adjustment mode, the switched capacitive oscillator is adjusted from the frequency point 602 of the current frequency band 630 to the upper right to reach the position of the target frequency. . If the frequency band 620 is selected, the switched capacitive oscillator is adjusted from the frequency point 604 of the frequency band 620 to the lower left to reach the position of the target frequency. As shown in FIG. 6, the slope of the adjustment characteristic curve to the right of the frequency point 602 of the frequency band 630 is relatively flat, but the adjustment characteristic curve to the left of the frequency point 604 of the frequency band 620 is steep. Therefore, the decision unit 180 of the setting device 104 changes the frequency band of the switched capacitive oscillator to the frequency band 620 to shorten the lock time after the frequency synthesizer 100 enters the fine adjustment mode.

As shown in flowchart 200 of FIG. 2, setting device 104 repeats the operation of step 220 before oscillator 140 reaches the target frequency of the coarse adjustment mode.

When the oscillator 140 reaches the target frequency of the coarse adjustment mode (step 230), the switching unit 106 switches the phase locked loop 102 to the closed loop state (step 240) to enter the fine tuning mode. In the embodiment of FIG. 1, the switching unit 106 switches the input of the oscillator 140 to the control signal Vc output by the loop filter 130 to cause the phase locked loop 102 to form a closed loop state. In the embodiment of Fig. 3, the switching unit 106 is turned off to cause the phase locked loop 102 to become a general closed loop state.

When the phase locked loop 102 is in the closed loop state, the phase locked loop 102 adjusts the control signal Vc of the oscillator 140 according to the reference clock Sref and the oscillation signal Sosc (step 250), so that the frequency of the oscillation signal Sosc can be achieved. Target frequency. Since the locking operation of the phase locked loop 102 in the closed loop state is a conventional technique, for the sake of brevity, no further details are provided herein.

The method of adjusting the oscillator is also applicable to the architecture of various fractional-N frequency synthesizers.

Please refer to FIG. 7, which is a simplified block diagram of a frequency synthesizer 700 according to a second embodiment of the present invention. The frequency synthesizer 700 includes a phase locked loop 702, a setting device 704, and a switching unit 706. The phase-locked loop 702 of this embodiment includes a detector 710 for detecting a frequency difference and/or a phase difference between the reference clock Sref and the frequency-divided signal Sf. The charge pump 720 is configured to generate a control current according to the detection result of the detector 710. a loop filter 730 for generating a control signal Vc according to the control current; an oscillator 740 for generating an oscillation signal Sosc according to the control signal Vc; and a frequency dividing device 750 for dividing the oscillation signal Sosc to generate a frequency The frequency signal Sf; and the divisor setting means 760 are used to intermittently adjust the divisor value of the frequency dividing means 750, so that the frequency dividing means 750 performs a non-integer frequency dividing operation on the oscillation signal Sosc.

As with the previous embodiments, the operation and implementation of the setting device 704 are substantially the same as the previously described setting device 104. That is, the setting device 704 can be designed to adjust the frequency of the oscillator 740 according to the reference clock Sref and the oscillation signal Sosc, and can also be designed to adjust the frequency of the oscillator 740 according to the reference clock Sref and the frequency-divided signal Sf. However, it should be noted that if the setting device 704 adjusts the frequency/band of the oscillator 740 according to the frequency-divided signal Sf and the reference clock Sref in the coarse adjustment mode (ie, the phase-locked loop 702 is in the open loop state), then the lock is used. When the phase loop 702 is in the open loop state, the divisor setting means 760 should set the divisor value of the frequency dividing means 750 to a fixed integer value. The operation and implementation of other components of the phase-locked loop 702 are substantially the same as those of the previous embodiments, and therefore will not be described again.

Similarly, the switching unit 706 can be coupled between the loop filter 730 and the oscillator 740. If the loop filter 730 is a filter having an operational amplifier-resistor-capacitor (OP-RC) architecture, the switching unit 706 can also be coupled between the input and output of the operational amplifier of the loop filter 730.

Since the frequency synthesizer disclosed above roughly sets and adjusts an oscillator (such as a switched capacitor oscillator) in an open loop manner, and then fine-tunes its control signal in a closed loop manner, the oscillator can be effectively adjusted. School speed, which in turn improves the overall performance of the frequency synthesizer.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 700. . . Frequency synthesizer

102, 702. . . Phase-locked loop

104, 704. . . Setting device

106, 706. . . Switching unit

110, 710. . . Detector

120, 720. . . Charge pump

130, 730. . . Loop filter

140, 740. . . Oscillator

150, 750, 410, 420. . . Frequency dividing device

170. . . Comparison device

180. . . Decision unit

430. . . counter

440. . . Comparators

600. . . Variable container characteristics

602, 604. . . Frequency point

610, 620, 630. . . Frequency band

760. . . Divisor setting device

Figure 1 is a simplified block diagram of a first embodiment of a frequency synthesizer of the present invention.

2 is a flow chart of an embodiment of a method for adjusting an oscillator of a phase locked loop according to the present invention.

Fig. 3 is another embodiment of the arrangement of the switching unit in Fig. 1.

Figure 4 is a block diagram of a first embodiment of the comparing device of Figure 1.

Figure 5 is a block diagram of a second embodiment of the comparing device of Figure 1.

FIG. 6 is a schematic diagram showing the characteristics of a variable capacitor of a switched capacitor oscillator according to an embodiment of the present invention.

Figure 7 is a simplified block diagram of a second embodiment of the frequency synthesizer of the present invention.

100. . . Frequency synthesizer

102. . . Phase-locked loop

104. . . Setting device

106. . . Switching unit

110. . . Detector

120. . . Charge pump

130. . . Loop filter

140. . . Oscillator

150. . . Frequency dividing device

170. . . Comparison device

180. . . Decision unit

Claims (18)

A frequency synthesizer comprising: a phase locked loop having an oscillator; a switching unit for switching the phase locked loop to an open loop state or a closed loop state; and a setting device for the lock When the phase loop is in an open loop state, the oscillation frequency of the oscillator is adjusted according to a reference clock and an oscillation signal output by the oscillator, and the setting device comprises: a comparing device for the oscillation signal and the reference The clock is compared to generate a comparison result. The comparing device includes: a first frequency dividing device for dividing the oscillation signal to generate a first frequency dividing signal; and a second frequency dividing device for Decoupling the reference clock to generate a second frequency dividing signal; a counter for counting according to the first and second frequency dividing signals to generate a count value; and a comparator for using comparing the count value with a predetermined value to generate the comparison result, wherein the predetermined value is 2 ^N, and N is a positive integer; and a decision unit, according to the comparison result of the comparing means, adjusting the Frequency of the oscillator; wherein, when the PLL circuit is in the on state, the control signal of the oscillator system is substantially constant and equal to the other input to one input terminal of the operational amplifier reference voltage. The frequency synthesizer according to claim 1, wherein the setting device is configured to set a setting value of an internal component of the oscillator according to the reference clock and the oscillation signal when the phase locked loop is in an open circuit state, To adjust the oscillation frequency of the oscillator. The frequency synthesizer of claim 1, wherein the oscillator is a switched capacitor oscillator. The frequency synthesizer of claim 3, wherein the setting device sets the frequency band of the switched capacitor oscillator according to a varactor characteristic of the switched capacitor oscillator. The frequency synthesizer of claim 1, wherein the phase locked loop adjusts the control signal of the oscillator according to the reference clock and the oscillation signal when the phase locked loop is in a closed loop state. The frequency synthesizer of claim 1, wherein the divisor of the first frequency dividing device is an integer value when the phase locked loop is in an open loop state. The frequency synthesizer of claim 1, wherein the switching unit switches the phase locked loop to a closed loop state after the determining unit adjusts the frequency of the oscillator. A frequency synthesizer includes: a phase locked loop, comprising: an oscillator for generating an oscillation signal; and a first frequency dividing device for dividing the oscillation signal to generate a a first frequency dividing signal; a switching unit for switching the phase locked loop to an open loop state or a closed loop state, wherein when the phase locked loop is in an open loop state, the control signal of the oscillator is substantially fixed; a second frequency dividing device for dividing a reference clock to generate a second frequency dividing signal; a counter for the phase locked loop being in an open loop state, according to the first and second dividing The frequency signal is counted to generate a count value; a comparator is configured to compare the count value with a predetermined value to generate a comparison result, wherein the predetermined value is 2 ^N and N is a positive integer; and a decision unit , used to adjust the frequency of the oscillator according to the comparison result. The frequency synthesizer of claim 8, wherein the phase-locked loop further comprises a loop filter, and the switching unit is coupled between the loop filter and the oscillator. The frequency synthesizer of claim 8, wherein the phase-locked loop further comprises a loop filter having an operational amplifier-resistor-capacitor (OP-RC) architecture filter (OP-RC filter) The switching unit is coupled between an input terminal and an output terminal of the operational amplifier. The frequency synthesizer of claim 8, wherein the oscillator is a switched-capacitor VCO. The frequency synthesizer of claim 11, wherein the determining unit sets the frequency band of the switched capacitor voltage controlled oscillator according to a varactor characteristic of the switched capacitor voltage controlled oscillator. The frequency synthesizer of claim 8, wherein the phase-locked loop is in a closed loop state, and the oscillation is determined according to a frequency difference or a phase difference between the reference clock and the first frequency-divided signal. Device Control signal. The frequency synthesizer of claim 8, wherein the divisor of the first frequency dividing device is an integer value when the phase locked loop is in an open loop state. The frequency synthesizer of claim 8, wherein the switching unit switches the phase locked loop to a closed loop state after the determining unit adjusts the frequency of the oscillator. A method for adjusting an oscillator in a phase-locked loop, the phase-locked loop comprising a loop filter, the method comprising: switching the phase-locked loop to an open loop state, and maintaining the control signal of the oscillator Fixed and equal to a reference voltage input to one of the operational amplifiers of the loop filter; when the phase locked loop is in an open loop state: one of the oscillator signals output by the oscillator is divided to generate a first frequency division signal; performing frequency division on a reference clock to generate a second frequency division signal; counting according to the first and second frequency division signals to generate a count value; comparing the count value with a Predetermining a value to generate a comparison result, wherein the predetermined value is 2 ^N and N is a positive integer; and adjusting the frequency of the oscillator according to the comparison result; when the frequency of the oscillator reaches a preset target, The phase locked loop is switched to a closed loop state; and when the phase locked loop is in a closed loop state, the control signal of the oscillator is adjusted according to the reference clock and the oscillation signal. The method of claim 16, wherein the frequency division of the oscillating signal is an integer division. The method of claim 16, wherein the step of adjusting the frequency of the oscillator comprises: setting a frequency band of the oscillator according to a varactor characteristic of the oscillator.