CN111106827B - Method, system and storage medium for detecting power supply fluctuation in digital chip - Google Patents
Method, system and storage medium for detecting power supply fluctuation in digital chip Download PDFInfo
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- CN111106827B CN111106827B CN201911251912.5A CN201911251912A CN111106827B CN 111106827 B CN111106827 B CN 111106827B CN 201911251912 A CN201911251912 A CN 201911251912A CN 111106827 B CN111106827 B CN 111106827B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
Abstract
The invention discloses a method, a system and a storage medium for detecting power supply fluctuation in a digital chip, wherein the method comprises the following steps: collecting control voltage of a phase-locked loop circuit in a digital chip; acquiring the fluctuation amplitude of the power supply voltage according to the control voltage; the control voltage is the output voltage of a phase discriminator/phase discriminator, a charge pump or a loop filter in the phase-locked loop circuit. The invention represents the amplitude of power supply voltage fluctuation through the control voltage in the phase-locked loop circuit, avoids the influence of parasitic inductance, can accurately obtain the amplitude value of the power supply fluctuation, and can be widely applied to the field of chip detection.
Description
Technical Field
The invention relates to the field of chip detection, in particular to a method and a system for detecting power supply fluctuation in a digital chip and a storage medium.
Background
In a chip test scene, an engineer hopes to know the accurate amplitude of the on-chip power supply voltage fluctuation in a complex electromagnetic environment, so as to analyze the radiation-resistant rule of a circuit; or when a chip immunity test is carried out, after interference is artificially applied to the pins, the accurate disturbed amplitude of the on-chip power supply is obtained.
As shown in fig. 2, the conventional chip power supply voltage fluctuation detection means is: and applying an oscilloscope probe to a power supply pin VDD of the chip, detecting the voltage level, and obtaining the fluctuation range of the power supply voltage by utilizing the data processing function of the oscilloscope. Such testing theory inherently equates the power supply voltage at the IC package pins to the power supply voltage within the IC die, and is not rigorous, as detailed below.
The existing testing means equates the supply voltage at the IC package pins to the IC core voltage, which is acceptable in dc or low frequency scenarios. However, when the power supply voltage is subjected to high-frequency interference, the voltage values of the two are greatly different. The reason is that the copper bonding wires between the die power pads and the package pins have parasitic inductance: at low frequency, the impedance of the parasitic inductor is very small, and the voltages at the bare chip power pad and the packaging power pin can be similar; when the internal power supply is interfered by radio frequency, the impedance of the parasitic inductor is very large, a very large voltage drop exists on the parasitic inductor, and the two voltages are obviously different. From the perspective of filtering, the parasitic inductance of the bonding wire is equivalent to an isolator, and can isolate high-frequency interference. Therefore, the accurate value of the power supply voltage at the die power pad cannot be obtained by the existing test means through the bonding wire, and the interference amplitude of the accurate value cannot be known. In other words, all means of measuring the voltage level of the power supply from the package power supply pins are inaccurate and imprecise.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a method, a system and a storage medium for detecting power supply fluctuation in a digital chip based on a phase-locked loop circuit.
The first technical scheme adopted by the invention is as follows:
a method for detecting power supply fluctuation in a digital chip comprises the following steps:
collecting control voltage of a phase-locked loop circuit in a digital chip;
acquiring the fluctuation amplitude of the power supply voltage according to the control voltage;
the control voltage is the output voltage of a phase discriminator/phase discriminator, a charge pump or a loop filter in the phase-locked loop circuit.
Further, the step of obtaining the amplitude of the power supply voltage fluctuation according to the control voltage specifically includes the following steps:
performing analog-to-digital conversion on the control voltage to obtain a first voltage digital value;
combining the first voltage digital value with a preset lookup table to obtain a second voltage digital value;
and D/A conversion is carried out on the second voltage digital value to obtain the fluctuation amplitude of the power supply voltage.
The second technical scheme adopted by the invention is as follows:
a detection system for power supply fluctuation in a digital chip comprises a detection module and a phase-locked loop circuit in the digital chip;
the detection module is used for acquiring the control voltage of the phase-locked loop circuit and acquiring the fluctuation amplitude of the power supply voltage according to the control voltage;
the control voltage is the output voltage of a phase discriminator/phase discriminator, a charge pump or a loop filter in the phase-locked loop circuit.
Further, the detection module comprises an analog-to-digital conversion unit, a lookup table unit and a digital-to-analog conversion unit, and the phase-locked loop circuit, the analog-to-digital conversion unit, the lookup table unit and the digital-to-analog conversion unit are sequentially connected.
Furthermore, the detection module further comprises a storage unit, and the analog-to-digital conversion unit is connected with the lookup table unit through the storage unit.
Further, the detection module further comprises an oscilloscope or a display screen.
Furthermore, the detection module is arranged in the digital chip, and the output end of the digital-to-analog conversion unit is connected with the I/O output module of the digital chip.
Furthermore, the detection module is arranged outside the digital chip, and the output ends of the phase discriminator/phase discriminator, the charge pump or the loop filter are connected with the I/O output module of the digital chip.
The third technical scheme adopted by the invention is as follows:
a system for detecting power fluctuations within a digital chip, comprising:
at least one processor;
at least one memory for storing at least one program;
when executed by the at least one processor, cause the at least one processor to implement the method described above.
The fourth technical scheme adopted by the invention is as follows:
a storage medium having stored therein processor-executable instructions for performing the method as described above when executed by a processor.
The invention has the beneficial effects that: the invention represents the amplitude of power supply voltage fluctuation through the control voltage in the phase-locked loop circuit, avoids the influence of parasitic inductance and can accurately obtain the amplitude value of power supply fluctuation.
Drawings
FIG. 1 is a flow chart of steps of a method for detecting power supply fluctuations on a digital chip, in accordance with an embodiment;
FIG. 2 is a schematic diagram of a prior art chip power supply voltage test;
FIG. 3 is a block diagram of a phase-locked loop circuit;
FIG. 4 is a schematic diagram of the relationship between the control voltage of the voltage controlled oscillator and the amplitude of the ripple;
FIG. 5 is a schematic diagram of a first implementation of a system for detecting power supply fluctuations on a digital chip, in accordance with an embodiment;
FIG. 6 is a diagram of a second implementation of a system for detection of power supply fluctuations on a digital chip, in accordance with an embodiment;
fig. 7 is a schematic diagram of a third implementation of a system for detecting power supply fluctuation on a digital chip in an embodiment.
Detailed Description
As shown in fig. 1, the present embodiment provides a method for detecting power supply fluctuation in a digital chip, including the following steps:
s1, collecting the control voltage of the phase-locked loop circuit in the digital chip;
s2, acquiring the fluctuation amplitude of the power supply voltage according to the control voltage;
the control voltage is the output voltage of a phase discriminator/phase discriminator, a charge pump or a loop filter in the phase-locked loop circuit.
The phase-locked loop circuit structure is shown in fig. 3, the phase frequency/phase discriminator compares the phases of the input and output signals after frequency division by M, N, generates a signal with a pulse width linearly related to the phase difference, outputs a smooth voltage control signal Vcont through the loop filter (the magnitude of Vcont is positively related to the pulse width), and changes the output frequency fout of the voltage control signal Vcont to reduce the input phase difference of the phase frequency/phase discriminator, so that the repeated negative feedback finally achieves the effect that fin/M is fout/N. For the voltage-controlled oscillator, the input control voltage Vcont and the output signal frequency fout have the following linear relationship: fout is fout0+ Kvco Vcont.
Case of disturbed supply voltage to the voltage controlled oscillator: taking a ring oscillator as an example, the power supply voltage is disturbed by a sine wave, and its output frequency fout decreases as the disturbance amplitude Arf increases. Thus, the output of the loop filter in the phase locked loop circuit is used to characterize the supply voltage fluctuation amplitude. Similarly, the output pulse of the phase detector/phase discriminator can be used to represent the amplitude Arf of the power supply voltage fluctuation instead of the control voltage Vcont. Or the current pulses of the charge pump are substituted for the control voltage Vcont to characterize the amplitude Arf of the supply voltage fluctuations.
In summary, there is a quantitative correspondence relationship between the output signal frequency fout, the input control voltage Vcont, and the interference amplitude Arf, and the amplitude variation of the power supply voltage due to interference can be tracked by Vcont, and the specific relationship is shown in fig. 4. When the phase-locked loop reaches a steady state, the output frequency is
When the voltage-controlled oscillator is interfered by the power supply, the power supply voltage is VDD＝VO+Arfsin(2πfrft) Causing the output frequency to shift. After the phase difference is detected by the phase discriminator/phase discriminator, the pulse is output to the filter to generate a new control voltage Vcont, and the new control voltage Vcont is used for correcting foutMaintaining the output frequency of
For a digital chip, the phase-locked loop circuit is an essential part as a clock source, when the chip is disturbed, the fluctuation amplitude of the power supply voltage can be always represented by the VCO control voltage Vcont in the phase-locked loop, for example, a lookup table of one-to-one correspondence between Vcont and Arf is established. When the chip is designed, the Vcont is set as a path of output, namely the power supply voltage fluctuation Arf can be monitored, and because the Vcont is a relatively slow signal, namely the signal belongs to a low-frequency signal, the difference between the values on the bare chip pad and the package pins does not need to be considered.
In the method, the fluctuation range of the power supply voltage is represented by the output of the loop filter, so that the influence of parasitic inductance can be avoided, and the fluctuation range of the power supply can be accurately obtained. Specifically, the actual result is obtained by simulating Hspice and manufacturing a PCB, so that the method is feasible and the fluctuation amplitude of the power supply voltage can be accurately obtained.
Further, as a preferred embodiment, the step S2 specifically includes steps S21 to S23:
s21, performing analog-to-digital conversion on the control voltage to obtain a first voltage digital value;
s22, combining the first voltage digital value and a preset lookup table to obtain a second voltage digital value;
and S23, performing digital-to-analog conversion on the second voltage digital value to obtain the fluctuation amplitude of the power supply voltage.
In the method of the embodiment, the collected control voltage is processed in an automatic mode, and the voltage value of the final power supply voltage fluctuation is output, manual table lookup according to the control voltage is not needed, the manual efficiency is greatly improved,
as shown in fig. 5, the present embodiment further provides a system for detecting power supply fluctuation in a digital chip, including a detection module and a phase-locked loop circuit in the digital chip;
the detection module is used for acquiring the control voltage of the phase-locked loop circuit and acquiring the fluctuation amplitude of the power supply voltage according to the control voltage;
the control voltage is the output voltage of a phase discriminator/phase discriminator, a charge pump or a loop filter in the phase-locked loop circuit;
the detection module is arranged outside the digital chip, and the output ends of the phase discrimination/phase discriminator, the charge pump or the loop filter are connected with the I/O output module of the digital chip.
In the system of the embodiment, when a chip is designed, a clock is generated by a phase-locked loop circuit, the phase-locked loop can be divided into modules such as a phase discrimination/frequency discriminator, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider, an intermediate quantity, namely a control voltage Vcont of the loop filter to the voltage-controlled oscillator is selected, the Vcont is set to be a path of chip I/O output, the path of output has a quantitative relation with the fluctuation amplitude of a power supply voltage, and the fluctuation amplitude can be effectively represented. The control voltage Vcont can be acquired at the I/O output end through the oscilloscope, and then the fluctuation amplitude of the power supply voltage is obtained through a manual lookup table or other lookup table modes.
As shown in fig. 6, the present embodiment further provides a system for detecting power supply fluctuation in a digital chip, including a detection module and a phase-locked loop circuit in the digital chip;
the detection module is used for acquiring the control voltage of the phase-locked loop circuit and acquiring the fluctuation amplitude of the power supply voltage according to the control voltage;
the control voltage is the output voltage of a phase discriminator/phase discriminator, a charge pump or a loop filter in the phase-locked loop circuit;
the detection module comprises an analog-to-digital conversion unit, a lookup table unit and a digital-to-analog conversion unit, and the phase-locked loop circuit, the analog-to-digital conversion unit, the lookup table unit and the digital-to-analog conversion unit are sequentially connected;
the detection module is arranged in the digital chip, and the output end of the digital-to-analog conversion unit is connected with the I/O output module of the digital chip.
The detection module is directly arranged in a chip to convert analog quantity Vcont into digital quantity through analog-to-digital conversion, then digital quantity representation of Arf is obtained according to a look-up table (LUT) related to Vcont and Arf, then the digital quantity of Arf is subjected to digital-to-analog conversion to obtain Arf analog quantity, the Arf analog quantity is directly output outside the chip, and finally the Arf analog quantity can be obtained through detection of an oscilloscope or displayed through a display screen. Therefore, the fluctuation range of the power supply voltage can be directly read without manually searching a table.
Further as a preferred embodiment, the detection module further includes a storage unit, and the analog-to-digital conversion unit is connected to the lookup table unit through the storage unit. In this way, voltage values at a plurality of points in time can be recorded.
As shown in fig. 7, the present embodiment further provides a system for detecting power supply fluctuation in a digital chip, including a detection module and a phase-locked loop circuit in the digital chip;
the detection module is used for acquiring the control voltage of the phase-locked loop circuit and acquiring the fluctuation amplitude of the power supply voltage according to the control voltage;
the control voltage is the output voltage of a phase discriminator/phase discriminator, a charge pump or a loop filter in the phase-locked loop circuit;
the detection module comprises an analog-to-digital conversion unit, a lookup table unit and a digital-to-analog conversion unit, and the phase-locked loop circuit, the analog-to-digital conversion unit, the lookup table unit and the digital-to-analog conversion unit are sequentially connected;
the detection module is arranged outside the digital chip, and the output ends of the phase discrimination/phase discriminator, the charge pump or the loop filter are connected with the I/O output module of the digital chip.
The detection module is arranged outside the chip, so that the area of the chip is reduced, and the cost of the chip is reduced.
This embodiment also provides a detection system of power supply fluctuation in the digital chip, including:
at least one processor;
at least one memory for storing at least one program;
when executed by the at least one processor, cause the at least one processor to implement the method described above.
The system for detecting power supply fluctuation in the digital chip can execute the method for detecting power supply fluctuation in the digital chip provided by the method embodiment of the invention, can execute any combination of the method embodiments, and has corresponding functions and beneficial effects of the method.
The present embodiments also provide a storage medium having stored therein processor-executable instructions, which when executed by a processor, are configured to perform the method as described above.
The storage medium of this embodiment can execute the method for detecting power supply fluctuation in the digital chip provided by the method embodiment of the present invention, can execute any combination of the implementation steps of the method embodiment, and has the corresponding functions and advantages of the method.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for detecting power supply fluctuation in a digital chip is characterized by comprising the following steps:
collecting control voltage of a phase-locked loop circuit in a digital chip;
acquiring the fluctuation amplitude of the power supply voltage according to the control voltage;
the control voltage is the output voltage of a phase discriminator/phase discriminator, a charge pump or a loop filter in the phase-locked loop circuit;
the control voltage and the amplitude of the power supply voltage fluctuation have a corresponding relation, the control voltage is adopted to represent the amplitude of the power supply voltage fluctuation, and the control voltage is a low-frequency signal.
2. The method for detecting power supply fluctuation in a digital chip according to claim 1, wherein the step of obtaining the amplitude of the power supply voltage fluctuation according to the control voltage specifically comprises the steps of:
performing analog-to-digital conversion on the control voltage to obtain a first voltage digital value;
combining the first voltage digital value with a preset lookup table to obtain a second voltage digital value;
and D/A conversion is carried out on the second voltage digital value to obtain the fluctuation amplitude of the power supply voltage.
3. A detection system for power supply fluctuation in a digital chip is characterized by comprising a detection module and a phase-locked loop circuit in the digital chip;
the detection module is used for acquiring the control voltage of the phase-locked loop circuit and acquiring the fluctuation amplitude of the power supply voltage according to the control voltage;
the control voltage is the output voltage of a phase discriminator/phase discriminator, a charge pump or a loop filter in the phase-locked loop circuit;
the control voltage and the fluctuation amplitude of the power supply voltage have a corresponding relation, the control voltage is adopted to represent the fluctuation amplitude of the power supply voltage, and the control voltage is a low-frequency signal.
4. The system of claim 3, wherein the detection module comprises an analog-to-digital conversion unit, a lookup table unit and a digital-to-analog conversion unit, and the phase-locked loop circuit, the analog-to-digital conversion unit, the lookup table unit and the digital-to-analog conversion unit are connected in sequence.
5. The system for detecting power supply fluctuation on a digital chip as claimed in claim 4, wherein the detection module further comprises a storage unit, and the analog-to-digital conversion unit is connected with the lookup table unit through the storage unit.
6. The system for detecting power supply fluctuation in a digital chip according to claim 4, wherein the detection module further comprises an oscilloscope or a display screen.
7. The system for detecting power supply fluctuation in a digital chip as claimed in claim 4, wherein the detection module is disposed in the digital chip, and the output terminal of the digital-to-analog conversion unit is connected to the I/O output module of the digital chip.
8. The system for detecting power supply fluctuation in a digital chip according to claim 3 or 4, wherein the detection module is disposed outside the digital chip, and the output terminal of the phase detector/phase discriminator, the charge pump or the loop filter is connected to the I/O output module of the digital chip.
9. A system for detecting power fluctuations on a digital chip, comprising:
at least one processor;
at least one memory for storing at least one program;
when executed by the at least one processor, cause the at least one processor to implement a method of detecting power supply fluctuations within a digital chip as claimed in any one of claims 1 to 2.
10. A storage medium having stored therein processor-executable instructions, which when executed by a processor, are configured to perform the method of any one of claims 1-2.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003023087A (en) * | 2001-07-09 | 2003-01-24 | Fujitsu Ltd | Semiconductor integrated circuit |
| CN1859006A (en) * | 2005-10-21 | 2006-11-08 | 华为技术有限公司 | System and method for realizing holding fuction by analogue phase locking loop |
| CN101383614A (en) * | 2007-09-04 | 2009-03-11 | 锐迪科微电子（上海）有限公司 | PLL filter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009081557A (en) * | 2007-09-25 | 2009-04-16 | Fujitsu Microelectronics Ltd | Phase-locked loop circuit |
| JP2015130035A (en) * | 2014-01-07 | 2015-07-16 | 富士通株式会社 | Semiconductor device and control method |
| CN204993302U (en) * | 2015-10-07 | 2016-01-20 | 杭州锐达数字技术有限公司 | Digital low frequency phase -locked loop |
| CN107104666B (en) * | 2017-03-29 | 2020-10-27 | 广州润芯信息技术有限公司 | Phase noise optimization device for phase-locked loop |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003023087A (en) * | 2001-07-09 | 2003-01-24 | Fujitsu Ltd | Semiconductor integrated circuit |
| CN1859006A (en) * | 2005-10-21 | 2006-11-08 | 华为技术有限公司 | System and method for realizing holding fuction by analogue phase locking loop |
| CN101383614A (en) * | 2007-09-04 | 2009-03-11 | 锐迪科微电子（上海）有限公司 | PLL filter |
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