CN211453930U - Parameter detection circuit - Google Patents
Parameter detection circuit Download PDFInfo
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- CN211453930U CN211453930U CN201922121522.8U CN201922121522U CN211453930U CN 211453930 U CN211453930 U CN 211453930U CN 201922121522 U CN201922121522 U CN 201922121522U CN 211453930 U CN211453930 U CN 211453930U
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Abstract
A parameter detection circuit is provided with two different reference voltage signals by different circuits, and the detection of another original reference voltage source is realized through one reference voltage signal so as to determine whether the other original reference voltage source has a fault or not, so that the detection precision of the parameter detection circuit is improved.
Description
Technical Field
The application belongs to the technical field of electronic circuits, and particularly relates to a parameter detection circuit.
Background
At present, in the field of electric energy metering, a sampling network is generally used to sample a voltage signal and a current signal to be measured, then the sampled signals are input into an analog-to-digital converter to be converted into digital signals, and finally a signal processor is used to process the digital signals to obtain measured values. However, when parameters of components in the sampling network change due to a fault, sampling errors occur, and finally measurement errors occur. For this situation, the measurement system needs to be able to detect it and process it accordingly.
Usually, a detection signal generating circuit is used to detect the sampling network, so as to determine whether the parameters of the sampling network change, and further locate the fault source. Specifically, an additional detection signal generated based on a reference voltage source is introduced into a node of the sampling network, and whether the parameter of the sampling network changes or not is judged by analyzing the measurement result of the signal processor on the detection signal, so that the fault source is positioned.
In the conventional art, a reference voltage source supplies a reference voltage to both the detection signal generation circuit and the analog-to-digital converter. In order to ensure the accuracy of the system, the reference voltage is generally required to have fast response and low noise. Specifically, it is necessary to connect a reference voltage source to an external pin and add a capacitance to the external pin. Since the reference voltage source is connected to the external pin, the chip is more easily damaged during operation, which causes the voltage value of the reference voltage source to change. However, when the voltage value of the reference voltage source changes, the detection signal generated by the detection signal generation circuit changes in proportion, and the detection signal is converted into a digital signal by the analog-to-digital converter and changes in inverse proportion, so that the detection value is kept unchanged and is the same as the reference value.
Therefore, the traditional measuring system cannot detect the fault that the reference voltage source changes, and the change of the reference voltage value provided by the reference voltage source cannot be identified.
Disclosure of Invention
The application aims to provide a parameter detection circuit with a reference detection function, and aims to solve the problem that a traditional parameter detection circuit cannot detect that a reference voltage source fails.
A parameter detection circuit comprising:
a first reference voltage source for providing a first reference voltage;
a crystal oscillator generating a clock reference signal;
the phase-locked loop is connected with the crystal oscillator and generates a second reference voltage according to the clock reference signal;
a detection signal generation circuit;
the selection switch is connected with the first reference voltage source, the phase-locked loop and the detection signal generating circuit, and is used for selecting one of the first reference voltage source and the phase-locked loop to be communicated with the detection signal generating circuit so as to provide a first reference voltage or a second reference voltage for the detection signal generating circuit; the detection signal generation circuit is configured to generate a first detection signal and a second detection signal according to the first reference voltage and the second reference voltage respectively;
the sampling network is connected with the measuring signal and the detection signal generating circuit, is configured to access the first detection signal and the second detection signal, and respectively outputs a first detection sampling signal and a second detection sampling signal;
the analog-to-digital converter is connected with the sampling network and the first reference voltage source and is used for converting the first detection sampling signal and the second detection sampling signal into corresponding digital signals under the condition that the first reference voltage source provides a first reference voltage;
and the signal processor is connected with the analog-to-digital converter and used for determining whether the first reference voltage source has a fault according to the first detection sampling signal and the second detection sampling signal which are converted into digital signals.
In one embodiment, the signal processor is specifically configured to determine whether the first reference voltage source has a fault according to a change in the calibrated value and the detected value of the first detection sample signal converted into a digital signal and a change in the calibrated value and the detected value of the second detection sample signal converted into a digital signal.
In one embodiment, the signal processor is further configured to determine whether the sampling network has a fault based on the first detected sampled signal calibration and detection value converted to a digital signal.
In one embodiment, the sampling network access measurement signal further outputs a measurement sampling signal, the analog-to-digital converter converts the measurement sampling signal into a digital signal, and the signal processor is further configured to perform the electric quantity measurement and the calibration thereof according to the first detection sampling signal and/or the second detection sampling signal converted into the digital signal and the measurement sampling signal.
In one embodiment, the frequencies of the first detection signal and the second detection signal are greater than the frequency of the measurement signal and are non-integer multiples of the measurement signal.
In one embodiment, the phase-locked loop and the signal processor are on-chip circuits of an integrated circuit, and at least part of the first reference voltage source, the crystal oscillator, the detection signal generating circuit and the sampling network are off-chip circuits of the integrated circuit
In one embodiment, the phase-locked loop includes a phase detector, a low-pass filter and a voltage-controlled oscillator, the first input end of the phase detector is connected to the output end of the crystal oscillator, the input end of the low-pass filter is connected to the output end of the phase detector, the output end of the low-pass filter serves as the output end of the phase-locked loop, the input end of the voltage-controlled oscillator is connected to the output end of the low-pass filter, and the output end of the voltage-controlled oscillator is connected to the second input end of the phase detector.
In one embodiment, the crystal oscillator includes a quartz crystal, an inverting amplifier, a feedback resistor, a first load capacitor and a second load capacitor, two ends of the quartz crystal, the inverting amplifier and the feedback resistor after being connected in parallel are grounded through the first load capacitor and the second load capacitor, respectively, and an output end of the inverting amplifier serves as an output end of the crystal oscillator.
The parameter detection circuit is provided with two different reference voltage signals by different circuits, and the detection of the other original reference voltage source is realized through one reference voltage signal so as to determine whether the other original reference voltage source has a fault or not, so that the detection precision of the parameter detection circuit is improved.
Drawings
Fig. 1 is a schematic structural diagram of a parameter detection circuit according to an embodiment of the present disclosure;
fig. 2 is a circuit diagram of a crystal oscillator in a parameter detection circuit according to an embodiment of the present application;
fig. 3 is a circuit diagram of a phase-locked loop in a parameter detection circuit according to an embodiment of the present disclosure;
fig. 4 is a flowchart of a parameter detection method according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It should be noted that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
Referring to fig. 1, a parameter detection circuit according to an embodiment of the present application includes: a first reference voltage source 10 for providing a first reference voltage, a crystal oscillator 20 for generating a clock reference signal, a phase locked loop 25, a detection signal generating circuit 30, a selection switch 40, a sampling network 50, an analog-to-digital converter 60 and a signal processor 70.
The phase locked loop 25 is connected to the crystal oscillator 20 and generates a second reference voltage based on a clock reference signal provided by the crystal oscillator 20. The selection switch 40 is connected with the first reference voltage source 10, the phase-locked loop 25 and the detection signal generating circuit 30, and the selection switch 40 is used for selecting one of the first reference voltage source 10 and the phase-locked loop 25 to be communicated with the detection signal generating circuit 30 so as to provide the first reference voltage or the second reference voltage for the detection signal generating circuit 30; the detection signal generation circuit 30 is configured to generate a first detection signal and a second detection signal from a first reference voltage and a second reference voltage, respectively.
The sampling network 50 is connected to the measurement signal and detection signal generating circuit 30, and is configured to access the first detection signal and the second detection signal and output the first detection sampling signal and the second detection sampling signal, respectively. The analog-to-digital converter 60 is connected to the sampling network 50 and the first reference voltage source 10, and is configured to convert the first detection sampling signal and the second detection sampling signal into corresponding digital signals when the first reference voltage source 10 provides the first reference voltage. The signal processor 70 is connected to the analog-to-digital converter 60, and is configured to determine whether the first reference voltage source 10 has a fault according to the first detection sample signal and the second detection sample signal converted into the digital signal.
In this embodiment, the analog-to-digital converter 60 is provided with a reference voltage by the first reference voltage source 10, and the first reference voltage source 10 needs to be connected to an external pin; the detection signal generating circuit 30 can select the reference voltage supplied from the first reference voltage source 10 or the phase-locked loop 25 through the selection switch. The crystal oscillator 20 and the phase locked loop 25 serve only as chip internal circuits and are not connected to external pins. Since the crystal oscillator 20 and the phase-locked loop 25 are only used as the chip internal circuit, they naturally have high reliability.
The working process of the application is divided into two stages: respectively a calibration stage and a use stage.
Wherein, the calibration stage is as follows: the sampling network 50 is calibrated by the detection signal at the initial factory shipment. The calibration phase is divided into two times: when the first reference voltage source 10 is selected to provide the reference voltage reference for the detection signal generating circuit 30, the value of the first detection sampling signal is calibrated to the calibrated value VEDTA0. When the crystal oscillator 20 and the phase-locked loop 25 are selected as the reference voltage reference supplied from the detection signal generating circuit 30, the value of the second detection sampling signal is calibrated to a calibrated value VEDTB0(ii) a The using stage is as follows: in use, when the first reference voltage source 10 is selected to provide the reference voltage reference for the detection signal generating circuit 30, the detection value V of the first detection sampling signal is detectedEDTANWith a calibrated value VEDTA0And (6) carrying out comparison. Periodically, when the crystal oscillator 20 and the phase-locked loop 25 are selected as the reference voltage reference supplied from the detection signal generating circuit 30, the detection value V of the second detection sampling signal is detectedEDTBNWith a calibrated value VEDTB0And (6) carrying out comparison.
Therefore, in one embodiment, the signal processor 70 is specifically configured to calibrate the value V according to the first detection sampling signal converted into the digital signalEDTA0And a detected value VEDTANAnd a calibration value V of the second detection sampling signal converted into the digital signalEDTB0And a detected value VEDTBNDetermines whether there is a fault in the first reference voltage source 10. Specifically, if the detection value V of the first detection sampling signal of the digital signalEDTANWith a calibrated value VEDTA0Same, but detected value V of second detected sample signal of digital signalEDTBNWith a calibrated value VEDTB0In contrast, it is assumed that the first reference voltage source 10 is changed, i.e., an abnormality exists, and a failure may occur.
The detection signal generation circuit 30 may be a voltage/current generation circuit.
In addition, in one embodiment, the signal processor 70 is further configured to determine whether the sampling network 50 is abnormal according to the calibration value of the first detection sampling signal converted into the digital signal and the variation of the detection value. Specifically, if the detected value V of the first detected sample signal converted into the digital signalEDTANWith a calibrated value VEDTA0Instead, the sampling network 50 parameters are changed.
Further, the sampling network 50 accesses the measurement signal and outputs a measurement sampling signal, the analog-to-digital converter 60 converts the measurement sampling signal into a digital signal, and the signal processor is further configured to perform the electrical quantity measurement and the calibration thereof according to the first detection sampling signal and/or the second detection sampling signal converted into the digital signal and the measurement sampling signal.
Further, the signal processor 70 processes the first detection sampling signal and the second detection sampling signal converted into digital signals to obtain an amplitude value and a phase value of the first detection sampling signal and an amplitude value and a phase value of the second detection sampling signal, respectively, and determines whether the circuit parameter of the sampling network 50 is abnormal according to at least one of an amplitude value change of the first detection sampling signal, an amplitude value change of the second detection sampling signal, a phase change of the first detection sampling signal, and a phase change of the second detection sampling signal. And the measurement sampling signal is calibrated according to the abnormal condition of the circuit parameters of the sampling network 50, so that the electric quantity measurement is carried out by using the accurate measurement sampling signal.
In one embodiment, the frequencies of the first detection signal and the second detection signal are greater than the frequency of the measurement sampling signal and are non-integer multiples of the measurement signal.
In one embodiment, the phase-locked loop 25 and the signal processor 70 are on-chip circuits of the integrated circuit, and at least some of the first reference voltage source 10, the crystal oscillator 20, the detection signal generating circuit 30 and the sampling network 50 are off-chip circuits of the integrated circuit. The external capacitor in the first reference voltage source 10 and the pin connected to the capacitor are off-chip circuits of the integrated circuit.
Referring to fig. 2, in one embodiment, the crystal oscillator 25 includes a quartz crystal, an inverting amplifier U1, a feedback resistor R0, a first load capacitor C0, and a second load capacitor C1, two ends of the quartz crystal, the inverting amplifier U1, and the feedback resistor R0 connected in parallel are grounded through the first load capacitor C0 and the second load capacitor C1, respectively, and an output end of the inverting amplifier U1 serves as an output end of the crystal oscillator 25 to output the clock reference signal CLK. Quartz crystal is an off-chip device for integrated circuits, being a piece of flat piezoresistor material that allows the conversion of mechanical and electrical energy, the exchange of this energy being most efficient at a particular frequency, the point of which is called the resonance frequency. The quartz crystal exhibits an inductance between the series resonance frequency and the parallel resonance frequency, and the oscillator can be formed by the inductance and a capacitive amplifier. The feedback resistor R0 is used for introducing direct current bias; the inverting amplifier U1 provides the necessary gain and produces a 180 ° phase shift; the load capacitors C0, C1 set the feedback factor of the circuit, in combination with the additional 180 ° phase shift required for the quartz crystal oscillator's inductive reactance to oscillate, to produce a highly accurate clock reference signal CLK.
Referring to fig. 3, in one embodiment, the phase locked loop 25 includes a phase detector 251, a low pass filter 252, and a voltage controlled oscillator 253, the phase detector 251 of whichA first input terminal is connected to the output terminal of the crystal oscillator 20, an input terminal of the low-pass filter 252 is connected to the output terminal of the phase detector 251, an output terminal of the low-pass filter 252 serves as the output terminal of the phase-locked loop 25, an input terminal of the voltage-controlled oscillator 253 is connected to the output terminal of the low-pass filter 252, and an output terminal of the voltage-controlled oscillator 253 is connected to the second input terminal of the phase detector 251. A feedback system consisting of a phase detector 251, a low-pass filter 252 and a voltage-controlled oscillator 253, wherein the phase detector 251 compares a feedback signal V of the voltage-controlled oscillator 253OUTAnd the phase of the clock reference signal CLK, an error is generated which is filtered by the low pass filter 252 to change the oscillation frequency of the voltage controlled oscillator 253 until the phases are aligned, i.e., the loop is locked. Wherein, the output V of the phase detector 251PDConsisting of a dc component (desired) and a high frequency component (undesired). The low pass filter 252 is used to suppress the high frequency component output from the phase detector 251 and only suppress the dc component VCONTTo the voltage controlled oscillator 253. The voltage controlled oscillator 253 generates a specific output frequency according to the input control voltage. In this embodiment, the output voltage V of the low-pass filter 252 is adjustedCONTAs a second reference voltage.
In another test mode, the first and second reference voltages may be generated by a reference circuit formed of a semiconductor device.
In addition, referring to fig. 4, a method for detecting parameters is also provided, which includes the following steps:
step S110, generating a first detection signal based on a first reference voltage generated by a first reference voltage source and loading the first detection signal on a sampling network to generate a first detection sampling signal;
step S120, generating a second detection signal based on a second reference voltage generated by a phase-locked loop, and loading the second detection signal onto a sampling network to generate a second detection sampling signal, wherein the phase-locked loop generates the second reference voltage according to a clock reference signal generated by a crystal oscillator;
step S130, converting the first detection sampling signal and the second detection sampling signal into digital signals, respectively, based on the first reference voltage;
step S140, determining whether the first reference voltage source has a fault according to the first detection sampling signal and the second detection sampling signal converted into the digital signal.
In one embodiment, determining whether the first reference voltage source has a fault according to the first detection sampling signal and the second detection sampling signal converted into the digital signal includes:
and determining whether the first reference voltage source has a fault according to the change of the calibration value and the detection value of the first detection sampling signal converted into the digital signal and the change of the calibration value and the detection value of the second detection sampling signal converted into the digital signal.
In one embodiment, the method further comprises determining whether the sampling network has a fault according to the calibration value and the change of the detection value of the first detection sampling signal converted into the digital signal.
In one embodiment, the method further comprises the following steps:
loading the measurement signal in a sampling network to generate a measurement sampling signal;
converting the measurement sampling signal into a digital signal based on the first reference voltage;
and carrying out electric quantity metering and calibration thereof according to the first detection sampling signal and/or the second detection sampling signal which are converted into digital signals and the measurement sampling signal.
According to the parameter detection circuit and the parameter detection method, different circuits provide two different reference voltage signals, and the detection of the other original reference voltage source is realized through one reference voltage signal so as to determine whether the other original reference voltage source has a fault or not, so that the detection precision of the parameter detection circuit is improved.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (8)
1. A parameter detection circuit, comprising:
a first reference voltage source for providing a first reference voltage;
a crystal oscillator for generating a clock reference signal;
the phase-locked loop is connected with the crystal oscillator and generates a second reference voltage according to the clock reference signal;
a detection signal generation circuit;
the selection switch is connected with the first reference voltage source, the phase-locked loop and the detection signal generating circuit, and is used for selecting one of the first reference voltage source and the phase-locked loop to be communicated with the detection signal generating circuit so as to provide a first reference voltage or a second reference voltage for the detection signal generating circuit; the detection signal generation circuit is configured to generate a first detection signal and a second detection signal according to the first reference voltage and the second reference voltage respectively;
the sampling network is connected with the measuring signal and the detection signal generating circuit, is configured to access the first detection signal and the second detection signal, and respectively outputs a first detection sampling signal and a second detection sampling signal;
the analog-to-digital converter is connected with the sampling network and the first reference voltage source and is used for converting the first detection sampling signal and the second detection sampling signal into corresponding digital signals under the condition that the first reference voltage source provides a first reference voltage; and
and the signal processor is connected with the analog-to-digital converter and used for determining whether the first reference voltage source is abnormal or not according to the first detection sampling signal and the second detection sampling signal which are converted into digital signals.
2. The parameter detection circuit according to claim 1, wherein the signal processor is specifically configured to determine whether the first reference voltage source is abnormal based on a change in the calibrated value and the detected value of the first detection sample signal converted into a digital signal and a change in the calibrated value and the detected value of the second detection sample signal converted into a digital signal.
3. The parameter detection circuit of claim 1, wherein the signal processor is further configured to determine whether the sampling network is abnormal based on the first detected sample signal calibration value and the change in the detected value converted to a digital signal.
4. The parameter detection circuit of claim 2, wherein the sampling network access measurement signal further outputs a measurement sample signal, the analog-to-digital converter converts the measurement sample signal to a digital signal, and the signal processor is further configured to perform the electrical quantity measurement and calibration thereof according to the first detection sample signal and/or the second detection sample signal converted to a digital signal and the measurement sample signal.
5. The parameter detection circuit of claim 4, wherein the frequencies of the first detection signal and the second detection signal are greater than the frequency of the measurement signal and are non-integer multiples of the measurement signal.
6. The parameter sensing circuit of claim 1, wherein the phase locked loop and the signal processor are on-chip circuitry of an integrated circuit, and wherein at least some of the first voltage reference source, the crystal oscillator, the sense signal generating circuit, and the sampling network are off-chip circuitry of the integrated circuit.
7. The parameter detection circuit according to any one of claims 1 to 6, wherein the phase-locked loop comprises a phase detector, a low-pass filter and a voltage-controlled oscillator, a first input terminal of the phase detector is connected to an output terminal of the crystal oscillator, an input terminal of the low-pass filter is connected to an output terminal of the phase detector, an output terminal of the low-pass filter serves as an output terminal of the phase-locked loop, an input terminal of the voltage-controlled oscillator is connected to an output terminal of the low-pass filter, and an output terminal of the voltage-controlled oscillator is connected to a second input terminal of the phase detector.
8. The parameter detection circuit according to any one of claims 1 to 6, wherein the crystal oscillator includes a quartz crystal, an inverting amplifier, a feedback resistor, a first load capacitor and a second load capacitor, two ends of the quartz crystal, the inverting amplifier and the feedback resistor after being connected in parallel are grounded through the first load capacitor and the second load capacitor, respectively, and an output end of the inverting amplifier serves as an output end of the crystal oscillator.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201922121522.8U CN211453930U (en) | 2019-11-28 | 2019-11-28 | Parameter detection circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201922121522.8U CN211453930U (en) | 2019-11-28 | 2019-11-28 | Parameter detection circuit |
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| CN211453930U true CN211453930U (en) | 2020-09-08 |
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