CN113452366A - PLL circuit and electronic equipment - Google Patents

PLL circuit and electronic equipment Download PDF

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Publication number
CN113452366A
CN113452366A CN202110832568.XA CN202110832568A CN113452366A CN 113452366 A CN113452366 A CN 113452366A CN 202110832568 A CN202110832568 A CN 202110832568A CN 113452366 A CN113452366 A CN 113452366A
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pll circuit
current
charge pump
voltage
capacitor
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CN113452366B (en
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田辉群
宋康
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Hytera Communications Corp Ltd
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Hytera Communications Corp Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

Abstract

The invention provides a PLL circuit and an electronic device, the PLL circuit includes: a charge pump and a current input module; the charge pump is used for receiving a control signal, and the control signal is used for controlling the charging current and the discharging current of the charge pump; one end of the current input module is connected with the voltage input end, and the other end of the current input module is connected with the output end of the charge pump; the current input module is used for outputting a target current. That is to say, the PLL circuit changes the on/off timing of the charge pump of the PLL circuit by externally connecting a current input module to the output terminal of the charge pump, and further changes the fractional modulation mode, thereby achieving the purpose of optimizing fractional spurs.

Description

PLL circuit and electronic equipment
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a PLL circuit and an electronic device.
Background
In digital logic circuit design, a frequency divider is a basic circuit; which is typically used to divide a given frequency to obtain a desired target frequency.
Based on an integer frequency divider, the implementation method is simple, and a standard counter can be adopted, and the implementation can also be realized by adopting a programmable logic device design.
However, in some cases, when the clock source is not an integer multiple of the required target frequency, a fractional divider is required to divide the frequency. For example, the division coefficient is a half integer divider of 2.5, 3.5, 7.5, etc.
Further, in the PLL (Phase Locked Loop) frequency synthesis technique, in order to reduce frequency stepping while ensuring low in-band noise, a PLL circuit including a fractional divider is also required. However, the use of fractional division inevitably results in fractional spurs, which in severe cases deteriorate the performance of the receiver and transmitter.
Therefore, how to suppress the fractional spur of the PLL circuit is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, to solve the above problems, the present invention provides a PLL circuit and an electronic device, and the technical solution is as follows:
a PLL circuit, the PLL circuit comprising: a charge pump and a current input module;
the charge pump is used for receiving a control signal, and the control signal is used for controlling the charging current and the discharging current of the charge pump;
one end of the current input module is connected with the voltage input end, and the other end of the current input module is connected with the output end of the charge pump;
the current input module is used for outputting a target current.
In the PLL circuit, a difference between the discharge current and the charge current is preferably equal to the target current.
Preferably, in the PLL circuit, the current input block is a constant current source.
Preferably, in the PLL circuit, the current input module is a load resistor;
the first end of the load resistor is connected with the voltage input end;
and the second end of the load resistor is connected with the output end of the charge pump.
Preferably, in the PLL circuit, the current input module includes: the circuit comprises a triode, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor;
the first end of the first resistor is connected with the first end of the first capacitor, and the connection node is connected with the base electrode of the triode;
the second end of the first resistor and the second end of the first capacitor are grounded respectively;
the first end of the second capacitor and the first end of the third capacitor are respectively connected with the first end of the second resistor, and a connection node is connected with an emitting electrode of the triode;
the second end of the second capacitor and the second end of the third capacitor are grounded respectively;
the second end of the second resistor is connected with the voltage input end;
and the collector electrode of the triode is connected with the output end of the charge pump.
Preferably, in the PLL circuit described above, the PLL circuit further includes: a loop filter;
wherein, the input end of the loop filter is connected with the output end of the charge pump;
the loop filter is used for generating a loop control voltage based on a sum of the charging current, the discharging current and the target current.
Preferably, in the PLL circuit described above, the PLL circuit further includes: a voltage controlled oscillator;
wherein the input end of the voltage-controlled oscillator is connected with the output end of the loop filter;
the output end of the voltage-controlled oscillator is used as the output end of the PLL circuit;
the loop control voltage is used to control the frequency of the output signal of the voltage controlled oscillator.
Preferably, in the PLL circuit described above, the PLL circuit further includes: a fractional frequency divider;
the input end of the decimal frequency divider is connected with the output end of the voltage-controlled oscillator;
the fractional frequency divider is used for receiving the output signal of the voltage-controlled oscillator and generating a feedback signal.
Preferably, in the PLL circuit described above, the PLL circuit further includes: a phase frequency detector;
the first input end of the phase frequency detector is used for receiving phase detection frequency signals;
the second input end of the phase frequency detector is connected with the output end of the fractional frequency divider and used for receiving the feedback signal;
the output end of the phase frequency detector is connected with the control end of the charge pump;
the phase frequency detector is used for generating the control signal according to the phase frequency detection signal and the feedback signal.
An electronic device comprising the PLL circuit of any of the above.
Compared with the prior art, the invention has the following beneficial effects:
the present invention provides a PLL circuit including: a charge pump and a current input module; the charge pump is used for receiving a control signal, and the control signal is used for controlling the charging current and the discharging current of the charge pump; one end of the current input module is connected with the voltage input end, and the other end of the current input module is connected with the output end of the charge pump; the current input module is used for outputting a target current. That is to say, the PLL circuit changes the timing sequence of the charge pump of the PLL circuit by externally connecting a current input module to the output terminal of the charge pump, and further changes the fractional modulation mode, thereby achieving the purpose of optimizing fractional spurious. Moreover, a charge pump and a frequency divider in the PLL circuit are integrated on a phase-locked loop chip, and a loop filter and a voltage-controlled oscillator are arranged outside the phase-locked loop chip; in general, the optimization of fractional spur needs to depend on a phase-locked loop chip, but the PLL circuit provided by the invention is additionally provided with a current input module, so that the time sequence of a charge pump of the PLL circuit can be changed, and further, the fractional modulation mode is changed, the PLL circuit is not required to modify a fractional frequency division modulation method in the phase-locked loop chip, the fractional spur can be improved through the current input module connected with the output end of the charge pump of the phase-locked loop chip, and the optimization of the fractional spur of the PLL circuit does not depend on the phase-locked loop chip.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of a PLL circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of another PLL circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of another PLL circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of another PLL circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of another PLL circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of another PLL circuit according to an embodiment of the present invention;
fig. 7 is a schematic diagram of another PLL circuit according to an embodiment of the present invention;
fig. 8 is a schematic diagram of another PLL circuit according to an embodiment of the present invention;
fig. 9 is a schematic diagram of another PLL circuit according to an embodiment of the present invention;
FIG. 10 is a waveform diagram illustrating a conventional PLL circuit during locking;
FIG. 11 is a schematic diagram of spur analysis when a conventional PLL circuit is locked;
FIG. 12 is a waveform diagram illustrating the PLL circuit locking according to an embodiment of the present invention;
FIG. 13 is a schematic diagram illustrating spur analysis when a PLL circuit is locked according to an embodiment of the present invention;
FIG. 14 is another equivalent diagram of the spur analysis diagram of FIG. 13.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a novel PLL circuit structure, which realizes effective suppression on fractional stray of the PLL circuit, thereby improving the performance of the PLL circuit.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, fig. 1 is a schematic diagram of a PLL circuit according to an embodiment of the present invention.
The PLL circuit includes: a charge pump CP and a current input module 11.
The charge pump CP is configured to receive a control signal, and the control signal is configured to control a charging current and a discharging current of the charge pump CP.
One end of the current input module 11 is connected to the voltage input terminal VCC, and the other end is connected to the output terminal of the charge pump CP.
The current input module 11 is used for outputting a target current.
In this embodiment, the control signal is used to control the operating state of the charge pump CP, which includes at least a charging state and a discharging state; the charge pump CP is in a charging state and is used for transmitting charging current; the charge pump CP is in a discharge state for delivering a discharge current.
Furthermore, based on the current charge pump CP PLL circuit structure, the current input module 11 is externally connected to the output end of the charge pump CP, so that the timing sequence of the charge pump of the PLL circuit is changed, and then the fractional modulation mode is changed, thereby achieving the purpose of optimizing fractional stray.
The charge pump of the PLL circuit is integrated on a phase-locked loop chip, and the optimization of fractional spurious needs to depend on the phase-locked loop chip under the normal condition.
Further, according to the above embodiment of the present invention, the difference between the discharge current and the charge current is equal to the target current. It should be noted that, in a working cycle, the discharge current has at least one current value different from 0, a ratio of a product of an absolute value of the current value and a current value maintaining time to the working cycle is a first ratio, in a working cycle, the charge current has at least one current value different from 0, a ratio of a product of an absolute value of the current value and the current value maintaining time to the working cycle is a second ratio, and a difference between the discharge current and the charge current is a difference between the first ratio and the second ratio, that is, a difference between the first ratio and the second ratio is equal to the target current. It should be further noted that, in one duty cycle, the discharge current may have a plurality of current values different from 0, and when the discharge current has a plurality of current values different from 0 in one duty cycle, obtaining the first ratio includes: obtaining products of absolute values of current values which are not 0 and respective maintaining time of the current values, and obtaining sum values of the products, wherein the first ratio is the ratio of the sum value to the working period; similarly, when there are a plurality of currents other than 0 in the charging current in one duty cycle, the second ratio may be obtained according to the above calculation method.
Specifically, as shown in FIG. 12, I in FIG. 10SOURCERepresenting a charging current, said charging current having 6 current values other than 0 during a duty cycle, and deriving a first ratio comprises: obtaining the product of the absolute value of the 6 currents different from 0 and the respective maintaining time, and obtaining the respective currentA sum of the products, the first ratio being a ratio of the sum to the duty cycle; i in FIG. 10SINXRepresenting a charging current, said discharging current having 6 current values other than 0 during a duty cycle, and obtaining a second ratio comprises: and obtaining products of the absolute values of the 6 current values which are not 0 and the respective maintenance time of the current values, and obtaining the sum of the products, wherein the second ratio is the ratio of the sum to the working period.
In this embodiment, the final output current of the charge pump and the current input module is: a current after the discharge current, the charge current, and the target current are superimposed.
Further, based on the above-mentioned embodiment of the present invention, referring to fig. 2, fig. 2 is a schematic diagram of another PLL circuit according to an embodiment of the present invention.
The PLL circuit further includes: a loop filter LPF.
Wherein, the input end of the loop filter LPF is connected with the output end of the charge pump CP.
The loop filter LPF is used for generating a loop control voltage based on the charging current, the discharging current and the current after the target current is superposed.
In this embodiment, the loop filter LPF filters the current finally output by the charge pump CP and the current input module 11, and generates a loop control voltage CV.
Alternatively, referring to fig. 3, fig. 3 is a schematic diagram of a PLL circuit according to another embodiment of the present invention.
The loop filter LPF is an RC filter or a linear filter.
As shown in fig. 3, the loop filter LPF is an RC filter and is composed of a plurality of capacitors C and a plurality of resistors R.
Further, based on the above-mentioned embodiment of the present invention, referring to fig. 4, fig. 4 is a schematic diagram of another PLL circuit according to an embodiment of the present invention.
The PLL circuit further includes: a voltage controlled oscillator VCO.
Wherein, the input end of the voltage-controlled oscillator VCO is connected with the output end of the loop filter LPF.
The loop control voltage CV is used to control the frequency of the output signal of the voltage controlled oscillator VCO.
In this embodiment, the loop control voltage CV is used to control the frequency of the output signal of the voltage-controlled oscillator VCO, and generally, when the loop control voltage CV is at a high level, the frequency of the output signal of the voltage-controlled oscillator VCO increases; when the loop control voltage CV is low, the frequency of the output signal of the voltage controlled oscillator VCO decreases.
Further, based on the above-mentioned embodiment of the present invention, referring to fig. 5, fig. 5 is a schematic diagram of another PLL circuit according to an embodiment of the present invention.
The PLL circuit further includes: and the decimal frequency divider DIV and the current pump CP are integrated in a phase-locked loop chip.
The input terminal of the fractional divider DIV is connected to the output terminal of the voltage controlled oscillator VCO.
The fractional divider DIV is configured to receive an output signal of the voltage controlled oscillator VCO and generate a feedback signal.
In this embodiment, the frequency division coefficient of the fractional frequency divider DIV is determined according to an actual requirement, and further, the frequency division processing is performed on the output signal of the voltage controlled oscillator VCO according to the frequency division coefficient to generate the feedback signal.
Further, based on the above-mentioned embodiment of the present invention, referring to fig. 6, fig. 6 is a schematic diagram of another PLL circuit according to an embodiment of the present invention.
The PLL circuit further includes: and the phase frequency detector PFD, the fractional frequency divider and the current pump are integrated in a phase-locked loop chip.
The first input end of the phase frequency detector PFD is used for receiving a phase frequency detection signal VREF。
A second input terminal of the phase frequency detector PFD is connected to an output terminal of the fractional frequency divider DIV for receiving the feedback signal VFB。
The output end of the phase frequency detector PFD is connected to the control end of the charge pump CP.
The phase frequency detector PFD is used for detecting the phase frequency signal V according toREFAnd the feedback signal VFBAnd generating the control signal.
In this embodiment, the control signal is used to control the operating state of the charge pump CP, which includes at least a charging state and a discharging state; in a charging state, for delivering a charging current; in the discharge state, for delivering a discharge current. Which in turn controls the magnitude of the voltage CV.
Further, based on the above-mentioned embodiment of the present invention, referring to fig. 7, fig. 7 is a schematic diagram of another PLL circuit according to an embodiment of the present invention.
The current input module 11 is a constant current source 12.
In this embodiment, the constant current source 12 is a constant current source for outputting a preset target current.
Further, based on the above-mentioned embodiment of the present invention, referring to fig. 8, fig. 8 is a schematic diagram of another PLL circuit according to an embodiment of the present invention.
The current input module 11 is a load resistor Rs.
Wherein a first terminal of the load resistor Rs is connected to the voltage input terminal VCC.
A second terminal of the load resistor Rs is connected to an output terminal of the charge pump CP.
In this embodiment, the resistance of the load resistor Rs depends on the magnitude of the target current and the voltage at the voltage input terminal.
Further, based on the above-mentioned embodiment of the present invention, referring to fig. 9, fig. 9 is a schematic diagram of a PLL circuit according to another embodiment of the present invention.
The current input module 11 includes: the circuit comprises a triode Q, a first resistor R1, a second resistor R2, and first to third capacitors C1-C3.
The first end of the first resistor R1 is connected with the first end of the first capacitor C1, and the connection node is connected with the base of the triode Q.
The second end of the first resistor R1 and the second end of the first capacitor C1 are respectively grounded.
A first end of the second capacitor C2 and a first end of the third capacitor C3 are respectively connected to a first end of the second resistor R2, and a connection node is connected to an emitter of the transistor Q.
The second terminal of the second capacitor C2 and the second terminal of the third capacitor C3 are respectively grounded.
The second end of the second resistor R2 is connected to the voltage input VCC.
And the collector of the triode Q is connected with the output end of the charge pump CP.
Further, based on all the above embodiments of the present invention, the following explains the principle of the PLL circuit provided by the present invention again:
first, an analysis is made based on the fractional spur case of a conventional PLL circuit.
For example, to implement a division of N +1/6, in 6 divisions, where N division is performed 5 times and N +1 division is performed 1 time, the cumulative division number is (5 · N + (N +1))/6 ═ N + 1/6.
Referring to fig. 10, fig. 10 is a waveform diagram illustrating a locked state of a conventional PLL circuit.
Wherein, VREFRepresenting a phase discrimination reference frequency waveform; vFBRepresents the output signal waveform of the fractional divider; i isSOURCEA waveform representing a charge state of the charge pump; i isSINXA waveform representing a discharge state of the charge pump; i isCPRepresenting the final output current waveform of the charge pump.
Referring to fig. 11, fig. 11 is a schematic diagram illustrating the spurious analysis when the conventional PLL circuit is locked.
Assuming that the period of the phase demodulation reference frequency of the phase frequency detector is T, a time constant T is set for convenient analysis0Said time constant t0The basic unit of abscissa, i.e. t, of the above-mentioned stray permission diagram1、t2、t3、t4、t5、t6Is t0The fractional spurious distribution period is 6 × T for 1/6 frequency division, and spurious caused by fractional frequency division is low, has the largest influence on the whole PLL circuit, and is most difficult to filter.
As shown in fig. 11, for each spur point phase, the following relationship exists:
θ1＝θ(t1)＝θ(t4)-π；
θ2＝θ(t2)＝θ(t5)-π；
θ3＝θ(t3)＝θ(t6)-π。
then, the spurious signal with period of 6 × T is Fourier transformed to have frequency ω0Taking only the fundamental term can obtain:
f(t)＝Icp·K·6·t0·[sin(ω0·t+θ1)+sin(ω0·t+θ2)+sin(ω0·t+θ3)]
where K denotes the Fourier transform coefficient of a square wave, IcpIs a fixed value, t, set according to the frequency of the output of the phase-locked loop circuit0Is also a fixed value set.
This can be used to derive the fractional spur of conventional PLL circuits.
Secondly, the fractional spurious condition of the PLL circuit provided by the embodiment of the invention is analyzed.
Referring to fig. 12, fig. 12 is a waveform diagram illustrating a locked state of a PLL circuit according to an embodiment of the present invention.
For example, a constant current source is applied to the output end of the charge pump, and the target current output by the constant current source is set as follows: 4. t0·ICPa/T; the locking waveform is shown in fig. 12.
Wherein, VREFRepresenting a phase discrimination reference frequency waveform; vFBRepresents the output signal waveform of the fractional divider; i isSOURCEA waveform representing a charge state of the charge pump; i isSINXA waveform representing a discharge state of the charge pump; i isCPRepresenting the final output current waveform of the charge pump.
At this time, ISINXRatio ISOURCELarge 4. t0·ICPand/T. It should be noted that the conventional PLL circuit has the following stable conditions: in a period T, the current of the current pump CP needs to satisfy that the difference between the charging current and the discharging current is 0, and in the embodiment of the present application, a constant current source is added at the output end of the current pump, and the target current is: 4. t0·ICPT, so as to ensure the stability of the PLL circuit, ISINXRatio ISOURCELarge 4. t0·ICP/T。
Referring to FIG. 13, FIG. 13 is a schematic diagram of spurious analysis during PLL circuit locking according to an embodiment of the present invention, I11Representing the waveform of a constant current source, effectively ICPBecome toCP1And I isCP-ICP1＝4·t0·ICP/T。
Referring to fig. 14, fig. 14 is another equivalent diagram of the stray analysis diagram shown in fig. 13.
By the same method as above for ICP1Fourier transform can be performed to obtain:
f1'(t)＝ICP·K·6·t0·[(1-8·t0/(3·T))Sin(ω0·t+θ1)+(1-4·t0/T)Sin(ω0·t+θ2)+(1-4·t0/T)Sin(ω0·t+θ3)]
then by comparing f (t) and f1(t) it can be seen that for the same phase of the signal amplitude, f1(t) is lower than f (t), i.e.:
for the fundamental wave of the spurious signal, the amplitude of the PLL circuit provided by the invention is lower than that of the traditional PLL circuit.
In some specific practices, it has been found that about 15dB can be optimized.
As can be seen from the above description, the PLL circuit provided by the present invention changes the on/off timing sequence of the charge pump of the PLL circuit by externally connecting a current input module to the output terminal of the charge pump, so as to change the fractional modulation mode, thereby achieving the purpose of optimizing fractional spurs.
Moreover, the improvement mode has no dependence on the PLL circuit, the PLL circuit is not required to open any authority, and the improvement cost is low.
Based on all the above embodiments of the present invention, in another embodiment of the present invention, there is further provided an electronic device, which includes the PLL circuit described in the above embodiments.
The PLL circuit and the electronic device provided by the present invention are described in detail above, and a specific example is applied in the present document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include or include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A PLL circuit, comprising: a charge pump and a current input module;
the charge pump is used for receiving a control signal, and the control signal is used for controlling the charging current and the discharging current of the charge pump;
one end of the current input module is connected with the voltage input end, and the other end of the current input module is connected with the output end of the charge pump;
the current input module is used for outputting a target current.
2. The PLL circuit of claim 1, wherein a difference between the discharge current and the charge current is equal to the target current.
3. The PLL circuit of claim 1, wherein the current input module is a constant current source.
4. The PLL circuit of claim 1, wherein the current input module is a load resistor;
the first end of the load resistor is connected with the voltage input end;
and the second end of the load resistor is connected with the output end of the charge pump.
5. The PLL circuit of claim 1, wherein the current input module comprises: the circuit comprises a triode, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor;
the first end of the first resistor is connected with the first end of the first capacitor, and the connection node is connected with the base electrode of the triode;
the second end of the first resistor and the second end of the first capacitor are grounded respectively;
the first end of the second capacitor and the first end of the third capacitor are respectively connected with the first end of the second resistor, and a connection node is connected with an emitting electrode of the triode;
the second end of the second capacitor and the second end of the third capacitor are grounded respectively;
the second end of the second resistor is connected with the voltage input end;
and the collector electrode of the triode is connected with the output end of the charge pump.
6. The PLL circuit of claim 1, wherein the PLL circuit further comprises: a loop filter;
wherein, the input end of the loop filter is connected with the output end of the charge pump;
the loop filter is used for generating a loop control voltage based on a sum of the charging current, the discharging current and the target current.
7. The PLL circuit of claim 6, further comprising: a voltage controlled oscillator;
wherein the input end of the voltage-controlled oscillator is connected with the output end of the loop filter;
the output end of the voltage-controlled oscillator is used as the output end of the PLL circuit;
the loop control voltage is used to control the frequency of the output signal of the voltage controlled oscillator.
8. The PLL circuit of claim 7, wherein the PLL circuit further comprises: a fractional frequency divider;
the input end of the decimal frequency divider is connected with the output end of the voltage-controlled oscillator;
the fractional frequency divider is used for receiving the output signal of the voltage-controlled oscillator and generating a feedback signal.
9. The PLL circuit of claim 8, wherein the PLL circuit further comprises: a phase frequency detector;
the first input end of the phase frequency detector is used for receiving phase detection frequency signals;
the second input end of the phase frequency detector is connected with the output end of the fractional frequency divider and used for receiving the feedback signal;
the output end of the phase frequency detector is connected with the control end of the charge pump;
the phase frequency detector is used for generating the control signal according to the phase frequency detection signal and the feedback signal.
10. An electronic device, characterized in that the electronic device comprises a PLL circuit according to any of claims 1-9.
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JP2002217723A (en) * 2001-01-23 2002-08-02 Mitsubishi Electric Corp Pll frequency synthesizer of decimal point frequency division system
US20050156673A1 (en) * 2004-01-20 2005-07-21 Harald Pretl Circuit and method for phase locked loop charge pump biasing
KR20070012999A (en) * 2005-07-25 2007-01-30 삼성전자주식회사 Process-insensitive phase locked loop circuit and self biasing method thereof
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