CN113098447A - Duty ratio sampling circuit, duty ratio sampling method and LED drive circuit - Google Patents
Duty ratio sampling circuit, duty ratio sampling method and LED drive circuit Download PDFInfo
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Abstract
The invention provides a duty ratio sampling circuit, a duty ratio sampling method and an LED driving circuit. The input end of the phase-locked loop is used for receiving the square wave signal, and the phase-locked loop is used for carrying out frequency multiplication processing according to the square wave signal to generate a frequency multiplication signal. The first input end of the counting circuit is coupled with the output end of the phase-locked loop to receive the frequency multiplication signal, the second input end of the counting circuit is used for receiving the square wave signal, and the counting circuit is used for counting according to the square wave signal and the frequency multiplication signal and outputting the counting signal to represent the duty ratio of the square wave signal. Furthermore, the duty ratio of the square wave signal can be characterized by converting the counting signal into an analog signal through a digital-to-analog conversion circuit. According to the duty ratio sampling circuit, the duty ratio sampling method and the LED driving circuit, the duty ratio information of the square wave signal is obtained in a digital quantization mode, the representation precision of the duty ratio is high, the scheme implementation cost is low, the response speed is high, and no ripple wave influence exists.
Description
Technical Field
The invention belongs to the technical field of power electronics, relates to a duty cycle sampling technology, and particularly relates to a duty cycle sampling circuit, a duty cycle sampling method and an LED driving circuit.
Background
In a specific circuit application, it is usually necessary to know the duty ratio information of the square wave signal, for example, in an application scenario of an LED driving circuit. For sampling the duty ratio of a square wave signal, a voltage signal similar to direct current can be obtained through a resistor-capacitor circuit (RC filter for short) or an active filter, and the magnitude of the duty ratio is represented through the voltage signal. As shown in fig. 1, the square wave signal is input to a low pass filter, and a voltage signal similar to dc is obtained after filtering processing by the low pass filter. Under the premise that the high level value and the low level value are known, the amplitude of the voltage signal approximate to direct current represents the product of the difference between the high level value and the low level value of the square wave signal and the duty ratio, and the low level value is added, so that the duty ratio information of the square wave signal is obtained. However, in the above method, a large capacitive circuit network or a high-order operational amplifier is required to implement the low-pass filtering function, and meanwhile, the voltage signal obtained after the low-pass filtering still has a ripple with a certain amplitude, and if the ripple is to be reduced, the cost of the filter circuit will be further increased. It should be noted that the ripple is more pronounced when the frequency of the input square wave signal is lower. In addition, the filter circuit may have a delay condition, so that the response speed of the output dc voltage signal is slow. On the other hand, the amplitude of the dc voltage signal is related to the high and low level values of the input square wave signal, and therefore the amplitude of the dc voltage signal cannot directly reflect the magnitude of the duty ratio.
In view of the above, it is desirable to provide a new structure or control method for solving the above existing technical problems.
Disclosure of Invention
In order to solve at least part of problems, the invention provides a duty ratio sampling circuit, a duty ratio sampling method and an LED driving circuit, the duty ratio has high representation precision, the scheme implementation cost is low, the response speed is high, and no ripple wave influence exists.
In one embodiment of the present invention, a duty cycle sampling circuit is disclosed, which includes:
the input end of the phase-locked loop is used for receiving a square wave signal and carrying out frequency multiplication processing according to the square wave signal to generate a frequency multiplication signal; and
and the counting circuit is coupled with the phase-locked loop at a first input end, is used for receiving the square wave signal at a second input end, and is used for counting according to the square wave signal and the frequency doubling signal and outputting a counting signal, wherein the counting signal is used for representing the duty ratio of the square wave signal.
As an embodiment of the present invention, the count signal includes a first count signal and a second count signal; counting the frequency-doubled signal when the square wave signal is at a first level during a period of the square wave signal to obtain a first count signal, and counting the frequency-doubled signal during the period of the square wave signal to obtain a second count signal.
As an embodiment of the present invention, the counting circuit includes a clock signal input terminal and an enable terminal, the clock signal input terminal is coupled to the frequency multiplication signal output terminal of the phase-locked loop, and the enable terminal is configured to receive the square wave signal.
As an embodiment of the present invention, the duty cycle sampling circuit further includes:
and the input end of the digital-to-analog conversion circuit is coupled with the output end of the counting circuit and is used for performing digital-to-analog conversion according to the counting signal and outputting a duty ratio characterization signal, and the duty ratio characterization signal characterizes the duty ratio of the square wave signal.
As an embodiment of the present invention, the phase-locked loop includes:
a phase discriminator, the first input end of which is used for receiving the square wave signal;
the input end of the low-pass filter is coupled with the output end of the phase discriminator;
the input end of the voltage-controlled oscillator is coupled with the output end of the low-pass filter and is used for outputting the frequency multiplication signal; and
and the input end of the frequency divider is coupled with the output end of the voltage-controlled oscillator, and the output end of the frequency divider is coupled with the second input end of the phase discriminator.
As an embodiment of the present invention, the phase-locked loop performs an nth power frequency multiplication process of 2 according to the square wave signal to generate a frequency multiplication signal, and the counting circuit is an N-bit counter; wherein N is a positive integer.
As an embodiment of the invention, the duty cycle of the square wave signal is equal to D1/D2, or the duty cycle of the square wave signal is equal to 1- (D1/D2); wherein D1 is the first count signal, and D2 is the second count signal.
As an embodiment of the present invention, the duty ratio characterization signal is a dc voltage signal or a dc current signal.
The embodiment of the invention also discloses an LED drive circuit, which comprises a drive control circuit and an LED load, wherein the drive control circuit comprises any one of the duty ratio sampling circuits.
The embodiment of the invention also discloses a duty ratio sampling method, which comprises the following steps:
receiving a square wave signal, and performing frequency multiplication processing according to the square wave signal to generate a frequency multiplication signal; and
counting according to the square wave signal and the frequency doubling signal and outputting a counting signal, wherein the counting signal is used for representing the duty ratio of the square wave signal.
As an embodiment of the present invention, the count signal includes a first count signal and a second count signal; the step of counting according to the square wave signal and the frequency multiplication signal specifically comprises:
counting the frequency-doubled signal when the square wave signal is at a first level during a period of the square wave signal to obtain a first count signal, and counting the frequency-doubled signal during the period of the square wave signal to obtain a second count signal.
As an embodiment of the present invention, the duty cycle sampling method further includes:
and performing digital-to-analog conversion according to the counting signal to generate a direct current voltage signal or a direct current signal representing the duty ratio of the square wave signal.
As an embodiment of the present invention, the duty cycle sampling method further includes:
carrying out N power frequency multiplication processing of 2 according to the square wave signal to generate a frequency multiplication signal, wherein a counting circuit for counting is an N-bit counter; wherein N is a positive integer.
The invention provides a duty ratio sampling circuit, a duty ratio sampling method and an LED driving circuit, wherein the duty ratio sampling circuit comprises a phase-locked loop and a counting circuit. The input end of the phase-locked loop is used for receiving the square wave signal, and the phase-locked loop is used for carrying out frequency multiplication processing according to the square wave signal to generate a frequency multiplication signal. The first input end of the counting circuit is coupled with the output end of the phase-locked loop to receive the frequency multiplication signal, the second input end of the counting circuit is used for receiving the square wave signal, the counting circuit is used for counting according to the square wave signal and the frequency multiplication signal and outputting a counting signal, and the counting signal is used for representing the duty ratio of the square wave signal. In addition, the duty cycle sampling method includes: receiving the square wave signal, and carrying out frequency multiplication processing according to the square wave signal to generate a frequency multiplication signal; and counting according to the square wave signal and the frequency multiplication signal and outputting a counting signal, wherein the counting signal is used for representing the duty ratio of the square wave signal. According to the duty ratio sampling circuit, the duty ratio sampling method and the LED driving circuit, the duty ratio information of the square wave signal is obtained in a digital quantization mode, the representation precision of the duty ratio of the square wave signal is high, the scheme implementation cost is low, the response speed is high, and no ripple wave influence exists.
Drawings
FIG. 1 shows a schematic circuit diagram of a prior art duty cycle sampling circuit;
FIG. 2 shows a circuit schematic of a duty cycle sampling circuit according to an embodiment of the invention;
FIG. 3 is a waveform diagram illustrating signals in a duty cycle sampling circuit according to an embodiment of the present invention;
fig. 4 shows a schematic step diagram of a duty cycle sampling method according to an embodiment of the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
For a further understanding of the invention, reference will now be made to the preferred embodiments of the invention by way of example, and it is to be understood that the description is intended to further illustrate features and advantages of the invention, and not to limit the scope of the claims.
The description in this section is for several exemplary embodiments only, and the present invention is not limited only to the scope of the embodiments described. It is within the scope of the present disclosure and protection that the same or similar prior art means and some features of the embodiments may be interchanged.
The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a connection made through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connections may also include connections through other active or passive devices, such as connections through switches, follower circuits, etc., that serve the same or similar functional purpose.
The invention discloses a duty cycle sampling circuit which comprises a phase-locked loop and a counting circuit, wherein the input end of the phase-locked loop is used for receiving a square wave signal, the phase-locked loop is used for carrying out frequency multiplication processing according to the square wave signal, the output end of the phase-locked loop outputs a frequency multiplication signal, and the frequency multiplication value can be set according to the specific circuit requirement. The first input end of the counting circuit is coupled with the output end of the phase-locked loop, the second input end of the counting circuit is used for receiving the square wave signal, the counting circuit is used for counting according to the square wave signal and the frequency doubling signal and outputting a counting signal, and the counting signal is used for representing the duty ratio of the square wave signal. The phase-locked loop is combined with the counting circuit to obtain the duty ratio information of the square wave signal in a digital quantization mode, the characterization precision of the duty ratio is high, the scheme implementation cost is low, the response speed is high, and no ripple wave influence exists.
As shown in fig. 2, in an embodiment of the present invention, the duty cycle sampling circuit includes a phase locked loop 10 and a counting circuit, in this embodiment, the counting circuit is embodied as a counter 20. The input terminal of the phase-locked loop 10 is coupled to the output terminal of the square-wave signal generating circuit, the square-wave signal generating circuit outputs a square-wave signal f0, and the input terminal of the phase-locked loop 10 receives a square-wave signal f0, wherein the frequency of the square-wave signal f0 may be f 0. The phase-locked loop 10 is used for performing frequency multiplication processing according to the square wave signal f0 to generate a frequency multiplication signal f 1. In one embodiment, the PLL 10 generates the multiplied signal f1 by multiplying the square wave signal f0 by 2^ N, and the frequency f1 of the multiplied signal f1 is equivalent to the frequency 2^ N × f 0. In the embodiment shown in fig. 2, the counter 20 includes a clock signal input terminal coupled to the output terminal of the phase-locked loop 10 and an enable terminal coupled to the output terminal of the square-wave signal generating circuit to receive the square-wave signal f 0. The counter 20 is configured to count according to the square wave signal f0 and the frequency doubling signal f1 and output a count signal, wherein the count signal is used for representing the duty ratio of the square wave signal f 0.
In a particular embodiment, the count signals output by the counter 20 include a first count signal and a second count signal. As can be appreciated from fig. 2 and 3, the square wave signal f0 consists of a high level and a low level. When the square wave signal is at a first level (e.g., high level) during a period of the square wave signal, the counter 20 is enabled, and the counter 20 counts the frequency-multiplied signal to obtain a first count signal D1. That is, in the present embodiment, it is considered that the high level of the square wave signal is the first level and the low level of the square wave signal is the second level. It should be noted that the enabling end of the counter 20 controls the counting process of the first counting signal D1, and the counter 20 is not limited to counting other signals individually. In addition, the frequency-multiplied signal is counted within the period of the square wave signal to obtain a second count signal D2. Wherein the duty cycle of the square wave signal is characterized by the first count signal and the second count signal. In the present embodiment, the duty cycle of the square wave signal is equal to D1/D2. After the counting period is finished, the first counting signal and the second counting signal can be cleared, and counting can be restarted when the next counting period is started. The specific process of counting the frequency-doubled signal may be to count once a first level (for example, a high level) of the frequency-doubled signal, or to count once a second level (for example, a low level) of the frequency-doubled signal. In another embodiment, the first level (e.g., high level) and the second level (e.g., low level) of the frequency multiplied signal may be counted once respectively to obtain the count signal. In the process of obtaining the first count signal D1 and the second count signal D2, the frequency multiplication signals are counted in the same way. The above three ways of counting the frequency-doubled signals can be selected to obtain the first count signal D1 and the second count signal D2, respectively.
In another embodiment of the present invention, the count signal output by the counter 20 includes a first count signal and a second count signal. When the square wave signal is at a first level (e.g., a low level) during a period of the square wave signal, the counter 20 is enabled to count the frequency-multiplied signal to obtain a first count signal D1'. That is, in the present embodiment, the low level of the square wave signal is assumed to be the first level, and the high level of the square wave signal is assumed to be the second level. It should be noted that the enabling terminal of the counter 20 controls the counting process of the first counting signal D1'. In addition, the frequency-multiplied signal is counted within the period of the square wave signal to obtain a second count signal D2. The first count signal D1 'in the present embodiment is different from the first count signal D1 in the previous embodiment, and the duty cycle of the square wave signal is equal to 1- (D1'/D2) in the present embodiment.
In an embodiment of the invention, as shown in fig. 2, the Phase-locked loop 10 includes a Phase Detector (PD) 110, a Low Pass Filter (LPF) 120, a Voltage Controlled Oscillator (VCO) 130, and a frequency Divider (DIV) 140. The phase detector 110 has a first input terminal for receiving the square wave signal f0, and the phase detector 110 is configured to perform frequency comparison according to the input square wave signal f0 and the frequency division signal f1 'fed back from the frequency divider, so as to output a difference signal representing the difference between the square wave signal f0 and the frequency division signal f 1'. An input terminal of the low pass filter 120 is coupled to an output terminal of the phase detector 110, and the low pass filter 120 is configured to filter out a high frequency component of the difference signal generated by the phase detector 110, thereby generating a filtered signal. The input terminal of the voltage controlled oscillator 130 is coupled to the output terminal of the low pass filter, and the voltage controlled oscillator 130 is configured to generate a frequency multiplication signal according to the filtered signal output by the low pass filter 120. The input terminal of the frequency divider 140 is coupled to the output terminal of the voltage controlled oscillator 130, and the frequency divider 140 is configured to divide the frequency of the frequency multiplied signal output by the voltage controlled oscillator 130. In another embodiment of the present invention, the frequency multiplication value of the phase locked loop 10 matches the number of bits of the counter 20. In a preferred embodiment, the PLL 10 performs a 2^ N frequency multiplication according to the square wave signal f0 to generate a frequency multiplication signal f1, the frequency multiplication signal f1 is equivalent to the frequency 2^ N × f0, and the counter 20 is an N-bit counter; wherein N is a positive integer greater than 1. The sampling accuracy of the duty cycle sampling circuit can be set by the number of bits N of the counter 20, with the higher the value of N is set, the higher the duty cycle sampling accuracy. Of course, when the N value is set too high, the implementation complexity is large, and a reasonable N value should be selected in a specific application.
In an embodiment of the present invention, as shown in fig. 2, the duty ratio sampling circuit further includes a digital-to-analog conversion circuit 30, an input end of the digital-to-analog conversion circuit 30 is coupled to an output end of the counter 20, and an output end of the digital-to-analog conversion circuit 30 outputs a duty ratio characterizing signal that characterizes a duty ratio of the square wave signal f 0. The number of bits of the digital-to-analog conversion circuit 30 and the number of bits of the counter 20 may be equal or may not be equal. In a specific embodiment, the digital-to-analog conversion circuit 30 generates a duty ratio characterization signal according to the first count signal D1 and the second count signal D2 output by the counter 20, where the duty ratio characterization signal is an analog quantity. In another embodiment, the duty cycle characterizing signal may be a dc voltage signal V1 or a dc current signal.
In another embodiment of the present invention, the duty cycle sampling circuit includes a phase-locked loop and a counting circuit, a first input terminal of the phase-locked loop is coupled to the output terminal of the square wave signal generating circuit to receive the square wave signal, and the phase-locked loop is configured to perform a frequency multiplication process according to the square wave signal to generate a frequency multiplication signal. The first input end of the counting circuit is coupled with the output end of the square wave signal generating circuit to receive the square wave signal, the second input end of the counting circuit is coupled with the output end of the phase-locked loop to receive the frequency doubling signal, and the counting circuit counts according to the square wave signal and the frequency doubling signal to obtain a counting signal representing the duty ratio of the square wave signal. In a specific embodiment, the output terminal of the counting circuit is further coupled to the second input terminal of the phase-locked loop. The counting signals output by the counter comprise a first counting signal and a second counting signal. In a period of the square wave signal, when the square wave signal is at a first level (for example, a high level), the counting circuit counts a state where the frequency multiplication signal is at the first level (for example, the high level) to obtain a first count signal. The counting circuit also counts a state in which the frequency-multiplied signal is at a first level (e.g., a high level) during a period of the square wave signal to obtain a second count signal. The counting period is the period of the square wave signal, and the state of the square wave signal corresponding to the starting point of counting by the counting circuit can be selected according to the requirement, and can be when the square wave signal is in a first state (such as high level) or when the square wave signal is in a second state (such as low level). The first count signal and the second count signal may be indicative of a duty cycle of the square wave signal. In addition, the phase-locked loop performs 2^ N frequency multiplication according to the square wave signal f0 so as to generate a frequency multiplication signal f1, and the counting circuit can be an N-bit counter. The phase-locked loop comprises a voltage-controlled oscillator, and the phase-locked loop adjusts the frequency output of the voltage-controlled oscillator by judging the difference between the second counting signal and 2^ N. When the phase-locked loop is in a steady state, the frequency multiplication signal f1 output by the voltage-controlled oscillator is f0 ^ 2^ N. In another embodiment, the duty cycle sampling circuit includes a phase-locked loop, a counting circuit, and a digital-to-analog conversion circuit, an input end of the digital-to-analog conversion circuit is coupled to an output end of the counting circuit, the digital-to-analog conversion circuit is configured to perform digital-to-analog conversion according to the first counting signal and the second counting signal to generate a duty cycle characterizing signal characterizing the duty cycle of the square wave signal, and the duty cycle characterizing signal is an analog signal. The duty ratio characterization signal can be a direct current voltage signal or a direct current signal, and the duty ratio characterization signal obtained based on the above method has the advantages of high duty ratio characterization precision, low scheme implementation cost, high response speed and no ripple influence.
The embodiment of the invention also discloses an LED driving circuit, which comprises a driving control circuit and an LED load, wherein the output end of the driving control circuit is coupled with the LED load, and the driving control circuit is used for driving the LED load to work. The drive control circuit comprises a duty cycle sampling circuit as described in any of the above. The duty ratio sampling circuit can effectively improve the duty ratio sampling precision, thereby improving the control precision of the LED drive circuit.
An embodiment of the present invention further discloses a duty cycle sampling method, as shown in fig. 4, the duty cycle sampling method includes the following steps:
step S100, receiving a square wave signal, and performing frequency multiplication processing according to the square wave signal to generate a frequency multiplication signal; and
and S200, counting according to the square wave signal and the frequency multiplication signal and outputting a counting signal, wherein the counting signal is used for representing the duty ratio of the square wave signal.
In an embodiment of the invention, the phase-locked loop receives a square wave signal and performs frequency multiplication processing according to the square wave signal to generate a frequency multiplication signal. The counting circuit counts according to the square wave signal and the frequency multiplication signal and outputs a counting signal, and the counting signal can represent the duty ratio of the square wave signal. In a particular embodiment, the count signal includes a first count signal and a second count signal. The counting circuit counts according to the square wave signal and the frequency multiplication signal, and specifically comprises the following steps: the frequency doubling signal is counted during a period of the square wave signal when the square wave signal is at a first level to obtain a first count signal, and the frequency doubling signal is counted during the period of the square wave signal to obtain a second count signal. The first count signal and the second count signal are used for representing the duty ratio of the square wave signal. In one embodiment, the duty cycle of the square wave signal is equal to D1/D2. In another embodiment, the duty cycle of the square wave signal is equal to 1- (D1/D2). Wherein D1 is the first count signal, and D2 is the second count signal.
In another embodiment of the present invention, the duty cycle sampling method further includes: the digital-to-analog conversion circuit performs digital-to-analog conversion according to the first counting signal and the second counting signal to generate a direct current voltage signal or a direct current signal representing the duty ratio of the square wave signal.
In an embodiment of the invention, the phase-locked loop performs 2^ N frequency multiplication according to the square wave signal so as to generate a frequency multiplication signal, the frequency of the square wave signal multiplied by 2^ N is the same order of magnitude or similar order of magnitude with the frequency of the frequency multiplication signal, and 2^ N is the N power of 2. The counting circuit for counting is an N-bit counter, wherein N is a positive integer.
The invention provides a duty ratio sampling circuit, a duty ratio sampling method and an LED driving circuit, wherein the duty ratio sampling circuit comprises a phase-locked loop and a counting circuit. The input end of the phase-locked loop is used for receiving the square wave signal, and the phase-locked loop is used for carrying out frequency multiplication processing according to the square wave signal so as to generate a frequency multiplication signal. The first input end of the counting circuit is coupled with the output end of the phase-locked loop to receive the frequency multiplication signal, the second input end of the counting circuit is used for receiving the square wave signal, the counting circuit is used for counting according to the square wave signal and the frequency multiplication signal and outputting a counting signal, and the counting signal is used for representing the duty ratio of the square wave signal. In addition, the duty cycle sampling method includes: receiving the square wave signal, and performing frequency multiplication processing according to the square wave signal so as to generate a frequency multiplication signal; and counting according to the square wave signal and the frequency multiplication signal and outputting a counting signal, wherein the counting signal is used for representing the duty ratio of the square wave signal.
The invention does not need a filter circuit, can realize duty cycle sampling of the square wave signal through full digit, has lower cost, and particularly obtains the duty cycle of the low-frequency square wave signal. In addition, the digital-to-analog conversion circuit outputs a direct current voltage signal or a direct current signal representing the duty ratio of the square wave signal according to the counting signal, and the direct current voltage signal or the direct current signal is a pure direct current signal and has no ripple influence. In addition, the duty ratio sampling mode of the invention has high response speed, and after the phase-locked loop is stabilized, the direct current voltage signal or the direct current signal output by the digital-to-analog conversion circuit can be ensured to change one by one along with the duty ratio of the square wave signal by taking the period of the input square wave signal as a unit. In addition, the counting signal output by the N-bit counter is only related to the duty ratio of the input square wave signal, the amplitude of the direct current voltage signal or the direct current signal output by the digital-to-analog conversion circuit is defined by the N-bit digital-to-analog conversion circuit, and errors caused by mismatching of the high level and the low level of the input square wave signal and the reference voltage of the detection circuit are avoided. According to the duty ratio sampling circuit, the duty ratio sampling method and the LED driving circuit, the duty ratio information of the square wave signal is obtained in a digital quantization mode, the representation precision of the duty ratio is high, the scheme implementation cost is low, the response speed is high, and no ripple wave influence exists.
The above description and applications of the invention herein are illustrative and are not intended to limit the scope of the invention to the above described embodiments. The descriptions related to the effects or advantages mentioned in the embodiments may not be reflected in the experimental examples due to the uncertainty of the specific condition parameters, and are not used for limiting the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.
Claims (13)
1. A duty cycle sampling circuit, comprising:
the input end of the phase-locked loop is used for receiving a square wave signal and carrying out frequency multiplication processing according to the square wave signal to generate a frequency multiplication signal; and
and the counting circuit is coupled with the phase-locked loop at a first input end, is used for receiving the square wave signal at a second input end, and is used for counting according to the square wave signal and the frequency doubling signal and outputting a counting signal, wherein the counting signal is used for representing the duty ratio of the square wave signal.
2. The duty cycle sampling circuit of claim 1, wherein the count signal comprises a first count signal and a second count signal; counting the frequency-doubled signal when the square wave signal is at a first level during a period of the square wave signal to obtain a first count signal, and counting the frequency-doubled signal during the period of the square wave signal to obtain a second count signal.
3. The duty cycle sampling circuit of claim 1, wherein the counting circuit comprises a clock signal input coupled to a frequency multiplied signal output of the phase locked loop and an enable to receive the square wave signal.
4. The duty cycle sampling circuit of claim 1, wherein the duty cycle sampling circuit further comprises:
and the input end of the digital-to-analog conversion circuit is coupled with the output end of the counting circuit and is used for performing digital-to-analog conversion according to the counting signal and outputting a duty ratio characterization signal, and the duty ratio characterization signal characterizes the duty ratio of the square wave signal.
5. The duty cycle sampling circuit of claim 1, wherein the phase locked loop comprises:
a phase discriminator, the first input end of which is used for receiving the square wave signal;
the input end of the low-pass filter is coupled with the output end of the phase discriminator;
the input end of the voltage-controlled oscillator is coupled with the output end of the low-pass filter and is used for outputting the frequency multiplication signal; and
and the input end of the frequency divider is coupled with the output end of the voltage-controlled oscillator, and the output end of the frequency divider is coupled with the second input end of the phase discriminator.
6. The duty cycle sampling circuit of claim 1, wherein the phase locked loop performs a power-of-N multiplication process of 2 according to the square wave signal to generate a multiplied signal, and the counting circuit is an N-bit counter; wherein N is a positive integer.
7. The duty cycle sampling circuit of claim 2, wherein the duty cycle of the square wave signal is equal to D1/D2, or the duty cycle of the square wave signal is equal to 1- (D1/D2); wherein D1 is the first count signal, and D2 is the second count signal.
8. The duty cycle sampling circuit of claim 4, wherein the duty cycle characterization signal is a DC voltage signal or a DC current signal.
9. An LED driving circuit, comprising a driving control circuit and an LED load, wherein the driving control circuit comprises the duty cycle sampling circuit according to any one of claims 1 to 8.
10. A duty cycle sampling method, characterized in that the duty cycle sampling method comprises:
receiving a square wave signal, and performing frequency multiplication processing according to the square wave signal to generate a frequency multiplication signal; and
counting according to the square wave signal and the frequency doubling signal and outputting a counting signal, wherein the counting signal is used for representing the duty ratio of the square wave signal.
11. The duty cycle sampling method of claim 10, wherein the count signal includes a first count signal and a second count signal; the step of counting according to the square wave signal and the frequency multiplication signal specifically comprises:
counting the frequency-doubled signal when the square wave signal is at a first level during a period of the square wave signal to obtain a first count signal, and counting the frequency-doubled signal during the period of the square wave signal to obtain a second count signal.
12. The duty cycle sampling method of claim 10, further comprising:
and performing digital-to-analog conversion according to the counting signal to generate a direct current voltage signal or a direct current signal representing the duty ratio of the square wave signal.
13. The duty cycle sampling method of claim 10, further comprising:
carrying out N power frequency multiplication processing of 2 according to the square wave signal to generate a frequency multiplication signal, wherein a counting circuit for counting is an N-bit counter; wherein N is a positive integer.
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