CN104702277A - Phase-locked loop circuit - Google Patents
Phase-locked loop circuit Download PDFInfo
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- CN104702277A CN104702277A CN201310670184.8A CN201310670184A CN104702277A CN 104702277 A CN104702277 A CN 104702277A CN 201310670184 A CN201310670184 A CN 201310670184A CN 104702277 A CN104702277 A CN 104702277A
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Abstract
A phase-locked loop circuit comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider and a frequency doubler. The frequency doubler is suitable for performing frequency doubling on input signals to generate frequency doubling signals, frequency of the frequency doubling signals is larger than that of the input signals, and the phase frequency detector is suitable for detecting phase difference between the frequency doubling signals and frequency dividing signals generated by the frequency divider to generate error voltage signals in direct proportion to the phase difference. Noise of the whole phase-locked loop circuit can be lowered by performing frequency doubling on the input signals.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of phase-locked loop circuit.
Background technology
Phase-locked loop (PLL, Phase-locked loops) circuit be a kind of utilize feedback control principle to realize frequency and the simultaneous techniques of phase place, its effect is that the output signal of circuit is kept synchronous with the reference signal of its outside.When the frequency of reference signal or phase place change, phase-locked loop circuit can detect this change, and comes frequency or the phase place of regulation output signal by the reponse system of its inside, until both re-synchronizations.
Based in the frequency synthesizer of phase-locked loop circuit, frequency divider is a very important module, and it is that frequency synthesizer can provide multiple high accuracy frequency signal and realize key and the prerequisite of high-frequency and low-consumption work simultaneously.The proposition of Fractional Frequency-Dividing Technology, has broken the restriction relation between frequency synthesizer loop bandwidth and channel spacing, makes it have that frequency error factor speed is fast, precision advantages of higher.So-called fractional frequency division, be also sometimes referred to as fraction division, namely the divider ratio of frequency divider is a fractional value.
Fig. 1 is the structural representation of the phase-locked loop circuit of common a kind of fractional frequency division.With reference to figure 1, described phase-locked loop circuit comprises phase frequency detector (PFD, Phase Frequency Detector) 11, charge pump 12, loop filter (LPF, Loop Filter) 13, voltage controlled oscillator (VCO, Voltage ControlledOscillator) 14 and frequency divider 15.
Described phase frequency detector 11 is suitable for the phase difference detecting input signal Vin and fractional frequency signal Vdiv, and exports the error voltage signal be directly proportional to described phase difference; Described charge pump 12 is suitable for the charging and discharging currents described error voltage signal being converted into loop; Described loop filter 13 is suitable for the radio-frequency component that charge pump 12 described in filtering exports, and suppresses voltage ripple, under the control of described charging and discharging currents, exports control voltage Vc; Described voltage controlled oscillator 14 is suitable for the output signal Vout that generation frequency is directly proportional to described control voltage Vc, the relation of the described output signal frequency Fout of Vout and described control voltage Vc is as follows: Fout=F0+Kvco*Vc, F0 is the frequency of described control voltage Vc described output signal Vout when equalling zero, be also referred to as the free oscillation frequency of described voltage controlled oscillator 14, Kvco is the gain of described voltage controlled oscillator 14; Described frequency divider 15 is suitable for carrying out fractional frequency division to described output signal Vout, produces described fractional frequency signal Vdiv.
Phase-locked loop circuit each several part shown in Fig. 1 is all a noise source, and especially described frequency divider 15 can produce larger quantizing noise when carrying out fractional frequency division.The existence of noise makes seizure performance, the linearity tracking degradation of loop, and make the phase place of described output signal Vout produce randomized jitter, frequency spectrum is impure, can destroy the normal work of loop time serious completely.Therefore, the noise how reducing the phase-locked loop circuit shown in Fig. 1 is a problem demanding prompt solution.
Summary of the invention
What the present invention solved is the problem that the phase-locked loop circuit noise of existing fractional frequency division is larger.
For solving the problem, the invention provides a kind of phase-locked loop circuit, comprising phase frequency detector, charge pump, loop filter, voltage controlled oscillator and frequency divider, also comprising frequency multiplier;
Described frequency multiplier is suitable for carrying out process of frequency multiplication to produce frequency-doubled signal to input signal, and the frequency of described frequency-doubled signal is greater than the frequency of described input signal;
Described phase frequency detector is suitable for detecting the phase difference of the fractional frequency signal that described frequency-doubled signal produces to described frequency divider to produce the error voltage signal be directly proportional to described phase difference.
Optionally, the frequency of described frequency-doubled signal is the twice of the frequency of described input signal.
Optionally, described frequency multiplier comprises delay circuit and same or logical circuit;
Described delay circuit is suitable for carrying out delay process to produce the time delayed signal lagging behind described input signal to described input signal;
Described with or logical circuit be suitable for described input signal and described time delayed signal carry out with or logical process to produce described frequency-doubled signal.
Optionally, described time delayed signal lags behind the time of described input signal is 1/4th of the cycle of described input signal.
Optionally, described charge pump is suitable for the charging and discharging currents described error voltage signal being converted into loop;
Described loop filter is suitable for exporting control voltage under the control of described charging and discharging currents;
Described voltage controlled oscillator is suitable for the output signal that generation frequency is directly proportional to described control voltage;
Described frequency divider is suitable for carrying out scaling down processing to produce described fractional frequency signal to described output signal.
Optionally, described frequency divider is suitable for carrying out fractional frequency division process to described output signal.
Optionally, described phase-locked loop circuit also comprises the reference frequency source being suitable for producing described input signal.
Compared with prior art, technical scheme of the present invention has the following advantages:
By increasing frequency multiplier, process of frequency multiplication being carried out to input signal, increase the frequency of the signal of input phase frequency detector, thus the frequency of the fractional frequency signal that frequency divider is produced increasing.Because the quantizing noise of described frequency divider and the frequency of described fractional frequency signal are Negative correlation, therefore, when the loop bandwidth of phase-locked loop circuit is constant, when the frequency of described fractional frequency signal increases, the quantizing noise of described frequency divider reduces.
Due to the loop effect of described phase-locked loop circuit, when being greater than described loop bandwidth, the loop noise with low-pass characteristic is suppressed by loop; When being less than described loop bandwidth, the loop noise with high pass characteristic is suppressed by loop.Thus, when low frequency, the loop noise in the noise of described phase-locked loop circuit with low-pass characteristic plays a leading role; And when high frequency, the loop noise in the noise of described phase-locked loop circuit with high pass characteristic plays a leading role.The quantizing noise of described frequency divider belongs to the loop noise of low-pass characteristic, the noise of voltage controlled oscillator belongs to high-frequency noise, therefore, adopt the phase-locked loop circuit that technical solution of the present invention provides, can described loop bandwidth be selected larger, to obtain the noise of good voltage controlled oscillator, thus reduce the noise of whole phase-locked loop circuit.
In possibility of the present invention, described frequency multiplier carries out twice process of frequency multiplication to described input signal, and the circuit of described frequency multiplier is simple, and be easy to realize, cost is lower.
Accompanying drawing explanation
Fig. 1 is the structural representation of the phase-locked loop circuit of common a kind of fractional frequency division;
Fig. 2 is the phase noise curve synoptic diagram of the frequency divider shown in Fig. 1;
Fig. 3 is the structural representation of the phase-locked loop circuit of embodiment of the present invention;
Fig. 4 is the phase noise curve comparison schematic diagram of the frequency divider of the present invention and prior art;
Fig. 5 is the phase noise curve synoptic diagram of the voltage controlled oscillator of embodiment of the present invention;
Fig. 6 is the electrical block diagram of the frequency multiplier of the embodiment of the present invention;
Fig. 7 is the signal waveform schematic diagram of the frequency multiplier shown in Fig. 6.
Embodiment
In the phase-locked loop circuit of fractional frequency division, frequency divider is primarily of sigma-delta modulator and integer frequency divider composition.Sigma-delta modulator produces the frequency dividing ratio that pseudorandom bigit sequence dynamically changes integer frequency divider, makes its mean value be decimal.Actual frequency dividing ratio always departs from required fractional frequency division ratio, thus there is quantization error.Quantization error in sigma-delta modulator can cause the quantizing noise of low pass and reduce the phase noise performance of phase-locked loop circuit.
For the phase-locked loop circuit of the fractional frequency division shown in Fig. 1, Fig. 2 shows the phase noise curve of described frequency divider 15.Due to the loop effect of phase-locked loop circuit, and the quantizing noise of described frequency divider 15 has low-pass characteristic, and therefore, when being greater than the loop bandwidth of described phase-locked loop circuit, the quantizing noise of described frequency divider 15 is suppressed by loop.With reference to figure 2, dotted line L21 is not by the phase noise that loop suppresses, the phase noise that solid line L22 is suppressed by loop.
For suppressing the quantizing noise of described frequency divider 15, usually there are two kinds of methods: one is the loop filter that can use more high-order; Two is the loop bandwidths reducing described phase-locked loop circuit.The exponent number of practical application loop filter generally more than 3, because the higher phase margin of exponent number is lower, can not may causes loop unstable, limit the application of first method.And second method has run counter to the original intention utilizing fractional frequency division to improve the loop bandwidth of described phase-locked loop circuit, also inapplicable.Technical solution of the present invention provides a kind of phase-locked loop circuit, is reduced the quantizing noise of frequency divider by the frequency increasing the fractional frequency signal that frequency divider exports.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 3 is the structural representation of the phase-locked loop circuit of embodiment of the present invention.With reference to figure 3, described phase-locked loop circuit comprises frequency multiplier 20, phase frequency detector 21, charge pump 22, loop filter 23, voltage controlled oscillator 24 and frequency divider 25.
Particularly, described frequency multiplier 20 is suitable for carrying out process of frequency multiplication to produce frequency-doubled signal Vfm to input signal Vin, and the frequency of described frequency-doubled signal Vfm is greater than the frequency of described input signal Vin.The frequency of described input signal Vin is the reference frequency of described phase-locked loop circuit, the frequency of described input signal Vin is amplified by described frequency multiplier 20, if the frequency of described input signal Vin is Fr, then the frequency of described frequency-doubled signal Vfm is n*Fr, n > 1, n is frequency multiplication number of times.
Described phase frequency detector 21 is suitable for detecting the phase difference of the fractional frequency signal Vdiv that described frequency-doubled signal Vfm produces to described frequency divider 25 to produce the error voltage signal be directly proportional to described phase difference.Different from phase-locked loop circuit of the prior art, the phase difference of what phase frequency detector 21 in the phase-locked loop circuit of technical solution of the present invention detected is described frequency-doubled signal Vfm and described fractional frequency signal Vdiv.
When phase-locked loop circuit is started working, if the frequency of described fractional frequency signal Vdiv is away from the frequency of described frequency-doubled signal Vfm, described phase frequency detector 21 and the collaborative work of described charge pump 22, change the control voltage Vc of described voltage controlled oscillator 24, the frequency of frequency-doubled signal Vfm described in the frequency approaches making described fractional frequency signal Vdiv.When the frequency of described fractional frequency signal Vdiv and described frequency-doubled signal Vfm frequency enough close to time, described phase frequency detector 21, just as phase discriminator, carries out the phase compare of described fractional frequency signal Vdiv and described frequency-doubled signal Vfm.The physical circuit of described phase frequency detector 21 has multiple implementation, does not repeat them here.
Described charge pump 22 is suitable for the charging and discharging currents described error voltage signal being converted into loop, belongs to transconductance circuit, is also the interface of digital circuit and analog circuit.Usually, described charge pump 22 is made up of the current source of two belt switches controlled by described error voltage signal, and two current sources provide charging current and discharging current respectively.When providing switch corresponding to the current source of charging current to close, the 22 pairs of phase-locked loop circuit chargings of described charge pump; When providing switch corresponding to the current source of discharging current to close, the 22 pairs of phase-locked loop circuit electric discharges of described charge pump.
Described loop filter 23 is suitable under the control of described charging and discharging currents, export described control voltage Vc.Filter can be divided into active filter and passive filter, considers that active filter is comparatively complicated, and described loop filter 23 adopts passive filter to realize loop filtering usually, and passive filter generally all adopts Order RC network.Radio-frequency component in the described charging and discharging currents of described loop filter 23 filtering, suppresses voltage ripple, described charging and discharging currents is converted into described control voltage Vc.
Described voltage controlled oscillator 24 is suitable for the output signal Vout that generation frequency is directly proportional to described control voltage Vc, the relation of the described output signal frequency Fout of Vout and described control voltage Vc is as follows: Fout=F0+Kvco*Vc, F0 is the frequency of described control voltage Vc described output signal Vout when equalling zero, be also referred to as the free oscillation frequency of described voltage controlled oscillator 14, Kvco is the gain of described voltage controlled oscillator 14.Described voltage controlled oscillator 24 can be LC oscillator, ring oscillator or other forms of oscillator, and the present invention is not construed as limiting this.
Described frequency divider 25 is suitable for carrying out scaling down processing to produce described fractional frequency signal Vdiv to described output signal Vout.The frequency of described output signal Vout is generally the several times of the frequency of described input signal Vin, therefore, need described frequency divider 25 to carry out frequency division to described output signal Vout, then the fractional frequency signal Vdiv obtained after frequency division and described frequency-doubled signal Vfm is compared.
When described output signal Vout is through M frequency division, M is divider ratio, and after the Phase synchronization of its phase place and described input signal Vin, described control voltage Vc stablizes, whole phase-locked loop circuit locking.During locking, the frequency * M of the frequency=described frequency-doubled signal Vfm of described output signal Vout.In embodiments of the present invention, described frequency divider 24 carries out fractional frequency division process to described output signal Vout, and therefore, divider ratio M is decimal.
It should be noted that, in other embodiments, described phase-locked loop circuit can also comprise reference frequency source, and described reference frequency source is suitable for producing described input signal Vin.
Carry out process of frequency multiplication by described frequency multiplier 20 to described input signal Vin in technical solution of the present invention, increase the frequency of the signal inputting described phase frequency detector 21, therefore, the frequency of described fractional frequency signal Vdiv also increases thereupon.Because the quantizing noise of described frequency divider 25 is Negative correlation with the frequency of described fractional frequency signal Vdiv, namely the frequency of described fractional frequency signal Vdiv is larger, and the quantizing noise of described frequency divider 25 is less.Therefore, when the loop bandwidth of described phase-locked loop circuit is constant, technical solution of the present invention reduces the quantizing noise of described frequency divider 25.
Fig. 4 is the phase noise curve comparison schematic diagram of the frequency divider of the present invention and prior art.With reference to figure 4, dotted line L21 is not by the phase noise that loop suppresses in prior art, and solid line L22 is by the phase noise that loop suppresses in prior art, and dotted line L41 is not by phase noise that loop suppresses in the technical program.As can be seen from Figure 4, described dotted line L41 is shifted downwards relative to described dotted line L21, and through the loop inhibitory action of described phase-locked loop circuit, the quantizing noise of frequency divider 25 described in technical solution of the present invention reduces.
The quantizing noise of described frequency divider 25 is main sources for phase-locked loop circuit noise, and another main source of described phase-locked loop circuit noise is the noise of described voltage controlled oscillator 24.Fig. 5 shows the phase noise curve of described voltage controlled oscillator 24.Due to the loop effect of phase-locked loop circuit, and the noise of described voltage controlled oscillator 24 has high pass characteristic, and therefore, when being less than the loop bandwidth of described phase-locked loop circuit, the noise of described voltage controlled oscillator 24 is suppressed by loop.With reference to figure 5, dotted line L51 is not by the phase noise that loop suppresses, the phase noise that solid line L52 is suppressed by loop.
Based on above-mentioned analysis, due to the loop effect of described phase-locked loop circuit, when being greater than described loop bandwidth, the quantizing noise of described frequency divider 25 is suppressed by loop, and the noise of described phase-locked loop circuit is played a leading role by the noise of described voltage controlled oscillator 24; When being less than described loop bandwidth, the noise of described voltage controlled oscillator 24 is suppressed by loop, and the noise of described phase-locked loop circuit is played a leading role by the quantizing noise of described frequency divider 25.Therefore, the phase-locked loop circuit adopting technical solution of the present invention to provide, can select larger by the loop bandwidth of phase-locked loop circuit, to reduce the noise of described voltage controlled oscillator 24, thus reduce the noise of whole phase-locked loop circuit.
It should be noted that, the frequency multiplication frequency n of described frequency multiplier 20 can set according to practical application request.In embodiments of the present invention, get n=2, namely carry out twice process of frequency multiplication to described input signal Vin, the frequency of the frequency-doubled signal Vfm of acquisition is the twice of the frequency of described input signal Vin.Correspondingly, the embodiment of the present invention provides a kind of frequency multiplication number of times to be the frequency multiplier of 2.The electrical block diagram of Fig. 6 to be described frequency multiplication number of times be frequency multiplier of 2.With reference to figure 2, described frequency multiplier comprises delay circuit 61 and same or logical circuit 62.
Described delay circuit 61 is suitable for carrying out delay process to produce the time delayed signal Vin ' lagging behind described input signal Vin to described input signal Vin.The time that described time delayed signal Vin ' lags behind described input signal Vin is 1/4th of the cycle of described input signal Vin.Described delay circuit 61 can adopt RC delay circuit structure or other there is the circuit structure of delay function, the present invention is not construed as limiting this.
Described with or logical circuit 62 be suitable for described input signal Vin and described time delayed signal Vin ' carry out with or logical process to produce described frequency-doubled signal Vfm.
Fig. 7 is the signal waveform schematic diagram of the frequency multiplier shown in Fig. 6.With reference to figure 7, the frequency of described time delayed signal Vin ' is identical with the frequency of described input signal Vin, and the time that described time delayed signal Vin ' lags behind described input signal Vin is Δ T, and Δ T equals 1/4th cycles of described input signal Vin.Frequency multiplier shown in Fig. 6 carries out twice process of frequency multiplication to described input signal Vin, and the circuit of described frequency multiplier is simple, and be easy to realize, cost is lower.
In sum, the phase-locked loop circuit that technical solution of the present invention provides, can select larger by loop bandwidth, thus reduce the noise of whole phase-locked loop circuit.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (7)
1. a phase-locked loop circuit, comprises phase frequency detector, charge pump, loop filter, voltage controlled oscillator and frequency divider, it is characterized in that, also comprise frequency multiplier;
Described frequency multiplier is suitable for carrying out process of frequency multiplication to produce frequency-doubled signal to input signal, and the frequency of described frequency-doubled signal is greater than the frequency of described input signal;
Described phase frequency detector is suitable for detecting the phase difference of the fractional frequency signal that described frequency-doubled signal produces to described frequency divider to produce the error voltage signal be directly proportional to described phase difference.
2. phase-locked loop circuit as claimed in claim 1, it is characterized in that, the frequency of described frequency-doubled signal is the twice of the frequency of described input signal.
3. phase-locked loop circuit as claimed in claim 2, is characterized in that, described frequency multiplier comprises delay circuit and same or logical circuit;
Described delay circuit is suitable for carrying out delay process to produce the time delayed signal lagging behind described input signal to described input signal;
Described with or logical circuit be suitable for described input signal and described time delayed signal carry out with or logical process to produce described frequency-doubled signal.
4. phase-locked loop circuit as claimed in claim 3, it is characterized in that, the time that described time delayed signal lags behind described input signal is 1/4th of the cycle of described input signal.
5. phase-locked loop circuit as claimed in claim 1, it is characterized in that, described charge pump is suitable for the charging and discharging currents described error voltage signal being converted into loop;
Described loop filter is suitable for exporting control voltage under the control of described charging and discharging currents;
Described voltage controlled oscillator is suitable for the output signal that generation frequency is directly proportional to described control voltage;
Described frequency divider is suitable for carrying out scaling down processing to produce described fractional frequency signal to described output signal.
6. phase-locked loop circuit as claimed in claim 5, it is characterized in that, described frequency divider is suitable for carrying out fractional frequency division process to described output signal.
7. phase-locked loop circuit as claimed in claim 1, is characterized in that, also comprise the reference frequency source being suitable for producing described input signal.
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| CN201310670184.8A CN104702277A (en) | 2013-12-10 | 2013-12-10 | Phase-locked loop circuit |
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| CN201310670184.8A CN104702277A (en) | 2013-12-10 | 2013-12-10 | Phase-locked loop circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107562119A (en) * | 2016-09-21 | 2018-01-09 | 晨星半导体股份有限公司 | Eye diagram measurement device and its clock data recovery system, method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6005443A (en) * | 1998-03-19 | 1999-12-21 | Conexant Systems, Inc. | Phase locked loop frequency synthesizer for multi-band application |
| CN103269215A (en) * | 2013-06-03 | 2013-08-28 | 上海宏力半导体制造有限公司 | Frequency multiplier circuit |
| CN103378855A (en) * | 2012-04-30 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Phase-locked loop with frequency multiplier and method for forming the phase-locked loop |
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2013
- 2013-12-10 CN CN201310670184.8A patent/CN104702277A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6005443A (en) * | 1998-03-19 | 1999-12-21 | Conexant Systems, Inc. | Phase locked loop frequency synthesizer for multi-band application |
| CN103378855A (en) * | 2012-04-30 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Phase-locked loop with frequency multiplier and method for forming the phase-locked loop |
| CN103269215A (en) * | 2013-06-03 | 2013-08-28 | 上海宏力半导体制造有限公司 | Frequency multiplier circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107562119A (en) * | 2016-09-21 | 2018-01-09 | 晨星半导体股份有限公司 | Eye diagram measurement device and its clock data recovery system, method |
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