CN103269215A - Frequency multiplier circuit - Google Patents
Frequency multiplier circuit Download PDFInfo
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- CN103269215A CN103269215A CN2013102179721A CN201310217972A CN103269215A CN 103269215 A CN103269215 A CN 103269215A CN 2013102179721 A CN2013102179721 A CN 2013102179721A CN 201310217972 A CN201310217972 A CN 201310217972A CN 103269215 A CN103269215 A CN 103269215A
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Abstract
The invention discloses a frequency multiplier circuit which at least comprises a frequency multiplier module and a duty ratio voltage generating module, wherein the frequency multiplier module is used for receiving an input signal and realizing the frequency multiplier of the input signal; and the duty ratio voltage generating module is used for receiving the signal subjected to frequency multiplier, integrating the frequency multiplier signal to obtain a direct current component so as to control the duty ratio of the frequency multiplier module. According to the frequency multiplier circuit, clock signals of frequency multiplier for multiplying 2, 4 and the like can be easily obtained, and the circuit design is simplified.
Description
Technical field
The present invention particularly relates to a kind of frequency multiplier circuit that comparatively is easy to generate the frequency doubling clock signal about a kind of frequency multiplier circuit.
Background technology
In a lot of the application, often need clock signals of different frequencies, especially need to have the clock signal of multiple relation, as except 2, except 4 ... or take advantage of 2, take advantage of the clock signal of relations such as 4..., yet, in the prior art, except 2, except 4... isochronon signal is easy to produce, take advantage of 2, though take advantage of 4... isochronon signal to have a lot of ways to produce, but all comparatively complicated, be difficult for realizing.
Summary of the invention
For overcoming the problem that above-mentioned prior art exists, main purpose of the present invention is to provide a kind of frequency multiplier circuit, and it can relatively easily obtain to take advantage of 2, takes advantage of the clock signal of frequencys multiplication such as 4..., has simplified circuit design.
For reaching above-mentioned and other purpose, the invention provides a kind of frequency multiplier circuit, comprise at least:
Times frequency module receives input signal and realizes frequency multiplication to this input signal; And
The duty ratio voltage generating module, the signal after the reception frequency multiplication carries out integration to frequency-doubled signal and obtains its DC component to control the duty ratio of this times frequency module.
Further, this times frequency module comprises controllable delay and gate, this controllable delay is used for this input signal is finished 1/4 cycle delay, and the signal after the delay and this input signal are sent to two inputs of this gate, through realizing the frequency multiplication to this input signal after the gate.
Further, this duty ratio voltage generating module comprises integrating circuit, and this frequency-doubled signal is sent to the first input end of this integrating circuit, and another input of this integrating circuit receives reference voltage, this controllable delay of output termination of this integrating circuit.
Further, this gate is XOR gate.
Further, this frequency-doubled signal is sent to the inverting input of this integrating circuit, and the in-phase input end of this integrating circuit connects reference voltage.
Further, when the high level of this frequency-doubled signal is longer, this integrating circuit output reduces, the time-delay of this controllable delay reduced until 1/4 cycle that equals this input signal, when the high level of this frequency-doubled signal more in short-term, this integrating circuit output raises, this controllable delay time-delay increased until 1/4 cycle that equals this input signal, when the high level of this frequency-doubled signal equated with low level time, this integrating circuit output was constant, and this controllable delay time-delay is constant to be 1/4 cycle of this input signal
Further, this integrating circuit comprises integrating resistor, integrating capacitor and operational amplifier, this this frequency-doubled signal of integrating resistor one termination wherein, this operational amplifier negative input end of another termination, this this reference voltage of operational amplifier positive input termination, output connects this integrating resistor by this integrating capacitor, and simultaneously, output also is connected in this controllable delay.
Further, this gate is same or door, and its output is connected to the in-phase input end of this integrating circuit, and the inverting input of this integrating circuit connects reference voltage.
Further, the output in this times frequency module carries out the cascade of N level, acquisition 2N frequency doubling clock signal.
Compared with prior art, a kind of frequency multiplier circuit of the present invention carries out frequency multiplication by times frequency module to input signal, utilize the duty ratio voltage generating module that frequency-doubled signal is carried out integration and obtain its DC component with the duty ratio of control times frequency module, realized relatively easily obtaining to take advantage of 2, take advantage of the purpose of the clock signal of frequencys multiplication such as 4..., simplified circuit design.
Description of drawings
Fig. 1 is the circuit diagram of the preferred embodiment of a kind of frequency multiplier circuit of the present invention;
Fig. 2 is the sequential schematic diagram of preferred embodiment of the present invention.
Embodiment
Below by specific instantiation and accompanying drawings embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification discloses.The present invention also can be implemented or be used by other different instantiation, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications and change under the spirit of the present invention not deviating from.
Fig. 1 is the circuit diagram of the preferred embodiment of a kind of frequency multiplier circuit of the present invention.As shown in Figure 1, a kind of frequency multiplier circuit of the present invention comprises times frequency module 10 and duty ratio voltage generating module 11, and wherein times frequency module 10 reception input signal CKIN and realization are to the frequency multiplication of input signal CKIN; Duty ratio voltage generating module 11 receives the signal CK_X after the frequency multiplication, frequency-doubled signal CK_X is carried out integration obtain its DC component with the duty ratio of control times frequency module 10.
Wherein, in preferred embodiment of the present invention, times frequency module comprises controllable delay 101 and gate 102, controllable delay 101 is used for input signal CKIN is finished the time-delay of 1/4 cycle, signal CK_D0 after the delay and input signal CKIN are sent to two inputs of gate 102, in preferred embodiment of the present invention, gate 102 is XOR gate, so, the different CK_X that then exports of two inputs input is high level, importing the identical CK_X that then exports is low level, so just finishes the frequency multiplication to input signal CKIN; Duty ratio voltage generating module 11 comprises integrating circuit, frequency-doubled signal CK_X is sent to the inverting input of integrating circuit, the integrating circuit in-phase input end meets reference voltage V BIAS=1/2VDD, then when the high level of frequency-doubled signal CK_X is longer (duty ratio＞50%), integrating circuit output Vctl reduces, the controllable delay time-delay reduced until 1/4 cycle that equals input signal CKIN, when the high level of frequency-doubled signal CK_X (duty ratio＜50%) more in short-term, integrating circuit output Vctl raises, the controllable delay time-delay increased until 1/4 cycle that equals input signal CKIN, when the high level of frequency-doubled signal CK_X equates with low level time (duty ratio=50%), Vctl is constant in integrating circuit output, the controllable delay time-delay is constant to be 1/4 cycle of input signal CKIN, and Fig. 2 then is the sequential chart of preferred embodiment of the present invention.In preferred embodiment of the present invention, integrating circuit comprises integrating resistor R0, integrating capacitor C0 and operational amplifier OP_AMP, integrating resistor R0 one termination frequency-doubled signal CK_X wherein, another termination operational amplifier OP_AMP negative input end, operational amplifier OP_AMP positive input termination reference voltage V BIAS, output meets integrating resistor R0 by integrating capacitor C0, and simultaneously, output also is connected in controllable delay 101.
As other real-time modes of the present invention, XOR gate 101 also can be used together or door reaches same purpose, but same or door output need be connected to the in-phase input end of integrating circuit, the inverting input of integrating circuit connects reference voltage, the slope that does not perhaps change the connection of integrator and change the controllable delay line also can, the present invention is not as limit.
Need to prove, though preferred embodiment of the present invention has provided the implementation of 2 frequency doubling clock signals, be not difficult to draw, only need utilize the present invention to carry out the cascade of N level, can obtain 2
NThe frequency doubling clock signal.
In sum, a kind of frequency multiplier circuit of the present invention carries out frequency multiplication by times frequency module to input signal, utilize the duty ratio voltage generating module that frequency-doubled signal is carried out integration and obtain its DC component with the duty ratio of control times frequency module, realized relatively easily obtaining to take advantage of 2, take advantage of the purpose of the clock signal of frequencys multiplication such as 4..., simplified circuit design.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not is used for restriction the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and above-described embodiment is modified and changed.Therefore, the scope of the present invention should be listed as claims.
Claims (9)
1. frequency multiplier circuit comprises at least:
Times frequency module receives input signal and realizes frequency multiplication to this input signal; And
The duty ratio voltage generating module, the signal after the reception frequency multiplication carries out integration to frequency-doubled signal and obtains its DC component to control the duty ratio of this times frequency module.
2. a kind of frequency multiplier circuit as claimed in claim 1, it is characterized in that: this times frequency module comprises controllable delay and gate, this controllable delay is used for this input signal is finished 1/4 cycle delay, signal after the delay and this input signal are sent to two inputs of this gate, through realizing the frequency multiplication to this input signal after the gate.
3. a kind of frequency multiplier circuit as claimed in claim 2, it is characterized in that: this duty ratio voltage generating module comprises integrating circuit, this frequency-doubled signal is sent to the first input end of this integrating circuit, another input of this integrating circuit receives reference voltage, this controllable delay of output termination of this integrating circuit.
4. a kind of frequency multiplier circuit as claimed in claim 3, it is characterized in that: this gate is XOR gate.
5. a kind of frequency multiplier circuit as claimed in claim 4, it is characterized in that: this frequency-doubled signal is sent to the inverting input of this integrating circuit, and the in-phase input end of this integrating circuit connects reference voltage.
6. a kind of frequency multiplier circuit as claimed in claim 5, it is characterized in that: when the high level of this frequency-doubled signal is longer, this integrating circuit output reduces, this controllable delay time-delay reduced until 1/4 cycle that equals this input signal, when the high level of this frequency-doubled signal more in short-term, this integrating circuit output raises, this controllable delay time-delay increased until 1/4 cycle that equals this input signal, when the high level of this frequency-doubled signal equates with low level time, this integrating circuit output is constant, and this controllable delay time-delay is constant to be 1/4 cycle of this input signal.
7. a kind of frequency multiplier circuit as claimed in claim 6, it is characterized in that: this integrating circuit comprises integrating resistor, integrating capacitor and operational amplifier, this this frequency-doubled signal of integrating resistor one termination wherein, this operational amplifier negative input end of another termination, this this reference voltage of operational amplifier positive input termination, output connects this integrating resistor by this integrating capacitor, and simultaneously, output also is connected in this controllable delay.
8. a kind of frequency multiplier circuit as claimed in claim 3 is characterized in that: this gate for or door, its output is connected to the in-phase input end of this integrating circuit, the inverting input of this integrating circuit connects reference voltage.
9. a kind of frequency multiplier circuit as claimed in claim 3, it is characterized in that: the output in this times frequency module carries out the cascade of N level, obtains 2
NThe frequency doubling clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102179721A CN103269215A (en) | 2013-06-03 | 2013-06-03 | Frequency multiplier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102179721A CN103269215A (en) | 2013-06-03 | 2013-06-03 | Frequency multiplier circuit |
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| CN103269215A true CN103269215A (en) | 2013-08-28 |
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| CN2013102179721A Pending CN103269215A (en) | 2013-06-03 | 2013-06-03 | Frequency multiplier circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104702277A (en) * | 2013-12-10 | 2015-06-10 | 展讯通信（上海）有限公司 | Phase-locked loop circuit |
| CN111904407A (en) * | 2020-09-14 | 2020-11-10 | 北京航空航天大学 | Heart rate signal processing device and heart rate detection device |
| CN114430271A (en) * | 2022-01-28 | 2022-05-03 | 北京奕斯伟计算技术有限公司 | Frequency divider, electronic device and frequency dividing method |
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| CN1547077A (en) * | 2003-12-09 | 2004-11-17 | A charging pulse generator, exposure generating device therefor, and charging pulse output method | |
| CN1574639A (en) * | 2003-05-23 | 2005-02-02 | 株式会社瑞萨科技 | Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit |
| CN101005277A (en) * | 2005-10-06 | 2007-07-25 | 飞思卡尔半导体公司 | Digital clock frequency multiplier |
| US20070223638A1 (en) * | 2004-05-12 | 2007-09-27 | Thine Electronics, Inc. | Isophase Multiphase Clock Signal Generation Circuit and Serial Digital Data Receiving Circuit Using the Same |
| CN102624360A (en) * | 2012-04-05 | 2012-08-01 | 四川和芯微电子股份有限公司 | Frequency multiplying circuit and system capable of automatically adjusting duty ratio of output signal |
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2013
- 2013-06-03 CN CN2013102179721A patent/CN103269215A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574639A (en) * | 2003-05-23 | 2005-02-02 | 株式会社瑞萨科技 | Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit |
| CN1547077A (en) * | 2003-12-09 | 2004-11-17 | A charging pulse generator, exposure generating device therefor, and charging pulse output method | |
| US20070223638A1 (en) * | 2004-05-12 | 2007-09-27 | Thine Electronics, Inc. | Isophase Multiphase Clock Signal Generation Circuit and Serial Digital Data Receiving Circuit Using the Same |
| CN101005277A (en) * | 2005-10-06 | 2007-07-25 | 飞思卡尔半导体公司 | Digital clock frequency multiplier |
| CN102624360A (en) * | 2012-04-05 | 2012-08-01 | 四川和芯微电子股份有限公司 | Frequency multiplying circuit and system capable of automatically adjusting duty ratio of output signal |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104702277A (en) * | 2013-12-10 | 2015-06-10 | 展讯通信（上海）有限公司 | Phase-locked loop circuit |
| CN111904407A (en) * | 2020-09-14 | 2020-11-10 | 北京航空航天大学 | Heart rate signal processing device and heart rate detection device |
| CN114430271A (en) * | 2022-01-28 | 2022-05-03 | 北京奕斯伟计算技术有限公司 | Frequency divider, electronic device and frequency dividing method |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
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Effective date of registration: 20140514 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20130828 |
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| RJ01 | Rejection of invention patent application after publication |