CN102938635A - Frequency multiplication circuit - Google Patents
Frequency multiplication circuit Download PDFInfo
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- CN102938635A CN102938635A CN2012104438209A CN201210443820A CN102938635A CN 102938635 A CN102938635 A CN 102938635A CN 2012104438209 A CN2012104438209 A CN 2012104438209A CN 201210443820 A CN201210443820 A CN 201210443820A CN 102938635 A CN102938635 A CN 102938635A
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Abstract
An embodiment of the invention discloses a frequency multiplication circuit. The circuit comprises a delay module, a logical operation module, a reference voltage generation module and a feedback control module, wherein the delay module receives delay control voltage output by an input clock signal and the feedback control module, performs delay processing on the input clock signal according to the delay control voltage, and outputs a delay clock signal; the logical operation module performs logical xor or xnor calculation on the input clock signal and the delay clock signal to obtain a frequency multiplication clock signal and outputs the signal to the feedback control module; the reference voltage generation module generates a reference voltage directly proportional to a supply voltage and outputs the voltage to the feedback control module; and the feedback control module amplifies the difference between the average voltage of the frequency multiplication clock signal and the reference voltage to obtain the delay control voltage and outputs the voltage to the delay module. According to the embodiment, frequency multiplication of clock signals can be achieved at low power consumption and a small area, and a duty cycle of output clock signals can be controlled accurately.
Description
Technical field
The present invention relates to communication technical field, particularly relate to a kind of frequency multiplier circuit.
Background technology
Frequency multiplier circuit (Frequency-Doubler) is used for the frequency of input clock signal is double, thereby improves the frequency of input clock signal.In integrated circuit (IC) system, frequency multiplier circuit can be applied in multiple occasion, such as charge pump circuit, ADC(Analog-to-Digital Converter, analog/digital converter) circuit etc.By this frequency multiplier circuit, can provide for system the clock signal of higher frequency.
In the prior art one, adopt PLL(Phase Locked Loop, phase-locked loop) as frequency multiplier circuit.Its advantage is that the frequency that can realize any multiple increases, and output frequency is very accurate, can accurately control the duty ratio of its output signal.But the shortcoming of PLL circuit is the circuit relative complex, and circuit power consumption and area are all larger.
The frequency multiplier circuit of prior art two as shown in Figure 1, described frequency multiplier circuit comprises: time delay module 10a and XOR gate 20a.With reference to Fig. 1, clock signal clk _ D after obtaining delaying time behind the described time delay module 10a of input clock signal CLK_IN process.After clock signal clk _ D carries out logical operation by described XOR gate 20a after described input clock signal CLK_IN and the time-delay, can obtain frequency multiplication signal CLK_OUT, realize double to the frequency of input clock signal CLK_IN.The oscillogram of clock signal clk _ D and frequency multiplied clock signal CLK_OUT as shown in Figure 2 after described input clock signal CLK_IN, the time-delay.
The advantage of frequency multiplier circuit shown in Figure 1 is that circuit structure is simple, is easy to realize.But the time-delay of the time delay module 10a of circuit shown in Figure 1 easily is subject to the various effect of parameters such as temperature, voltage, technique, thereby can't accurately control the duty ratio of the frequency multiplication signal CLK_OUT of output, affects the application of frequency multiplier circuit.
Summary of the invention
A kind of frequency multiplier circuit is provided in the embodiment of the invention, can has realized the frequency multiplication of clock signal, and can accurately control the duty ratio of its clock signal with lower power consumption, less area.
On the one hand, provide a kind of frequency multiplier circuit, described circuit comprises: time delay module, logical operation module, reference voltage generation module and feedback control module; Described time delay module, voltage is controlled in the time-delay that is used for the output of reception input clock signal and described feedback control module, described input clock signal is carried out delay process, the output delay clock signal according to described time-delay control voltage; Described logical operation module is used for described input clock signal and described delay clock signal are carried out logic XOR or same exclusive disjunction, obtains the frequency multiplied clock signal, and exports described feedback control module to; Described reference voltage generation module is used for generating a reference voltage that is directly proportional with supply voltage, and exports described feedback control module to; Described feedback control module is used for the average voltage of described frequency multiplied clock signal and the difference of described reference voltage are amplified, and obtains described time-delay control voltage, and exports described time delay module to.
In the possible implementation of the first, described logical operation circuit is an XOR gate or same or door.
In the possible implementation of the second, described reference voltage generation module is a resistor voltage divider circuit.
In conjunction with the possible implementation of the second, in the third possible implementation, described reference voltage generation module comprises: the first resistance and the second resistance; One termination power voltage of described the first resistance, described the second resistance of another termination of described the first resistance; The other end ground connection of described the second resistance; The common port of described the first resistance and the second resistance is as the output of described reference voltage generation module.
In the 4th kind of possible implementation, described feedback control module is an integrator.
In conjunction with the 4th kind of possible implementation, in the 5th kind of possible implementation, described feedback control module comprises: the 3rd resistance, electric capacity and operational amplifier; One end of described the 3rd resistance is as the inverting input of described feedback control module, the inverting input of the described operational amplifier of another termination of described the 3rd resistance; The normal phase input end of described operational amplifier is as the normal phase input end of described feedback control module, and the output of described operational amplifier is as the output of described feedback control module; Described electric capacity is connected between the inverting input and output of described operational amplifier.
The described frequency multiplier circuit of the embodiment of the invention, compared with prior art, described time delay module is controlled voltage control to the delay process of input clock signal by the time-delay that is received from feedback control module, thereby realization is to the accurate control of the duty ratio of the frequency multiplied clock signal of output.
Simultaneously, in the described frequency multiplier circuit of the embodiment of the invention, described time delay module, logical operation module, reference voltage generation module and feedback control module can realize by simple circuit form, its circuit area is less, power consumption is lower, and can be good at realizing the purpose of frequency multiplication.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use among the embodiment, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the frequency multiplier circuit figure of prior art two;
Fig. 2 is the rear clock signal clk _ D of input clock signal CLK_IN, time-delay of circuit shown in Figure 1 and the oscillogram of frequency multiplied clock signal CLK_OUT;
The frequency multiplier circuit figure that Fig. 3 provides for the embodiment of the invention one;
The frequency multiplier circuit figure that Fig. 4 provides for the embodiment of the invention two.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is carried out clear, complete description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
A kind of frequency multiplier circuit is provided in the embodiment of the invention, can has realized the frequency multiplication of clock signal, and can accurately control the duty ratio of its clock signal with lower power consumption, less area.
With reference to shown in Figure 3, the frequency multiplier circuit figure that provides for the embodiment of the invention one.As shown in Figure 3, described frequency multiplier circuit comprises: time delay module 10, logical operation module 20, reference voltage generation module 30 and feedback control module 40.
The clock signal input terminal of described time delay module 10 is as the input of described frequency multiplier circuit, receive input clock signal CLK_IN, the output of the described feedback control module 40 of control signal input termination of described time delay module 10, the first input end of the described logical operation module 20 of output termination of described time delay module 10.
The second input termination described input clock signal CLK_IN of described logical operation module 20, the output of described logical operation module 20 be as the output of described frequency multiplier circuit, output frequency multiplied clock signal CLK_OUT.
The normal phase input end of described feedback control module 40 connects the output of described reference voltage generation module 30, the output of the described logical operation module 20 of anti-phase input termination of described feedback control module 40, the control signal input of the described time delay module 10 of output termination of described feedback control module 40.
Described time delay module 10, be used for receiving the time-delay control voltage DELAY_CTRL of input clock signal CLK_IN and 40 outputs of described feedback control module, described input clock signal CLK_IN is carried out delay process, output delay clock signal CLK_D according to described time-delay control voltage DELAY_CTRL.Wherein, described time-delay control voltage DELAY_CTRL is used for controlling the delay time of described delay process.
Described logical operation module 20 is used for described input clock signal CLK_IN and delay clock signal CLK_D are carried out logic XOR or same exclusive disjunction, obtains frequency multiplied clock signal CLK_OUT, and exports described feedback control module 40 to.
Described reference voltage generation module 30 is used for generating a reference voltage V REF who is directly proportional with supply voltage, and exports described feedback control module 40 to.
Described feedback control module 40 is used for the average voltage of described frequency multiplied clock signal CLK_OUT and the difference of described reference voltage V REF are amplified, and obtains described time-delay control voltage DELAY_CTRL, and exports described time delay module 10 to.
Concrete, the described frequency multiplier circuit of the embodiment of the invention produces a delay clock signal CLK_D based on input clock signal CLK_IN by described time delay module 10, and its delay time can be controlled by described time-delay control voltage DELAY_CTRL.Then, carry out logic XOR or same exclusive disjunction by 20 couples of described input clock signal CLK_IN of described logical operation module and delay clock signal CLK_D, realization obtains described frequency multiplied clock signal CLK_OUT to the frequency multiplication of described input clock signal CLK_IN.Described feedback control module 40 compares average voltage and the described reference voltage V REF of described frequency multiplied clock signal CLK_OUT, and the difference voltage that the two relatively obtains amplified, obtain described time-delay control voltage DELAY_CTRL, control the delay time of described time delay module 10.
The operation principle of the described frequency multiplier circuit of the embodiment of the invention is: the duty ratio of establishing the frequency multiplied clock signal CLK_OUT of described circuit output is D, then the average voltage of described frequency multiplied clock signal CLK_OUT be D*VDD(wherein, VDD is the supply voltage of described circuit).The described frequency multiplier circuit of the embodiment of the invention consists of a feedback control loop, described feedback control module 40 compares described average voltage D*VDD and described reference voltage V REF, and with difference voltage (VREF-D*VDD) amplification that relatively obtains, obtain time-delay control voltage DELAY_CTRL, feed back to described time delay module 10, control the delay time of described time delay module 10.Because the gain (being the multiplication factor of described feedback control module 40) of whole feedback control loop is very large, after described circuit is stable, the average voltage D*VDD of the frequency multiplied clock signal CLK_OUT of its output and described reference voltage V REF approximately equal are D*VDD=VREF.And described reference voltage V REF is directly proportional with supply voltage, and can be made as K*VDD(K is normal number), and its Proportional coefficient K is accurately controlled.Then have, D*VDD=K*VDD obtains D=K.
As the above analysis, for the described frequency multiplier circuit of the embodiment of the invention, after circuit is stable, the duty ratio D of the frequency multiplied clock signal CLK_OUT of described circuit output is approximately equal to the Proportional coefficient K of described reference voltage V REF, the duty ratio D that is described frequency multiplied clock signal CLK_OUT can accurately control by the concrete setting to reference voltage V REF, and described duty ratio D is subjected to the impact of ambient temperature, supply voltage, technique very little.
The described frequency multiplier circuit of the embodiment of the invention, compared with prior art, for described time delay module 10 increases by a control signal input, control voltage DELAY_CTRL control to the delay process of input clock signal CLK_IN by the time-delay that is received from feedback control module 40, thereby realization is to the accurate control of the duty ratio D of the frequency multiplied clock signal CLK_OUT of output.
Simultaneously, in the described frequency multiplier circuit of the embodiment of the invention, described time delay module 10, logical operation module 20, reference voltage generation module 30 and feedback control module 40 can realize by simple circuit form, its circuit area is less, power consumption is lower, and can be good at realizing the purpose of frequency multiplication.
With reference to shown in Figure 4, the frequency multiplier circuit figure that provides for the embodiment of the invention two.Circuit is a kind of specific implementation form of the described frequency multiplier circuit of the embodiment of the invention as shown in Figure 4.Certainly, the described frequency multiplier circuit of the embodiment of the invention can but be not limited to adopt circuit shown in Figure 4 to realize.In this area, any circuit that can realize the function of the described circuit modules of the embodiment of the invention all can be used for the embodiment of the invention, to realize goal of the invention of the present invention.
Concrete, as shown in Figure 4, described logical operation circuit 20 can be an XOR gate or same or door.Wherein, describe as an example of XOR gate XOR2 example among Fig. 4.
The first end of described XOR gate XOR2 as described logical operation module 20 first input end, connect the output of described time delay module 10; The second end of described XOR gate XOR2 meets described input clock signal CLK_IN as the second input of described logical operation module 20; The output of described XOR gate XOR2 is as the output of described logical operation module 20, output frequency multiplied clock signal CLK_OUT.
Described XOR gate XOR2 is used for realizing described input clock signal CLK_IN and delay clock signal CLK_D are carried out the logic XOR, obtains frequency multiplied clock signal CLK_OUT, and exports described feedback control module 40 to.
Certainly, in other embodiments of the invention, any can realize the logic XOR with or circuit structure may be used to the described circuit of the embodiment of the invention, realize the purpose of the frequency multiplication of the embodiment of the invention.
As shown in Figure 4, in the embodiment of the invention, described reference voltage generation module 30 can be realized by a resistor voltage divider circuit.Concrete, described reference voltage generation module 30 comprises: the first resistance R 1 and the second resistance R 2.
One termination power voltage VDD of described the first resistance R 1, described the second resistance R 2 of another termination of described the first resistance R 1; The other end ground connection of described the second resistance R 2.
The common port of described the first resistance R 1 and the second resistance R 2 is exported described reference voltage V REF as the output of described reference voltage generation module 30.
In the circuit shown in Figure 4, described reference voltage V REF=R2*VDD/(R1+R2).Described reference voltage V REF is directly proportional with described supply voltage VDD, its Proportional coefficient K=R2/(R1+R2).
According to the analysis of previous embodiment as can be known, after circuit was stable, the duty ratio D of the frequency multiplied clock signal CLK_OUT of described circuit output was approximately equal to the Proportional coefficient K of described reference voltage V REF, is described duty ratio D and is approximately equal to R2/(R1+R2).Therefore, the duty ratio D of described frequency multiplied clock signal CLK_OUT can accurately set by the value of the first resistance R 1 and the second resistance R 2, realization is to the accurate control of the duty ratio D of described frequency multiplied clock signal CLK_OUT, so that described duty ratio D is subjected to the impact of ambient temperature, supply voltage, technique very little.
Certainly, in other embodiments of the invention, any circuit structure that can generate the reference voltage that is directly proportional with supply voltage may be used to the described circuit of the embodiment of the invention, realizes the purpose of the frequency multiplication of the embodiment of the invention.
As shown in Figure 4, described feedback control module 40 comprises: the 3rd resistance R 3, capacitor C 1 and operational amplifier A 1.
Wherein, an end of described the 3rd resistance R 3 is as the output of the described logical operation module 20 of anti-phase input termination of described feedback control module 40, the inverting input of the described operational amplifier A 1 of another termination of described the 3rd resistance R 3.
The normal phase input end of described operational amplifier A 1 connects the output of described reference voltage generation module 30 as the normal phase input end of described feedback control module 40, the output of described operational amplifier A 1 is as the control signal input of the described time delay module 10 of output termination of described feedback control module 40.
Described capacitor C 1 is connected between the inverting input and output of described operational amplifier A 1.
Certainly, in other embodiments of the invention, any circuit structure of the function of described feedback control module of can realizing may be used to the described circuit of the embodiment of the invention, realizes the purpose of the frequency multiplication of the embodiment of the invention.
The described frequency multiplier circuit of the embodiment of the invention, compared with prior art, for described time delay module 10 increases by a control signal input, control voltage DELAY_CTRL control to the delay process of input clock signal CLK_IN by the time-delay that is received from feedback control module 40, thereby realization is to the accurate control of the duty ratio D of the frequency multiplied clock signal CLK_OUT of output.
Simultaneously, in the described frequency multiplier circuit of the embodiment of the invention, its circuit structure is simple, so that its circuit area is less, power consumption is lower, and can be good at realizing the purpose of frequency multiplication.
Above to a kind of frequency multiplier circuit provided by the present invention, be described in detail, used specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications.In sum, this description should not be construed as limitation of the present invention.
Claims (6)
1. a frequency multiplier circuit is characterized in that, described circuit comprises: time delay module, logical operation module, reference voltage generation module and feedback control module;
Described time delay module, voltage is controlled in the time-delay that is used for the output of reception input clock signal and described feedback control module, described input clock signal is carried out delay process, the output delay clock signal according to described time-delay control voltage;
Described logical operation module is used for described input clock signal and described delay clock signal are carried out logic XOR or same exclusive disjunction, obtains the frequency multiplied clock signal, and exports described feedback control module to;
Described reference voltage generation module is used for generating a reference voltage that is directly proportional with supply voltage, and exports described feedback control module to;
Described feedback control module is used for the average voltage of described frequency multiplied clock signal and the difference of described reference voltage are amplified, and obtains described time-delay control voltage, and exports described time delay module to.
2. frequency multiplier circuit according to claim 1 is characterized in that, described logical operation circuit is an XOR gate or same or door.
3. frequency multiplier circuit according to claim 1 is characterized in that, described reference voltage generation module is a resistor voltage divider circuit.
4. frequency multiplier circuit according to claim 3 is characterized in that, described reference voltage generation module comprises: the first resistance and the second resistance;
One termination power voltage of described the first resistance, described the second resistance of another termination of described the first resistance;
The other end ground connection of described the second resistance;
The common port of described the first resistance and the second resistance is as the output of described reference voltage generation module.
5. frequency multiplier circuit according to claim 1 is characterized in that, described feedback control module is an integrator.
6. frequency multiplier circuit according to claim 5 is characterized in that, described feedback control module comprises: the 3rd resistance, electric capacity and operational amplifier;
One end of described the 3rd resistance is as the inverting input of described feedback control module, the inverting input of the described operational amplifier of another termination of described the 3rd resistance;
The normal phase input end of described operational amplifier is as the normal phase input end of described feedback control module, and the output of described operational amplifier is as the output of described feedback control module;
Described electric capacity is connected between the inverting input and output of described operational amplifier.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012104438209A CN102938635A (en) | 2012-11-08 | 2012-11-08 | Frequency multiplication circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012104438209A CN102938635A (en) | 2012-11-08 | 2012-11-08 | Frequency multiplication circuit |
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| CN102938635A true CN102938635A (en) | 2013-02-20 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103490728A (en) * | 2013-09-04 | 2014-01-01 | 苏州苏尔达信息科技有限公司 | Frequency multiplication circuit |
| CN105322890A (en) * | 2014-07-23 | 2016-02-10 | 精工爱普生株式会社 | Frequency multiplication circuit, electronic device and moving object |
| CN112416055A (en) * | 2020-11-20 | 2021-02-26 | 海光信息技术股份有限公司 | Clock management method and device for multi-core CPU, electronic equipment and storage medium |
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| US6337588B1 (en) * | 1998-07-17 | 2002-01-08 | Oak Technology, Inc. | Apparatus and method for doubling the frequency of a clock signal |
| TW200427224A (en) * | 2003-05-21 | 2004-12-01 | Myson Century Inc | Clock multiplier |
| CN1553571A (en) * | 2003-06-06 | 2004-12-08 | 丽台科技股份有限公司 | Pulse distance voltage converter and converting method thereof |
| US20080309398A1 (en) * | 2007-06-15 | 2008-12-18 | Oki Electric Industry Co., Ltd. | Multiplier circuit |
| CN102664608A (en) * | 2010-12-28 | 2012-09-12 | 博通集成电路（上海）有限公司 | Frequency multiplier and frequency multiplication method |
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| US6337588B1 (en) * | 1998-07-17 | 2002-01-08 | Oak Technology, Inc. | Apparatus and method for doubling the frequency of a clock signal |
| TW200427224A (en) * | 2003-05-21 | 2004-12-01 | Myson Century Inc | Clock multiplier |
| CN1553571A (en) * | 2003-06-06 | 2004-12-08 | 丽台科技股份有限公司 | Pulse distance voltage converter and converting method thereof |
| US20080309398A1 (en) * | 2007-06-15 | 2008-12-18 | Oki Electric Industry Co., Ltd. | Multiplier circuit |
| CN102664608A (en) * | 2010-12-28 | 2012-09-12 | 博通集成电路（上海）有限公司 | Frequency multiplier and frequency multiplication method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103490728A (en) * | 2013-09-04 | 2014-01-01 | 苏州苏尔达信息科技有限公司 | Frequency multiplication circuit |
| CN105322890A (en) * | 2014-07-23 | 2016-02-10 | 精工爱普生株式会社 | Frequency multiplication circuit, electronic device and moving object |
| CN112416055A (en) * | 2020-11-20 | 2021-02-26 | 海光信息技术股份有限公司 | Clock management method and device for multi-core CPU, electronic equipment and storage medium |
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Application publication date: 20130220 |