CN110601695B - High-precision dynamic comparator - Google Patents
High-precision dynamic comparator Download PDFInfo
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- CN110601695B CN110601695B CN201910856644.3A CN201910856644A CN110601695B CN 110601695 B CN110601695 B CN 110601695B CN 201910856644 A CN201910856644 A CN 201910856644A CN 110601695 B CN110601695 B CN 110601695B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
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Abstract
The invention discloses a high-precision dynamic comparator, and relates to the technical field of integrated circuits. The high-precision dynamic comparator comprises a latch circuit, a time sequence logic circuit and at least two stages of dynamic pre-amplifying circuits which are connected with each other; a first-stage dynamic pre-amplification circuit in the at least two-stage dynamic pre-amplification circuits receives the voltage to be compared and amplifies the voltage to be compared according to a first clock signal sent by the sequential logic circuit; the next stage dynamic pre-amplifying circuit in the at least two stages of dynamic pre-amplifying circuits amplifies an input signal according to a clock signal sent by the sequential logic circuit, wherein the input signal is a voltage to be compared after being preprocessed by the previous stage dynamic pre-amplifying circuit; the latch circuit receives the output signal processed by the last stage of dynamic pre-amplifying circuit, processes the output signal according to the latch clock signal sent by the sequential logic circuit, and outputs a comparison result. The invention adopts a cascade structure of multistage dynamic pre-amplification and latching, thereby realizing high comparison precision and no static power consumption.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a high-precision dynamic comparator.
Background
In the application scenes of the portable and internet of things, a low-power-consumption high-precision SAR ADC (Successive approximation register Analog-to-Digital Converter, successive approximation analog-to-digital converter) has become a popular direction of research, and is used as a comparator of a SAR ADC core circuit, so that higher requirements are also put forward on the power consumption and the precision of the SAR ADC core circuit.
In the prior art, the dynamic comparator has high speed and no static power consumption, but has lower resolution, and is generally used for SAR ADC with middle and low resolution; the accuracy of a static comparator is typically high, but there is static power consumption in the circuit, which is typically employed in high resolution SAR ADCs.
As shown in fig. 1, the dynamic comparator in the prior art generally adopts a structure of a first-stage dynamic pre-amplifying circuit pre_dcomp and a latch, but is generally only used for SAR ADCs with resolution below 12 bits due to the limitation of noise and gain, and is difficult to realize higher precision. As shown in fig. 2, the static comparator in the prior art is generally composed of two stages of static pre-amplifying circuits pre_amp1, pre_amp2 and a latch, and the static comparator is easy to realize higher resolution, but the static comparator has static power consumption and is not suitable for low-power consumption application.
Disclosure of Invention
The invention mainly aims to provide a high-precision dynamic comparator, and aims to realize a comparator with high precision and low power consumption.
In order to achieve the above object, the present invention provides a high-precision dynamic comparator, which comprises a latch circuit, a sequential logic circuit and at least two stages of dynamic pre-amplifying circuits, wherein the sequential logic circuit and the at least two stages of dynamic pre-amplifying circuits are connected with each other;
a first-stage dynamic pre-amplification circuit in the at least two-stage dynamic pre-amplification circuits receives the voltage to be compared, and amplifies the voltage to be compared according to a first clock signal sent by the sequential logic circuit; the next-stage dynamic pre-amplification circuit in the at least two-stage dynamic pre-amplification circuit amplifies an input signal according to a clock signal sent by the sequential logic circuit, wherein the input signal is the voltage to be compared after being preprocessed by the previous-stage dynamic pre-amplification circuit;
the latch circuit receives the output signal processed by the last stage of dynamic pre-amplifying circuit in the at least two stages of dynamic pre-amplifying circuits, processes the output signal according to the latch clock signal sent by the sequential logic circuit, and outputs a comparison result.
Preferably, the first stage dynamic pre-amplifying circuit comprises a first PMOS tube and a second PMOS tube which receive the voltage to be compared, and further comprises a third PMOS tube connected to the power supply voltage, wherein the third PMOS tube is connected to the first PMOS tube and the second PMOS tube through a first resistor; the first PMOS tube is grounded through a first capacitor, and the second PMOS tube is grounded through a second capacitor;
the first PMOS tube is also connected with a first NMOS tube and a second NMOS tube, and the first NMOS tube and the second NMOS tube are respectively grounded; the first capacitor and the second capacitor are connected with a third NMOS tube; the second PMOS tube is connected with a fourth NMOS tube, and the fourth NMOS tube is grounded.
Preferably, the source electrode of the first PMOS transistor is connected to the drain electrode of the third PMOS transistor through a first resistor, the drain electrode thereof is grounded through a first capacitor, and the gate electrode thereof is connected to a first voltage of the voltages to be compared; the source electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube through a first resistor, the drain electrode of the second PMOS tube is grounded through a second capacitor, and the grid electrode of the second PMOS tube is connected with a second voltage in the voltages to be compared; the source electrode of the third PMOS tube is connected with a power supply, and the grid electrode of the third PMOS tube receives the first clock signal;
the drain electrode of the first NMOS tube is connected with the source electrode of the first PMOS tube, the grid electrode receives the first clock signal, and the source electrode is grounded; the drain electrode of the second NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode receives the first clock signal, and the source electrode is grounded; the source electrode of the third NMOS tube is connected with the drain electrode of the first PMOS tube and the first capacitor, and the drain electrode of the third NMOS tube is connected with the drain electrode of the second PMOS tube and the second capacitor; and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode receives the first clock signal, and the source electrode is grounded.
Preferably, the structure of each stage of circuit in the at least two stages of dynamic pre-amplifying circuits is the same as that of the first stage of dynamic pre-amplifying circuit.
Preferably, the at least two-stage dynamic pre-amplifying circuit further comprises a second-stage dynamic pre-amplifying circuit, and the structure of the second-stage dynamic pre-amplifying circuit is the same as that of the first-stage dynamic pre-amplifying circuit;
the second-stage dynamic pre-amplification circuit receives a second clock signal to pre-amplify the voltage to be compared processed by the first-stage dynamic pre-amplification circuit.
Preferably, the gate of the third NMOS transistor in the first stage dynamic pre-amplifying circuit receives a first pre-clock sent by the sequential logic circuit, and the first clock signal is delayed by a first time from the first pre-clock to turn over, so that the third NMOS transistor is turned off before the first PMOS transistor and the second PMOS transistor are turned on.
Preferably, the second stage dynamic pre-amplifying circuit further receives a second pre-clock sent by the sequential logic circuit, and the second pre-clock is delayed by a second time from the first clock signal to turn over, so that the second stage dynamic pre-amplifying circuit works after the first stage dynamic pre-amplifying circuit works; the second clock signal is delayed from the second pre-clock by a third time to flip.
Preferably, the latch clock signal is delayed from the second clock signal by a fourth time to flip.
The technical scheme of the invention adopts a cascade structure of the multistage dynamic pre-amplifying circuit and the latch circuit, and the multistage dynamic pre-amplifying circuit is controlled by sending the preset time sequence through the time sequence logic circuit, so that higher comparison precision is realized, static power consumption is avoided, and a low-power consumption solution is provided for the SAR ADC with medium and high precision.
Drawings
FIG. 1 is a schematic diagram of a dynamic comparator in the prior art;
FIG. 2 is a schematic diagram of a static comparator according to the prior art;
FIG. 3 is a schematic diagram of a high-precision dynamic comparator according to the present invention;
FIG. 4 is a schematic diagram of the circuit principle of the high-precision dynamic comparator of the present invention;
FIG. 5 is a timing diagram of clock signals according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a sequential logic circuit of the high-precision dynamic comparator of the present invention;
fig. 7 is a schematic diagram of other embodiments of the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The invention is further described below with reference to the accompanying drawings.
A high-precision dynamic comparator, as shown in fig. 3, comprises a latch circuit, a sequential logic circuit and at least two stages of dynamic pre-amplifying circuits which are connected with each other;
a first-stage dynamic pre-amplifying circuit pre-dcomp 1 of the at least two-stage dynamic pre-amplifying circuits receives voltages to be compared (VIPN and VINN), and amplifies the voltages to be compared according to a first clock signal CLK1 sent by the sequential logic circuit; the next-stage dynamic pre-amplification circuit in the at least two-stage dynamic pre-amplification circuit amplifies an input signal according to a clock signal sent by the sequential logic circuit, wherein the input signal is the voltage to be compared after being preprocessed by the previous-stage dynamic pre-amplification circuit;
the latch circuit receives the output signal processed by the last stage of dynamic pre-amplifying circuit in the at least two stages of dynamic pre-amplifying circuits, processes the output signal according to the latch clock signal CLK3 sent by the sequential logic circuit, and outputs comparison results (Q and QN). In a specific embodiment, the comparison result output by the latch circuit is high or low.
As shown in fig. 4, the first stage dynamic pre-amplifying circuit pre_dcomp1 includes a first PMOS tube PM1 and a second PMOS tube PM2 that receive the voltage to be compared, and further includes a third PMOS tube PM3 connected to the power supply voltage vdd, where the third PMOS tube PM3 is connected to the first PMOS tube PM1 and the second PMOS tube PM2 through a first resistor R1; the first PMOS tube PM1 is grounded through a first capacitor C1, and the second PMOS tube PM2 is grounded through a second capacitor C2;
the first PMOS tube PM1 is also connected with a first NMOS tube NM1 and a second NMOS tube NM2, and the first NMOS tube NM1 and the second NMOS tube NM2 are respectively grounded vss; the first capacitor C1 and the second capacitor C2 are connected with a third NMOS tube NM3; the second PMOS tube PM2 is connected to a fourth NMOS tube NM4, and the fourth NMOS tube NM4 is grounded vss.
Specifically, the values of the first capacitance C1 and the second capacitance C2 are equal.
The first stage dynamic pre-amplifying circuit pre-dcomp 1 is limited by the first resistor R1, and the effective charging time of the first capacitor C1 and the second capacitor C2 by the circuit can be adjusted to increase the gain of the first stage dynamic pre-amplifying circuit pre-dcomp 1.
As shown in fig. 4, the source of the first PMOS PM1 is connected to the drain of the third PMOS PM3 through a first resistor R1, the drain thereof is grounded vss through a first capacitor C1, and the gate thereof is connected to a first voltage VINN of the voltages to be compared; the source electrode of the second PMOS tube PM2 is connected to the drain electrode of the third PMOS tube PM3 through a first resistor R1, the drain electrode of the second PMOS tube PM3 is grounded vss through a second capacitor C2, and the grid electrode of the second PMOS tube PM2 is connected to a second voltage VINP in the voltages to be compared; the source electrode of the third PMOS tube PM3 is connected to a power supply vdd, and the grid electrode receives the first clock signal CLK1;
the drain electrode of the first NMOS tube NM1 is connected to the source electrode of the first PMOS tube PM1, the grid electrode receives the first clock signal CLK1, and the source electrode is grounded vss; the drain electrode of the second NMOS tube NM2 is connected to the drain electrode of the first PMOS tube PM1, the grid electrode receives the first clock signal CLK1, and the source electrode is grounded vss; the source electrode of the third NMOS tube NM3 is connected with the drain electrode of the first PMOS tube PM1 and the first capacitor C1, and the drain electrode is connected with the drain electrode of the second PMOS tube PM2 and the second capacitor C2; the drain electrode of the fourth NMOS transistor NM4 is connected to the drain electrode of the second PMOS transistor PM2, the gate electrode receives the first clock signal CLK1, and the source electrode is grounded vss.
As shown in fig. 3 and4, the at least two-stage dynamic pre-amplifying circuit further includes a second-stage dynamic pre-amplifying circuit pre_dcomp2, where the structure of the second-stage dynamic pre-amplifying circuit pre_dcomp2 is the same as that of the first-stage dynamic pre-amplifying circuit pre_dcomp1; the second-stage dynamic pre-amplifying circuit pre-dcomp 2 receives a second clock signal CLK2 to pre-amplify the voltage to be compared processed by the first-stage dynamic pre-amplifying circuit pre-dcomp 1.
As shown in fig. 4, the second stage dynamic pre-amplifying circuit pre_dcomp2 includes a fourth PMOS tube PM4 and a fifth PMOS tube PM5; the grid electrode of the fourth PMOS tube PM4 is connected with the drain electrode of the second PMOS tube PM2 and is used for receiving the second voltage VON1 after the amplification treatment of the first-stage dynamic pre-amplification circuit pre-dcomp 1; the drain electrode of the fifth PMOS tube PM5 is connected to the drain electrode of the first PMOS tube PM1 and is used for receiving the first voltage VOP1 amplified by the first-stage dynamic pre-amplifying circuit pre-dcomp 1;
the sources of the fourth PMOS tube PM4 and the fifth PMOS tube PM5 are connected to the drain electrode of the sixth PMOS tube PM6 through a second resistor R2, the source electrode of the sixth PMOS tube PM6 is connected to the power supply voltage vdd, and the grid electrode of the sixth PMOS tube PM6 is connected to the second clock signal CLK2. The source electrode of the fourth PMOS tube PM4 is connected with the drain electrode of the fifth NMOS tube NM5, the source electrode of the fifth NMOS tube NM5 is grounded vss, and the grid electrode of the fifth NMOS tube NM5 is connected with the second clock signal CLK2; the drain electrode of the fourth PMOS tube PM4 is connected with the drain electrode of the sixth NMOS tube NM6, the source electrode of the seventh NMOS tube NM7 and one end of the third capacitor C3, the other end of the third capacitor C3 is grounded vss, the source electrode of the sixth NMOS tube NM6 is grounded vss, and the grid electrode is connected with the second clock signal CLK2; the source of the seventh NMOS transistor NM7 is further connected to one end of the third capacitor C3, the drain is connected to the drain of the fifth PMOS transistor PM5, and the gate is connected to the second PRE-clock clk2_pre. The drain electrode of the fifth PMOS tube PM5 is connected to the drain electrode of the eighth NMOS tube NM8 and one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, and the source electrode of the eighth NMOS tube NM8 is grounded vss and the gate electrode is connected to the second clock signal CLK2. The drain electrode of the fourth PMOS tube PM4 outputs the second voltage VOP2 after the amplification process, and the drain electrode of the fifth PMOS tube PM5 outputs the first voltage VON2 after the amplification process.
The latch circuit receives the first voltage VON2 after the output amplification processing of the second-stage dynamic pre-amplification circuit pre-dcomp 2 and the second voltage VOP2 after the output amplification processing, latches the first voltage VON2 according to the latch clock signal CLK3 sent by the sequential logic circuit and outputs a result.
As shown in fig. 5, the gate of the third NMOS transistor NM3 in the first stage dynamic PRE-amplifying circuit pre_dcomp1 receives the first PRE-clock clk1_pre sent by the sequential logic circuit, and the first clock signal CLK1 is delayed by a first time TD1 from the first PRE-clock clk1_pre to flip, so that the third NMOS transistor NM3 is turned off before the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned on. The third NMOS transistor NM3 is turned off before the first-stage dynamic pre-amplifying circuit pre_dcomp1 starts to charge the first capacitor C1 and the second capacitor C2, which is beneficial to reducing the differential mode noise at two ends of the first capacitor C1 and the second capacitor C2.
As shown in fig. 5, the second-stage dynamic PRE-amplification circuit pre_dcomp2 further receives a second PRE-clock clk2_pre sent by the sequential logic circuit, where the second PRE-clock clk2_pre is delayed by a second time TD2 from the first clock signal CLK1 to flip, so that the second-stage dynamic PRE-amplification circuit pre_dcomp2 works after the first-stage dynamic PRE-amplification circuit pre_dcomp1 works; the second clock signal CLK2 is delayed from the second preamble clock clk2_pre by a third time TD3 to flip. The latch clock signal CLK3 is delayed from the second clock signal CLK2 by a fourth time TD4 to flip. Specifically, the first time TD1 and the third time TD3 are greater than 0 and as small as possible, i.e. the pre-clock needs to be turned on for a short period of time before the clock signal.
The second time TD2 may be adjusted according to the equivalent input noise of the second stage dynamic pre-amplifying circuit pre_dcomp2, and when the second stage dynamic pre-amplifying circuit pre_dcomp2 is turned on, the first stage dynamic pre-amplifying circuit pre_dcomp1 needs to amplify the voltage to be compared to exceed the equivalent input noise of the second stage dynamic pre-amplifying circuit pre_dcomp2.
The fourth time TD4 may be set according to the total equivalent input noise of the latch circuit, and when the latch circuit is turned on, the voltage to be compared amplified by the first stage dynamic pre-amplifying circuit pre_dcomp1 and the second stage dynamic pre-amplifying circuit pre_dcomp2 needs to be greater than the total equivalent input noise of the third stage latch circuit. When the second stage dynamic pre-amplifying circuit pre-dcomp 2 outputs the amplified voltage, the latch circuit can be turned on.
In a specific embodiment, after the latch circuit is turned on for the fifth time TD5, the first PRE-clock CLK1_pre, the first clock signal CLK1, the second PRE-clock CLK2_pre and the second clock signal CLK2 are flipped again, so that the first stage dynamic PRE-amplifying circuit pre_dcomp1 and the second stage dynamic PRE-amplifying circuit pre_dcomp2 are in a reset state, and the power consumption of the circuit is reduced. The fifth time TD5 may be set according to the operation time of the latch circuit, and the circuit may enter the reset state after the latch is completed.
Specifically, the input clock signal clk_in is input to the sequential logic circuit to cause the sequential logic circuit to generate the first preamble clock clk1_pre, the first clock signal CLK1, the second preamble clock clk2_pre, the second clock signal CLK2, and the latch clock signal CLK3, the first preamble clock clk1_pre being delayed by the sixth time TD6 to flip. Specifically, the sixth time TD6 is greater than 0 and as small as possible.
Specifically, the sequential logic circuit may be set according to the timing diagram shown IN fig. 5, IN which fig. 6 shows one embodiment of the sequential logic circuit, the input clock signal clk_in sequentially passes through the sixth delay TD6, the first delay TD1, the second delay TD2, the third delay TD3, the fourth delay TD4, the fifth delay TD5 AND the inverter INV, AND then performs the AND operation with the input clock signal clk_in to obtain a clock AND operation result clk_and, AND the clock AND operation result clk_and AND the input clock signal clk_in delayed by the sixth delay TD6 perform the NAND operation NAND1 to obtain the first PRE-clock clk1_pre; performing NAND operation on the clock AND operation result CLK_AND AND the input clock signal CLK_IN delayed by the sixth delay device TD6 AND the first delay device TD1 to obtain a first clock signal CLK1; performing NAND operation NAND3 on the clock AND operation result CLK_AND AND an input clock signal CLK_IN delayed by the sixth delay TD6, the first delay TD1 AND the second delay TD2 to obtain a second PRE-clock CLK2_PRE; AND performing NAND operation on the clock AND operation result CLK_AND AND the input clock signal CLK_IN delayed by the sixth delay TD6, the first delay TD1, the second delay TD2 AND the third delay TD3 to obtain a second clock signal CLK2. The input clock signal clk_in sequentially passes through the sixth delay TD6, the first delay TD1, the second delay TD2, the third delay TD3, and the fourth delay TD4 to obtain the latch clock signal CLK3. When the input clock signal clk_in is high, the sequential logic circuit starts to operate.
Specifically, the time delay duration of the first delayer TD1, the second delayer TD2, the third delayer TD3, the fourth delayer TD4, the fifth delayer TD5, and the sixth delayer TD6 is sequentially the first time TD1, the second time TD2, the third time TD3, the fourth time TD4, the fifth time TD5, and the sixth time TD6.
The working principle of the embodiment of the invention is as follows: before the comparator starts to operate, the input clock signal clk_in is at a low level, and at this time, the first-stage dynamic pre-amplifying circuit pre_dcomp1, the second-stage dynamic pre-amplifying circuit pre_dcomp2, and the latch circuit are IN a reset phase, and the voltages of the nodes VOP1, VON1, VOP2, VON2, Q, QN are set to 0.VINN and VINP are voltages to be compared.
When the input clock signal clk_in is at a high level, the sequential logic circuit sequentially outputs the first PRE-clock CLK1_pre, the first clock signal CLK1, the second PRE-clock CLK2_pre, the second clock signal CLK2, the latch clock signal CLK3 to the first-stage dynamic PRE-amplification circuit pre_dcomp1, the second-stage dynamic PRE-amplification circuit pre_dcomp2, and the latch circuit according to a timing chart.
First, the first front-end clock clk1_pre is inverted (changed from high level to low level), and the third NMOS transistor NM3 is turned off. The first clock signal CLK1 is turned over, the first-stage dynamic pre-amplification circuit pre-dcomp 1 pre-amplifies the input voltage to be compared, the third PMOS tube PM3 is conducted, the first NMOS tube NM1, the second NMOS tube NM2 and the fourth NMOS tube NM4 are turned off, the first PMOS tube PM1 and the second PMOS tube PM2 are biased by the voltage to be compared, at this time, the first-stage dynamic pre-amplification circuit pre-dcomp 1 enters a pre-amplification stage, and current respectively charges the first capacitor C1 and the second capacitor C2 through the third PMOS tube PM3, the first resistor R1, the first PMOS tube PM1 and the second PMOS tube PM 2.
Since the first voltage VINN and the second voltage VINP of the voltages to be compared are not equal, the charging speeds of the first capacitor C1 and the second capacitor C2 are different, and the gain of the output and the input can be expressed by equation one:
Wherein g m0 Is the approximate transconductance of the first PMOS tube PM1 or the second PMOS tube PM2,
is the duration of the low level in one clock cycle of the first clock signal CLK1;
the maximum value of the effective pre-amp time can be calculated by equation two:
wherein VCM IN For the common mode of the voltages to be compared, V th Is the threshold voltage of the first PMOS tube PM1 and the second PMOS tube PM2, I b For the average current flowing through the first resistor R1, the average current can be calculated by the equation
And (5) calculating.
The maximum gain of the effective pre-amplification can be calculated by equation three:
at the position of
The equivalent output noise for a time instant can be calculated by equation four:
wherein k is Boltzmann constant, T is thermodynamic temperature, gamma is constant, C 0 A value of the first capacitor C1 or the second capacitor C2;
the optimal equivalent input noise can be obtained by bringing the second equation into the fourth equation, such as the fifth equation:
from equation five, it can be seen that the capacitance C is increased 0 Or to extend the effective pre-amplification time
(i.e. reduce I b ) Comparator equivalent input noise can be reduced.
Then, the second PRE-clock clk2_pre and the second clock signal CLK2 are sequentially inverted, and the second-stage dynamic PRE-amplification circuit pre_dcomp2 starts to operate, and its operation is the same as that of the first-stage dynamic PRE-amplification circuit pre_dcomp1.
Finally, the latch clock signal CLK3 is inverted, and the output amplified by the second-stage dynamic pre-amplification circuit pre_dcomp2 is latched as a high-low level output by the latch circuit.
The embodiment of the invention adopts a mode that the first-stage dynamic pre-amplifying circuit pre-dcomp 1 works firstly, and then the second-stage dynamic pre-amplifying circuit pre-dcomp 2 starts to work again, so that equivalent input noise is reduced under the condition of maintaining gain, and the precision of the comparator is improved.
In some embodiments, each stage of the at least two stages of dynamic pre-amplification circuits has the same structure as the first stage of dynamic pre-amplification circuits pre_dcomp1.
As shown in fig. 7, in other embodiments, the at least two-stage dynamic pre-amplification circuit includes a first-stage dynamic pre-amplification circuit pre_dcomp1, a second-stage dynamic pre-amplification circuit pre_dcomp2, and a third-stage dynamic pre-amplification circuit pre_dcomp3. The one-stage amplification is added, so that the precision of the comparator can be improved.
It should be understood that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent structures or equivalent processes using the descriptions of the present invention and the accompanying drawings, or direct or indirect application in other relevant technical fields, are included in the scope of the present invention.
Claims (5)
1. The high-precision dynamic comparator comprises a latch circuit and is characterized by further comprising a sequential logic circuit and at least two stages of dynamic pre-amplifying circuits which are connected with each other;
a first-stage dynamic pre-amplification circuit in the at least two-stage dynamic pre-amplification circuits receives the voltage to be compared, and amplifies the voltage to be compared according to a first clock signal sent by the sequential logic circuit; the next-stage dynamic pre-amplification circuit in the at least two-stage dynamic pre-amplification circuit amplifies an input signal according to a clock signal sent by the sequential logic circuit, wherein the input signal is the voltage to be compared after being preprocessed by the previous-stage dynamic pre-amplification circuit;
the latch circuit receives the output signal processed by the last-stage dynamic pre-amplifying circuit in the at least two-stage dynamic pre-amplifying circuits, processes the output signal according to the latch clock signal sent by the sequential logic circuit and outputs a comparison result;
the sequential logic circuit sends a first clock signal and a first pre-clock to the first-stage dynamic pre-amplification circuit, and the first clock signal is delayed for a first time to overturn compared with the first pre-clock; the sequential logic circuit also sends a second clock signal and a second pre-clock to the second-stage dynamic pre-amplification circuit, wherein the second pre-clock is delayed by a second time to turn over compared with the first clock signal; the second clock signal is delayed by a third time to turn over than the second front-end clock; the latch clock signal is delayed from the second clock signal by a fourth time to flip.
2. The high-precision dynamic comparator according to claim 1, wherein the first stage dynamic pre-amplification circuit comprises a first PMOS tube and a second PMOS tube which receive the voltage to be compared, and further comprises a third PMOS tube connected to a power supply voltage, the third PMOS tube being connected to the first PMOS tube and the second PMOS tube through a first resistor; the first PMOS tube is grounded through a first capacitor, and the second PMOS tube is grounded through a second capacitor;
the first PMOS tube is also connected with a first NMOS tube and a second NMOS tube, and the first NMOS tube and the second NMOS tube are respectively grounded; the first capacitor and the second capacitor are connected with a third NMOS tube; the second PMOS tube is connected with a fourth NMOS tube, and the fourth NMOS tube is grounded;
and the grid electrode of the third NMOS tube in the first-stage dynamic pre-amplification circuit receives a first pre-clock sent by the time sequence logic circuit, and the first clock signal is delayed for a first time to overturn compared with the first pre-clock, so that the third NMOS tube is disconnected before the first PMOS tube and the second PMOS tube are connected.
3. The high-precision dynamic comparator according to claim 2, wherein the source of the first PMOS transistor is connected to the drain of the third PMOS transistor through a first resistor, the drain thereof is grounded through a first capacitor, and the gate thereof is connected to a first voltage of the voltages to be compared; the source electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube through a first resistor, the drain electrode of the second PMOS tube is grounded through a second capacitor, and the grid electrode of the second PMOS tube is connected with a second voltage in the voltages to be compared; the source electrode of the third PMOS tube is connected with a power supply, and the grid electrode of the third PMOS tube receives the first clock signal;
the drain electrode of the first NMOS tube is connected with the source electrode of the first PMOS tube, the grid electrode receives the first clock signal, and the source electrode is grounded; the drain electrode of the second NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode receives the first clock signal, and the source electrode is grounded; the source electrode of the third NMOS tube is connected with the drain electrode of the first PMOS tube and the first capacitor, and the drain electrode of the third NMOS tube is connected with the drain electrode of the second PMOS tube and the second capacitor; and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode receives the first clock signal, and the source electrode is grounded.
4. A high precision dynamic comparator according to claim 3, wherein each stage of the at least two stages of dynamic pre-amplification circuits has the same structure as the first stage of dynamic pre-amplification circuits.
5. The high precision dynamic comparator according to claim 3, wherein the at least two-stage dynamic pre-amplification circuit further comprises a second-stage dynamic pre-amplification circuit having the same structure as the first-stage dynamic pre-amplification circuit;
the second-stage dynamic pre-amplification circuit receives a second clock signal to pre-amplify the voltage to be compared processed by the first-stage dynamic pre-amplification circuit.
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