CN104184478B - Complementary cascade phase inverter and increment Sigma Delta analog to digital conversion circuits - Google Patents
Complementary cascade phase inverter and increment Sigma Delta analog to digital conversion circuits Download PDFInfo
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- CN104184478B CN104184478B CN201410386730.XA CN201410386730A CN104184478B CN 104184478 B CN104184478 B CN 104184478B CN 201410386730 A CN201410386730 A CN 201410386730A CN 104184478 B CN104184478 B CN 104184478B
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Abstract
The present invention is to provide a kind of complementary cascade phase inverter and increment Sigma Delta analog to digital conversion circuits.By second order sigma Delta modulator (101), desampling fir filter (102), clock signal generating circuit (103) and low pressure high-voltage converter (104) are formed, the switched-capacitor integrator with reset terminal in second order sigma Delta modulator (101) includes complementary cascade phase inverter, the complementary cascade phase inverter includes the first PMOS1 pipes and the first NMOS1 pipes, the 2nd NMOS2 that connected between the first PMOS1 pipes and the first NMOS1 pipes is managed and the 2nd PMOS2 pipes, 2nd NMOS2 pipes are upper, the grid end of 2nd NMOS2 pipes meets supply voltage VDD, 2nd PMOS2 pipes are under, 2nd PMOS2 pipes grid end is grounded GND.The characteristics of ADC of the present invention has extremely low power consumption and can worked at low supply voltages, suitable for the field such as portable instrument and measurement.
Description
Technical field
The present invention relates to a kind of increment Σ Δ analog-digital converters of low-voltage and low-power dissipation.
Background technology
Sigma-Delta (Σ Δs) analog-digital converters (ADC) due to it is simple in construction, power consumption is relatively low, precision is high and is not present
Device matching demand and be widely used in communication and MultiMedia Field.However, traditional Σ Δ structures are not suitable for instrument and survey
In amount application, very high precision and the linearity are required in such applications, and in addition to high dynamic range and signal to noise ratio,
Also require low-down imbalance and gain error.And traditional Σ Δs ADC only focuses on the dynamic spy such as signal to noise ratio and significance bit
Property.Increment Σ Δs ADC is highly suitable for instrumentation and testing field, because it can provide low imbalance, low gain error, point pair
Point, high-precision analog-to-digital conversion, and conversion time is relatively also shorter.
In fields such as instrumentation and testing fields, power consumption is that circuit design considers key factor.Currently with CMOS technology
The continuous reduction of device feature size, supply voltage also reduce in proportion therewith, and power consumption is also more and more lower.Yet with MOS devices
The threshold voltage of part can not be scaled down so that under sub-micro CMOS technology, low-voltage simulation circuit design encounters
The operational amplifier of very big challenge, particularly low-voltage and low-power dissipation turns into the design bottleneck of low-voltage simulation circuit.
The technology provided at present is：First, using body driving or digital assistant operational amplifier, however, body driving amplifier is made an uproar
Acoustic performance is poor, and causes bandwidth limited due to relatively low mutual conductance；Digital assistant amplifier needs extra digital calibration circuit, and
Consume unnecessary power consumption.2nd, circuit is converted into work based on comparator, based on forms of time and space and based on charge-domain
Mode, and omit operational amplifier.But the circuit based on comparator is also limited by low supply voltage；Electricity based on time domain
The precision of time signal is by device matching and the severe jamming of clock jitter in road；It is special that circuit based on charge-domain needs
Technique and higher supply voltage.
In recent years it has been proposed that a kind of new mode solves the problem：Switched-capacitor integrator based on phase inverter.Which
The simple inverter for being used in Class-AB or Class-C structures substitutes operational amplifier, significantly reduces system power dissipation
And circuit complexity.But two major issues of this mode are：Gain and bandwidth are severely limited；Because phase inverter does not have
Virtual earth point is, it is necessary to establish certainly, and cause dc point and phase inverter AC characteristic to have extremely strong process sensitivity.
The content of the invention
It is an object of the invention to provide the low complementary cascade phase inverter of a kind of high-gain, high bandwidth, process sensitivity.
The present invention also aims to provide a kind of low pressure, low-power consumption the increment Sigma- based on complementary cascade phase inverter
Delta analog to digital conversion circuits.
The complementary cascade phase inverter of the present invention includes the first PMOS1 pipes and the first NMOS1 pipes, is managed in the first PMOS1
And the first connect between NMOS1 pipes the 2nd NMOS2 pipes and the 2nd PMOS2 pipes, the 2nd NMOS2 pipes are in upper, the grid of the 2nd NMOS2 pipes
Termination power voltage VDD, the 2nd PMOS2 pipes are under, the 2nd PMOS2 pipes grid end ground connection GND.
The increment Sigma-Delta analog to digital conversion circuits based on complementary cascade phase inverter of the present invention are by second order Σ Δs
Modulator 101, desampling fir filter 102, clock signal generating circuit 103 and low pressure-high-voltage converter 104 are formed, second order Σ
The DC voltage of input is converted into the 1bit digital quantities comprising High-frequency quantization noise, desampling fir filter 102 by Delta modulator 101
1bit digital quantities are converted into N-bit numeral outputs, all clocks needed for the work of the generative circuit of clock signal generating circuit 103
Control signal, section clock signal are converted into the high voltage clock signal of modulator circuit demand through low pressure-high-voltage converter 104；
The switched-capacitor integrator with reset terminal in second order sigma Delta modulator 101 includes complementary cascade phase inverter, described mutual
Mending cascade phase inverter includes the first PMOS1 pipes and the first NMOS1 pipes, is gone here and there between the first PMOS1 pipes and the first NMOS1 pipes
Joining the 2nd NMOS2 pipes and the 2nd PMOS2 pipes, for the 2nd NMOS2 pipes upper, the grid end of the 2nd NMOS2 pipes meets supply voltage VDD, the
Two PMOS2 pipes are under, the 2nd PMOS2 pipes grid end ground connection GND.
The increment Sigma-Delta analog to digital conversion circuits based on complementary cascade phase inverter of the present invention can also wrap
Include：
1st, the second order sigma Delta modulator 101 includes first and second summing circuit 101-1,101-3, first and second band
Switched-capacitor integrator 101-2,101-4 of reset terminal, 1 bit comparator 101-5 and first and second 1 digit weighted-voltage D/A converter 101-
6th, 101-7, input voltage VIN and the one 1 digit weighted-voltage D/A converter 101-6 output are asked in the first summing circuit 101-1
And computing, operation result are input in the switched-capacitor integrator 101-2 of first band reset terminal, the switch electricity of first band reset terminal
The output and another 2nd 1 digit weighted-voltage D/A converter 101-7 output for holding integrator 101-2 are carried out in the second summing circuit 101-3
Summation operation, operation result are input in the second switched-capacitor integrator 101-4 with reset terminal, the second switch with reset terminal
Capacitance integrator 101-4 output is sent in 1 bit comparator 101-5；First and second switched-capacitor integrators with reset terminal
101-2,101-4 switch S1, S2, S3, S4, S5, S6, sampling capacitance C by first to the 6thS, integrating capacitor CI, correlated-double-sampling
Electric capacity CCAnd complementary cascade phase inverter composition.
2nd, the desampling fir filter 102 is made up of ripple counter 102-1 and accumulator 102-2, the accumulator
102-2 is made up of full adder and d type flip flop, and the 1bit numeral outputs of second order sigma Delta modulator 101 are sent to ripple counter 102-
1, the high level of 1bit numeral outputs is counted by ripple counter 102-1, ripple counter 102-1 output is sent to tired
Add device 102-2, accumulator 102-2 output is N-bit numeral output；102-2 points of ripple counter 102-1 and accumulator
Do not triggered in the rising edge and trailing edge of clock.
In order to overcome the shortcomings of existing Σ Δs ADC, the invention provides a kind of increment Σ Δs ADC of low-voltage and low-power dissipation.
The characteristics of ADC has extremely low power consumption and can worked at low supply voltages, suitable for the field such as portable instrument and measurement
In.
The DC voltage of input is converted into the 1bit numerals comprising High-frequency quantization noise using second order sigma Delta modulator 101
1bit digital quantities are converted into N-bit numeral outputs, the generative circuit of clock signal generating circuit 103 by amount, desampling fir filter 102
All clock control signals needed for work, section clock signal are converted into modulator circuit through low pressure-high-voltage converter 104 and needed
The high voltage clock signal asked.
Increment second order sigma Delta modulator portion 101 in the present invention is similar to traditional sigma Delta modulator, includes summing circuit
101-1,101-3, switched-capacitor integrator 101-2,101-4 with reset terminal, 1 bit comparator 101-5 and 1 digit weighted-voltage D/A converter
101-6,101-7, input voltage VIN and 1 digit weighted-voltage D/A converter 101-6 output carry out summation fortune in summing circuit 101-1
Calculate, operation result is input in the switched-capacitor integrator 101-2 with reset terminal, the output of the integrator and another 1 digit
Weighted-voltage D/A converter 101-7 output carries out summation operation in summing circuit 101-3, and operation result is input to the switch with reset terminal
In capacitance integrator 101-4, the output of integrator is sent in 1 bit comparator 101-5, and the output of the comparator is exactly to include high frequency
The 1bit digital quantities of quantizing noise.Switched-capacitor integrator 101-2,101-4 wherein with reset terminal before changing each time
All integrating capacitor is resetted.
The innovation of the present invention is using complementation in switched-capacitor integrator 101-2,101-4 design with reset terminal
The cascade phase inverter substitution operation amplifier of structure.Switched-capacitor integrator 101-2,101-4 with reset terminal are by switching
S1, S2, S3, S4, S5, S6, sampling capacitance CS, integrating capacitor CI, correlated-double-sampling electric capacity CCAnd complementary cascade phase inverter
Composition.Wherein complementary cascade phase inverter is connected between simple inverter PMOS1 and NMOS1 NMOS2 pipes and PMOS2
Pipe, wherein, for NMOS2 pipes upper, its grid end connects supply voltage VDD, PMOS2 pipe under, its grid end ground connection GND.Utilize PMOS
The complementarity sensitive to technique with NMOS tube, to reduce the process sensitivity of phase inverter performance.Complementary cascade is anti-in addition
NMOS tube and the PMOS isolation that parasitic capacitance is increased between the input and output of phase device, cascode structure have bigger increasing
Benefit, therefore have and preferably establish precision.The switched-capacitor integrator of correlated-double-sampling is also used in the present invention, is eliminated anti-phase
The imbalance of device, establish the virtual earth point of inverters work.
Increment Σ Δs ADC convert each time after reset function so that the design of down-sampled digital filter can be significantly
Simplify, it is not necessary to the combination of comb filter+finite impulse response filter+vertical correction wave filter.And only need to each
The high level of conversion is counted, then carry out it is cumulative can complete down-sampled filter function, the desampling fir filter in the present invention
Portion 102 is made up of ripple counter 102-1 and accumulator 102-2, and wherein accumulator 102-2 is made up of full adder and d type flip flop.
The 1bit numeral outputs in second order sigma Delta modulator portion 101 are sent to ripple counter 102-1, by ripple counter 102-1 to 1bit
The high level of numeral output is counted, and it, which is exported, is sent to accumulator 102-2, and accumulator 102-2 output is N-bit number
Word exports.In order to reduce circuit power consumption, ripple counter 102-1 and accumulator 102-2 this two parts are respectively in the rising of clock
Edge and trailing edge triggering.And the digital filter being related in the present invention has carried out specially treated in terms of sequential so that the filtering
Device power consumption is further reduced.
Brief description of the drawings
Fig. 1 is the increment Σ Δ ADC system block diagrams of the present invention.
Fig. 2 is second-order increment sigma Delta modulator block diagram.
Fig. 3-1 is the switched-capacitor integrator schematic diagram based on phase inverter with reset terminal.
Fig. 3-2 is complementary cascade inverter circuit figure.
Fig. 4 is digital filter system block diagram.
Embodiment
The embodiment of the present invention is introduced below in conjunction with the accompanying drawings.
The present invention is by second-order increment sigma Delta modulator portion 101, desampling fir filter portion 102, clock signal generating circuit 103
Formed with low pressure-high-voltage converter 104.The DC voltage of input is converted into comprising high frequency by second-order increment sigma Delta modulator 101
The 1bit digital quantities of quantizing noise, the digital quantity of the 1bit is input to desampling fir filter 102, and it is defeated to be converted into N-bit numerals
Go out, the clock signal part that clock signal generating circuit 103 generates conveys second-order increment by low pressure-high-voltage converter 104
Sigma Delta modulator 101, another part are conveyed to desampling fir filter portion 102.
Second-order increment sigma Delta modulator portion 101 is the core circuit of whole system, determines the conversion speed and essence of the ADC
Degree.Second-order increment sigma Delta modulator portion 101 is by summing circuit 101-1,101-3, the switched-capacitor integrator 101- with reset terminal
2nd, 101-4,1 bit comparator 101-5 and 1 digit weighted-voltage D/A converter 101-6,101-7 compositions.Input voltage VIN and 1 digital-to-analogue conversion
Device 101-6 output carries out summation operation in summing circuit 101-1, and operation result is input to the switching capacity product with reset terminal
Divide in device 101-2, the output of the integrator and another 1 digit weighted-voltage D/A converter 101-7 output are entered in summing circuit 101-3
Row summation operation, operation result are input in the switched-capacitor integrator 101-4 with reset terminal, and the output of integrator is input to 1
In bit comparator 101-5, the output of the comparator is 1bit digital quantities.
The cascade phase inverter of complementary structure is used in switched-capacitor integrator 101-2,101-4 design with reset terminal
Substitution operation amplifier.Switched-capacitor integrator 101-2,101-4 with reset terminal are adopted by switching S1, S2, S3, S4, S5, S6
Sample electric capacity CS, integrating capacitor CI, correlated-double-sampling electric capacity CCAnd complementary cascade phase inverter composition.
Traditional integrator uses the switching capacity form based on operational amplifier, is used as and put using phase inverter in the present invention
Big device uses, but because phase inverter only has an input, it is impossible to virtual earth point is provided.In Closed loop operation, phase inverter it is defeated
Enter to be represented by：
Here A represents DC current gain, the V of phase inverterCIRepresent integrating capacitor CIThe voltage at both ends, therefore, phase inverter
Input is approximately the offset voltage of phase inverter.It is C to feed back the electric charge shifted during phaseS(VI-VOFF), offset voltage to device size,
Threshold voltage, supply voltage and technique are all very sensitive, can cause integration is established to produce error.Also, due to simple inverter
Gain, bandwidth by supply voltage serious limitation, therefore cause integration establish it is very inaccurate.
To solve the problems, such as above integrator, the present invention makes to traditional quadrature device and changed at two：First, correlated-double-sampling is introduced
Establish virtual earth point, eliminate imbalance；2nd, using complementary type cascade CMOS inverter.
Fig. 3-1 is the switched-capacitor integrator with reset terminal for being used for second-order increment sigma Delta modulator portion 101 in the present invention
101-2 circuits.In sampling phase, sampling capacitance CSNegative plate connect input signal, positive plate end ground connection, input signal is sampled
Sampling capacitance CSOn, the input and output side short circuit of phase inverter, form a Unity-gain buffer form.Electric capacity CCPositive plate
Meet the offset voltage V of the input of phase inverter, negative pole plate earthing, therefore phase inverterOFFIt is sampled electric capacity CCOn.In integration clock
Phase incipient stage, sampling capacitance CSNegative pole plate earthing, positive plate meets CCNegative plate and integrating capacitor CIPositive plate, CC's
Positive plate meets the input of phase inverter, CINegative plate be connected on the output end of phase inverter.Therefore, VGThe voltage of node is changed into inputting
Sampled voltage VI, VXNode is changed into VOFF-VI.When closed loop is formed, because negative-feedback passes through electric capacity CIFormed, VXNode is VOFF,
And due to CCKeep VOFF, therefore force VGAs signal ground, such VGIt can be regarded as virtual earth point, electric capacity CSOn electric charge transfer
To CIIn.Sampling phase and feedback phase CCPhase inverter offset voltage is all maintained, therefore offset voltage is eliminated.Input and export
Relation is：
CSvI(n+1/2)+CIvO(n)=CIvO(n+1) (2)
Phase inverter such as Fig. 3-1 uses complementary cascade phase inverter, and its circuit is as shown in figure 3-2.PMOS1 and
NMOS1 forms simple inverter, and connected between PMOS1 and NMOS1 NMOS2 pipes and PMOS2 pipes, wherein NMOS2 are located at PMOS1
Between PMOS2.Using PMOS and the NMOS tube complementarity sensitive to technique, to reduce the technique of phase inverter performance sensitivity
Property.Cascode structure adds output impedance, improves phase inverter gain, improves signal and establishes precision.Due to gain
Improve, the phase inverter can be operated in Class-AB structures, improve system bandwidth.
Fig. 4 is the structure chart of desampling fir filter portion 102 in the present invention, by ripple counter 102-1 and accumulator 102-2
Composition, wherein accumulator is made up of full adder and d type flip flop.The 1bit numeral outputs in second order sigma Delta modulator portion 101 are input to
Ripple counter 102-1, the high level of 1bit numeral outputs is counted by ripple counter 102-1, it is input to
Accumulator 102-2, accumulator 102-2 output are N-bit numeral output.
Increment Σ Δs ADC input signal is generally direct current signal, therefore the calculating of noise and traditional Σ Δs ADC area
Not, to reach aimed at precision, can be calculated by digital filter.For second-order modulator, digital filter can use
Two integrator cascades.
The output of second-order modulator can be expressed as：
Y (z)=z-1X(z)+(1-z-1)2E(z) (3)
Wherein Y represents the output of modulator, and X represents the input of modulator, and E represents quantizing noise.Digital filter passes through
Output after integrating twice is expressed as:
The time domain output of digital filter is represented by：
If quantizing noise is limited, have：
So to reach N-bit resolution ratio, LSB=Xmax/2N, then
N=log2n(n+1)-1bit (9)
Wherein n is the operation times of digital filter, that is, over-sampling multiple.Before changing each time, ripple meter
Number device and accumulator are reset, through 2(N+1)/ 2 cycles export N-bit numeral outputs.The present invention is enterprising in the sequential of digital filter
Two specially treateds are gone.Firstth, ripple counter and accumulator trigger in the rising edge and trailing edge of clock respectively, make first
Level level signal settling time at least can be half of clock cycle, it is allowed to which circuit is established voltage using extremely faint electric current and believed
Number, significantly reduce power consumption.Secondth, sampling clock is n times than over-sampling multiple increase by one, such as over-sampling multiple, actual
Upper each sample quantization is n+1 times, because in accumulator, accumulation result transmission of each rising edge clock adder
Into d type flip flop, therefore the result after n+1 clock in d type flip flop is just the operation result of above n times, so follow-up
SRAM just only need to from d type flip flop reading, if only n clock, then SRAM just needs the reading after adder, aobvious
The data holding ability and driving force of right adder all can not show a candle to d type flip flop.
Clock signal generating circuit 103 utilizes input clock signal CLK, produces two-way not overlapping clock φ1And φ2, and
φ1And φ2Trailing edge postpones signal φ1dAnd φ2d, this four clock signals are conveyed to low pressure-high-voltage converter 104, by when
The high level of clock signal is converted to higher voltage, control signal of the second order sigma Delta modulator as switch is then passed to, with drop
The conducting resistance of low switch.
Claims (2)
1. a kind of increment Sigma-Delta analog to digital conversion circuits based on complementary cascade phase inverter, modulated by second order Σ Δs
Device (101), desampling fir filter (102), clock signal generating circuit (103) and low pressure-high-voltage converter (104) are formed, and two
The DC voltage of input is converted into the 1bit digital quantities comprising High-frequency quantization noise, down-sampled filter by rank sigma Delta modulator (101)
1bit digital quantities are converted into N-bit numeral outputs, clock signal generating circuit (103) generative circuit work institute by ripple device (102)
All clock control signals needed, section clock signal are converted into modulator circuit demand through low pressure-high-voltage converter (104)
High voltage clock signal；It is characterized in that：The switched-capacitor integrator with reset terminal in second order sigma Delta modulator (101) is included mutually
Cascade phase inverter is mended, the complementary cascade phase inverter includes the first PMOS and the first NMOS tube, in the first PMOS
The source for the second NMOS tube and the second PMOS, the drain terminal of the second NMOS tube and the first PMOS of being connected between pipe and the first NMOS tube
End is connected, and the source of the second PMOS is connected with the drain terminal of the first NMOS tube, the source of the second NMOS tube and the second PMOS
Drain terminal is connected, and the grid end of the second NMOS tube meets supply voltage VDD, the second gate pmos end ground connection GND；
The desampling fir filter (102) is made up of ripple counter (102-1) and accumulator (102-2), the accumulator
(102-2) is made up of full adder and d type flip flop, and the 1bit numeral outputs of second order sigma Delta modulator (101) are sent to ripple counter
(102-1), the high level of 1bit numeral outputs is counted by ripple counter (102-1), ripple counter (102-1)
Output is sent to accumulator (102-2), and the output of accumulator (102-2) is N-bit numeral output；Ripple counter (102-
1) triggered respectively in the rising edge and trailing edge of clock with accumulator (102-2).
2. the increment Sigma-Delta analog to digital conversion circuits according to claim 1 based on complementary cascade phase inverter,
It is characterized in that：The second order sigma Delta modulator (101) includes first and second summing circuit (101-1,101-3), and first and
Two switched-capacitor integrators (101-2,101-4) with reset terminal, 1 bit comparator (101-5) and first and second 1 digit mould turn
The output of parallel operation (101-6,101-7), input voltage VIN and the one 1 digit weighted-voltage D/A converter (101-6) is in the first summing circuit
Summation operation is carried out in (101-1), operation result is input in the switched-capacitor integrator (101-2) of first band reset terminal, the
The output of one switched-capacitor integrator (101-2) with reset terminal is with the output of the 2nd 1 digit weighted-voltage D/A converter (101-7) second
Summation operation is carried out in summing circuit (101-3), operation result is input to the second switched-capacitor integrator (101- with reset terminal
4) in, the output of the second switched-capacitor integrator (101-4) with reset terminal is sent in 1 bit comparator (101-5)；First and
Two switched-capacitor integrators (101-2,101-4) with reset terminal are adopted by the first to the 6th switch (S1, S2, S3, S4, S5, S6)
Sample electric capacity (CS), integrating capacitor (CI), correlated-double-sampling electric capacity (CC) and complementary cascade phase inverter composition.
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| CN104901700B (en) * | 2015-05-12 | 2018-04-20 | 清华大学 | The total word modules Sigma Delta modulators realized based on phase inverter |
| CN108156401B (en) * | 2017-12-19 | 2020-07-28 | 重庆湃芯创智微电子有限公司 | Low power consumption compact digital decimation filter for CMOS image sensor |
| CN108199718B (en) * | 2018-03-30 | 2023-11-14 | 福州大学 | Capacitive sensor detection method based on Sigma-Delta modulation |
| CN108881754B (en) * | 2018-07-19 | 2020-07-31 | 重庆湃芯创智微电子有限公司 | Down-sampling filter for realizing correlated double sampling in digital domain |
| CN108712172B (en) * | 2018-07-26 | 2023-06-23 | 福州大学 | Incremental Sigma-Delta digital-to-analog converter |
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| US7046039B1 (en) * | 2001-11-29 | 2006-05-16 | Cypress Semiconductor Corporation | Class AB analog inverter |
| CN102291103A (en) * | 2011-07-05 | 2011-12-21 | 浙江大学 | Dynamic body biasing class-C inverter and application thereof |
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| US20100321094A1 (en) * | 2010-08-29 | 2010-12-23 | Hao Luo | Method and circuit implementation for reducing the parameter fluctuations in integrated circuits |
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| US7046039B1 (en) * | 2001-11-29 | 2006-05-16 | Cypress Semiconductor Corporation | Class AB analog inverter |
| CN102291103A (en) * | 2011-07-05 | 2011-12-21 | 浙江大学 | Dynamic body biasing class-C inverter and application thereof |
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