CN203278797U - Zero optimization integrator circuit - Google Patents
Zero optimization integrator circuit Download PDFInfo
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- CN203278797U CN203278797U CN 201320295736 CN201320295736U CN203278797U CN 203278797 U CN203278797 U CN 203278797U CN 201320295736 CN201320295736 CN 201320295736 CN 201320295736 U CN201320295736 U CN 201320295736U CN 203278797 U CN203278797 U CN 203278797U
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Abstract
The utility model discloses a zero optimization integrator circuit which is suitable for a Sigma-Delta ADC circuit. The circuit comprises a clock generation sub circuit, a feedback sub circuit, a sampling sub circuit and an integration amplifier. The integration amplifier comprises an amplifier, an integration capacitor, a first capacitor, a first switch and a second switch. A positive phase input terminal of the amplifier is connected with an external common-mode voltage terminal and an inverting input terminal is connected with the feedback sub circuit, the sampling sub circuit, one end of the integration capacitor and one end of the first switch respectively. The other end of the first switch is connected with one end of the second switch and one end of the first capacitor. The other end of the second switch is connected with the external common-mode voltage terminal. The other end of the integration capacitor and the other end of the first capacitor are connected with an output terminal of the amplifier. The feedback sub circuit comprises a third switch, a fourth switch and a second capacitor. By using the integrator circuit of the utility model, a chip area occupied by the circuit is small; a parasitic capacitor is not sensitive; power consumption is low and design cost is low too.
Description
Technical field
The utility model relates to integrated circuit fields, optimizes integrator circuit the zero point that relates more specifically to a kind of Sigma-Delta of being applicable to adc circuit.
Background technology
Analog to digital converter (ADC) plays very important effect in signal is processed.Need a large amount of analog to digital converters in fields such as digital audio, Digital Television, Image Coding and frequency synthesis.Because size and the bias voltage of very lagre scale integrated circuit (VLSIC) constantly reduces, the precision of analogue device and dynamic range also constantly reduce, for realizing that high-resolution ADC is a kind of challenge.And the Sigma-delta adc circuit exchanges precision for speed, can realize higher resolution, therefore is widely used in practice.The Sigma-delta adc circuit adopts oversampling technique and noise shaping technology to combine, and to the quantizing noise double inhibition, thereby realizes the high precision analogue conversion.The zero point of traditional noise transfer function is all at the z=0 place, can not the noise in signal bandwidth effectively be compressed, in order further to improve signal to noise ratio, can adding zero point at Delta Sigma noise transfer function, thereby reduced the amplitude of noise transfer function in signal bandwidth, therefore can better to noise shaping, further improve the signal to noise ratio of system by optimizing zero point; Namely realize the better noise shaping of Sigma-delta adc circuit by optimizing integrator circuit the zero point that is applicable to the Sigma-Delta adc circuit.
Optimize the structure of integrator circuit the zero point of the existing Sigma-delta of being applicable to adc circuit as shown in Figure 1.It comprises clock generating electronic circuit, feedback sub-circuit, sampling electronic circuit and integral amplifier; The clock generating electronic circuit is connected with feedback sub-circuit and sampling electronic circuit respectively, control the work of feedback sub-circuit and sampling electronic circuit to produce clock pulse, and the clock generating electronic circuit has the first output L1 and the second output L2, the clock pulse that the first output L1 and the second output L2 output are complementary; Feedback sub-circuit is connected with feedback end and the integral amplifier of Sigma-Delta adc circuit respectively, the sampling electronic circuit is connected with external signal output and integral amplifier respectively, and the voltage signal that integral amplifier is exported sampling electronic circuit and feedback sub-circuit is by establishing their certainty ratio Coefficient Integrals.Wherein, feedback sub-circuit comprises four switch S 1, S2, S3, S4, capacitor C 12, and an end of switch S 1 is connected with the feedback end of Sigma-delta adc circuit, this feedback end output feedback voltage signal V
ZERO1To feedback sub-circuit, the end of switch S 2, S3 respectively with outside common-mode voltage end V
CM1Connect; The composition structure of sampling electronic circuit and the composition structure of feedback sub-circuit are identical, it comprises four switch S 5, S6, S7, S8, capacitor C 11, difference only is that an end of switch S 5 is connected with the external signal output, this external signal output output voltage signal V
IN1To the electronic circuit of sampling; Integral amplifier comprises amplifier OP1 and integrating capacitor Cf1, the normal phase input end of amplifier OP1 and outside common-mode voltage end V
CM1Connect, its inverting input is connected with feedback sub-circuit with the sampling electronic circuit respectively, and integrating capacitor Cf1 is connected across between the inverting input and output of amplifier OP1.Separately, optimize the concrete annexation of each device of integrator circuit and the annexation between the first output L1, the second output L2 and each switch the zero point of the existing Sigma-delta of being applicable to adc circuit as shown in Figure 1, carefully do not state at this.
In the foregoing circuit structure, it is closed when controlling clock pulse and being high level that each switch is it, disconnect during low level, and feedback voltage signal V
ZERO1Phase place and input voltage signal V
IN1Voltage-phase opposite, the output output voltage V of amplifier OP1
OUT1The course of work of above-mentioned existing Sigma-delta ADC switched-capacitor integrator circuit is as follows:
Sample phase: the clock pulse of the first output L1 output of clock generating electronic circuit is high level, and the clock pulse of the second output L2 output is low level, at this moment switch S 1, S3, S5, S7 closure, capacitor C 11 sampling input voltage signal V
IN1, capacitor C 12 sampling feedback voltage signal V
ZERO1, and the voltage signal after sampling converts charge storage in capacitor C 11, C12.
Integral process: the clock pulse of the first output L1 output of clock generating electronic circuit is low level, the clock pulse high-low level of the second output L2 output, this moment, switch S 2, S4, S6, S8 were closed, capacitor C 11, C12 to the integrating capacitor Cf1 of integral amplifier, convert the charge transfer on it to output voltage V simultaneously
OUT1
Analyze by the z domain model, the transfer function of above-mentioned integrator circuit is:
The purpose of optimizing in order to satisfy noise shaping, the gain coefficient C11/Cf1 that optimizes integrator circuit zero point is approximately 10
-1The order of magnitude, C12/Cf1 is approximately 10
-2The order of magnitude or less (can realize the purpose optimized zero point in conjunction with Delta Sigma modulating system), can be found out by (1) formula, existing integrator circuit is for input voltage signal V
IN1, its gain coefficient is C11/Cf1, for feedback voltage signal V
ZERO1Be C12/Cf1, in order to satisfy the requirement of noise shaping, gain coefficient is approximately 10
-1The order of magnitude.Suppose that here the gain coefficient C11/Cf1 that needs is that 1/10, C12/Cf is 1/500, integrating capacitor Cf1 value 10pF, C11 is 1pF so, C12 is 0.02pF; Because the capacitance of the minimum precision that technique can realize is limited, so the value of capacitor C 12 is too little, and gain coefficient C12/Cf1 ratio can produce very large error; Need to increase 10-20 times (its value depends on the minimum precision of the attainable electric capacity of technique) if reduce the capacitance of error capacitor C 12, for example, if it is constant that the gain coefficient of integrating circuit is optimized in maintenance zero point, capacitor C 2 is 0.2pF, C1, Cf need to increase identical multiple, and namely Cf is 100pF, and C1 is 10pF, therefore the appearance value of all electric capacity has all increased, and has increased widely chip occupying area; In addition, jumbo capacitor charge and discharge can increase the power consumption of circuit, has also limited the Slew Rate of operational amplifier, causes the decline of circuit performance, affects the precision of integrator.
Therefore, be necessary to provide a kind of zero point of the improved Sigma-Delta of being applicable to adc circuit to optimize integrator circuit and overcome defects.
The utility model content
The purpose of this utility model is to provide optimizes integrator circuit a kind of zero point, and it is applicable to the Sigma-Delta adc circuit, and this circuit chip occupying area is little, and parasitic capacitance is insensitive, low in energy consumption and design cost is low.
for achieving the above object, the utility model provides optimizes integrator circuit a kind of zero point, it is applicable to the Sigma-Delta adc circuit, comprise the clock generating electronic circuit, feedback sub-circuit, sampling electronic circuit and integral amplifier, described clock generating electronic circuit respectively with described feedback sub-circuit, integral amplifier and sampling electronic circuit connect, control described feedback sub-circuit to produce clock pulse, the work of integral amplifier and sampling electronic circuit, and described clock generating electronic circuit has the first output and the second output, the clock pulse that described the first output and the output of the second output are complementary, described feedback sub-circuit is connected with feedback end and the integral amplifier of Sigma-Delta adc circuit respectively, described sampling electronic circuit is connected with external signal output and integral amplifier respectively, described integral amplifier is pressed the preset proportion Coefficient Integrals to the voltage signal of described sampling electronic circuit and feedback sub-circuit output, wherein, described integral amplifier is connected with described clock generating electronic circuit, the clock pulse that described clock generating electronic circuit produces is controlled the work of described integral amplifier, and described integral amplifier comprises amplifier, integrating capacitor, the first electric capacity, the first switch and second switch, the normal phase input end of described amplifier is connected with outside common-mode voltage end, its inverting input is connected with feedback sub-circuit, sampling electronic circuit, an end of integrating capacitor and an end of the first switch respectively, the other end of described the first switch is connected with an end of described second switch and the first electric capacity, the other end of described second switch is connected with outside common-mode voltage end, and described integrating capacitor is connected with the output of described amplifier with the other end of the first electric capacity, described feedback sub-circuit comprises the 3rd switch, the 4th switch and the second electric capacity, described the 3rd switch one end is connected with the feedback end of Sigma-DeltaADC circuit, the other end is connected with an end of the second electric capacity and an end of the 4th switch, the other end of described the 4th switch is connected with outside common-mode voltage end, and the other end of described the second electric capacity is connected with the inverting input of amplifier.
Preferably, described the first switch, the 3rd switch are connected with the first output of clock generating electronic circuit, described second switch, the 4th switch are connected with the second output of clock generating electronic circuit, the closure of described the first switch of clock pulse control, second switch, the 3rd switch and the 4th switch of described clock generating electronic circuit output/disconnection, and described the first switch, second switch, the 3rd switch and the 4th switch are all closed when the control clock pulse is high level.
preferably, described sampling electronic circuit comprises the 5th switch, the 6th switch, minion is closed, the 8th switch and the 3rd electric capacity, described the 5th switch one end is connected with the external signal output, the other end is connected with an end of the 3rd electric capacity and an end of the 6th switch, the other end of described the 6th switch is connected with outside common-mode voltage end, the end that the other end of described the 3rd electric capacity and described minion are closed and an end of the 8th switch are connected, the other end that described minion is closed is connected with the inverting input of amplifier, the other end of described the 8th switch is connected with outside common-mode voltage end.
Preferably, described the 5th switch, the 8th switch are connected with the first output of clock generating electronic circuit, described the 6th switch, minion are closed and are connected with the second output of clock generating electronic circuit, the clock pulse of described clock generating electronic circuit output is controlled described the 5th switch, the 6th switch, minion is closed and the closure of the 8th switch/disconnection, and described the 5th switch, the 6th switch, minion pass and the 8th switch are all closed when the control clock pulse is high level.
compared with prior art, optimize integrator circuit zero point of the present utility model and also comprise the first electric capacity in described integrating amplification circuit, by coordinating of described the first electric capacity and integrating amplification circuit, make the electric capacity of optimizing integrator circuit whole zero point and only need low capacity can realize optimization to zero point, and then make total appearance value of whole circuit electric capacity used reduce, and because the power consumption of capacitor charge and discharge consumption is directly proportional to the appearance value size of electric capacity, therefore the power consumption that discharges and recharges consumption of little electric capacity also reduces relatively, the parasitic capacitance of little electric capacity is smaller simultaneously, the amplifier Slew Rate is required to reduce, therefore the performance index of circuit have been improved.
By following description also by reference to the accompanying drawings, it is more clear that the utility model will become, and these accompanying drawings are used for explaining the utility model.
Description of drawings
Fig. 1 optimizes the integrator circuit structure chart existing zero point.
Fig. 2 optimizes the integrator circuit structure chart zero point of the present utility model.
Embodiment
With reference now to accompanying drawing, describe embodiment of the present utility model, in accompanying drawing, similar element numbers represents similar element.As mentioned above, the utility model provides optimizes integrator circuit a kind of zero point, and this circuit chip occupying area is little, and parasitic capacitance is insensitive, low in energy consumption and design cost is low.
Please refer to Fig. 2, Fig. 2 is that the utility model is optimized the integrator circuit structure chart zero point.As shown in the figure, optimize integrator circuit zero point of the present utility model and be applicable to the Sigma-delta adc circuit, optimize integrator circuit described zero point and comprise clock generating electronic circuit, feedback sub-circuit, sampling electronic circuit and integral amplifier; The clock generating electronic circuit is connected with feedback sub-circuit and sampling electronic circuit respectively, control the work of feedback sub-circuit and sampling electronic circuit to produce clock pulse, and the clock generating electronic circuit has the first output Φ 1 and the second output Φ 2, the clock pulse that the first output Φ 1 and the second output Φ 2 outputs are complementary, when namely the clock pulse of the first output Φ 1 output is high level, the clock pulse of described the second output Φ 2 outputs is low level, and vice versa; The sampling electronic circuit is connected with external signal output and integral amplifier respectively, with the voltage signal V to outside signal output part input
INSample and keep the sampling after voltage signal; Described feedback sub-circuit is connected with feedback end and the integral amplifier of Sigma-Delta adc circuit respectively, to complete the noise shaping process in conjunction with the sampling electronic circuit, improves the signal to noise ratio of circuit; Described integral amplifier is to the signal of input integral amplifier Coefficient Integrals by a certain percentage.
Particularly, described integral amplifier comprises amplifier OP, integrating capacitor Cf, the first capacitor C 1, the first K switch 1 and second switch K2; The normal phase input end of described amplifier OP is connected with outside common-mode voltage end VCM, and its inverting input is connected with feedback sub-circuit, sampling electronic circuit, the end of integrating capacitor Cf and an end of the first K switch 1 respectively; The other end of described the first K switch 1 is connected with an end of described second switch K2 and the first capacitor C 1, and the closure of described first K switch 1 of clock pulse control of described the first output Φ 1 output/disconnection; The other end of described second switch K2 is connected with outside common-mode voltage end VCM, and the closure of the described second switch K2 of clock pulse control of described the second output Φ 2 outputs/disconnection.Described feedback sub-circuit comprises the 3rd K switch 3, the 4th K switch 4 and the second capacitor C 2, described the 3rd K switch 3 one ends are connected with the feedback end of Sigma-Delta adc circuit, the other end is connected with an end of the second capacitor C 2 and an end of the 4th K switch 4, the closure of described the 3rd K switch 3 of clock pulse control of described the first output Φ 1 output/disconnection, the feedback end output feedback voltage signal V of Sigma-Delta adc circuit
ZEROTo described feedback sub-circuit; The other end of described the 4th K switch 4 is connected with outside common-mode voltage end VCM, and the clock pulse of described the second output Φ 2 outputs is controlled the closure of described the 4th K switch 4/disconnection; The other end of described the second capacitor C 2 is connected with the inverting input of amplifier OP.Described sampling electronic circuit comprises the 5th K switch 5, the 6th K switch 6, minion pass K7, the 8th switch K8 and the 3rd capacitor C 3; Described the 5th K switch 5 one ends are connected with the external signal output, the other end is connected with an end of the 3rd capacitor C 3 and an end of the 6th K switch 6, and the closure of described the 5th K switch 5 of clock pulse control of described the first output Φ 1 output/disconnection, thereby described external signal output output voltage signal V
INTo described sampling electronic circuit; The other end of described the 6th K switch 6 and outside common-mode voltage end V
CMConnect, and the closure of described the 6th K switch 6 of clock pulse control of described the second output Φ 2 outputs/disconnection; The other end of described the 3rd capacitor C 3 is connected with the end that described minion is closed K7 and the 8th switch K8, the other end of described the 8th switch K8 and outside common-mode voltage end V
CMConnect, and the closure of described the 8th switch K8 of clock pulse control of described the first output Φ 1 output/disconnection; The other end that described minion is closed K7 is connected with the inverting input of described amplifier OP, and the closure of the described minion of the clock pulse control pass K7 of described the second output Φ 2 outputs/disconnection; Thereby described sampling electronic circuit is to described voltage signal V
INSample, and the signal after sampling remains on described the 3rd capacitor C 3.In preferred implementation of the present utility model, it is closed when controlling clock pulse and being high level that each described switch is it, disconnects during low level.
Refer again to Fig. 2, describe the course of work of optimizing integrator circuit zero point of the present utility model.
Sample phase; The clock pulse of the first output Φ 1 output of clock generating electronic circuit is high level, and the clock pulse of the second output Φ 2 outputs is low level, at this moment the 3rd capacitor C 3 sampling input voltage signal V
IN, and convert electric charge C3*V to
INBe stored in the 3rd capacitor C 3; The second capacitor C 2 sampling input voltage signal V
ZERO, and with electric charge C2*V
ZEROBe delivered on integrating capacitor Cf and the first capacitor C 1 in parallel by operational amplifier OP.
Integral process: the clock pulse of the first output Φ 1 output of clock generating electronic circuit is low level, and the clock pulse of the second output Φ 2 outputs is high level, and described the 3rd left pole plate of capacitor C 3 meets common-mode voltage V
CM, right pole plate connects the OP reverse input end of amplifier, and under the effect of amplifier OP, the electric charge that is stored on the 3rd capacitor C 3 is transferred to integrating capacitor Cf, and the first capacitor C 1 keeps output voltage; The second left pole plate of capacitor C 2 meets common-mode voltage V
CM, right pole plate connects the reverse input end of amplifier OP, under the effect of amplifier OP, draws electric charge from integrating capacitor Cf, and making the 3rd capacitor C 3 left and right polar plate voltages is all finally common-mode voltage V
CM, the first capacitor C 1 keeps output voltage simultaneously.
Analyze by the z domain model, the transfer function of optimizing integrator circuit the zero point for the Sigma-Delta adc circuit of the present utility model is:
Still satisfy the gain coefficient of assumed condition, namely
Be 1/10,
Be 1/500, can realize optimizing zero point; Each electric capacity can value C3=1pF, Cf=9.5pF, C1=0.5pF, C2=0.38pF, can find out in above-mentioned value, the capacitance of each capacitor C 1 of the present utility model, C2, C3, Cf is all very little, make optimize with his capacitance of device circuit whole zero point also very little, and because the power consumption of capacitor charge and discharge consumption is directly proportional to the appearance value size of electric capacity, therefore the power consumption that discharges and recharges consumption of little electric capacity also reduces relatively, the parasitic capacitance of little electric capacity is smaller simultaneously, and the amplifier Slew Rate is required to reduce, and has therefore improved the performance index of circuit.
Abovely in conjunction with most preferred embodiment, the utility model is described, but the utility model is not limited to the embodiment of above announcement, and should contains various modification, equivalent combinations of carrying out according to essence of the present utility model.
Claims (4)
1. optimize integrator circuit a zero point, be applicable to the Sigma-Delta adc circuit, comprise the clock generating electronic circuit, feedback sub-circuit, sampling electronic circuit and integral amplifier, described clock generating electronic circuit respectively with described feedback sub-circuit, integral amplifier and sampling electronic circuit connect, control described feedback sub-circuit to produce clock pulse, the work of integral amplifier and sampling electronic circuit, and described clock generating electronic circuit has the first output and the second output, the clock pulse that described the first output and the output of the second output are complementary, described feedback sub-circuit is connected with feedback end and the integral amplifier of Sigma-Delta adc circuit respectively, described sampling electronic circuit is connected with external signal output and integral amplifier respectively, described integral amplifier is pressed the preset proportion Coefficient Integrals to the voltage signal of described sampling electronic circuit and feedback sub-circuit output, it is characterized in that, described integral amplifier is connected with described clock generating electronic circuit, the clock pulse that described clock generating electronic circuit produces is controlled the work of described integral amplifier, and described integral amplifier comprises amplifier, integrating capacitor, the first electric capacity, the first switch and second switch, the normal phase input end of described amplifier is connected with outside common-mode voltage end, its inverting input is connected with feedback sub-circuit, sampling electronic circuit, an end of integrating capacitor and an end of the first switch respectively, the other end of described the first switch is connected with an end of described second switch and the first electric capacity, the other end of described second switch is connected with outside common-mode voltage end, and described integrating capacitor is connected with the output of described amplifier with the other end of the first electric capacity, described feedback sub-circuit comprises the 3rd switch, the 4th switch and the second electric capacity, described the 3rd switch one end is connected with the feedback end of Sigma-Delta adc circuit, the other end is connected with an end of the second electric capacity and an end of the 4th switch, the other end of described the 4th switch is connected with outside common-mode voltage end, and the other end of described the second electric capacity is connected with the inverting input of amplifier.
2. optimize integrator circuit zero point as claimed in claim 1, it is characterized in that, described the first switch, the 3rd switch are connected with the first output of clock generating electronic circuit, described second switch, the 4th switch are connected with the second output of clock generating electronic circuit, the closure of described the first switch of clock pulse control, second switch, the 3rd switch and the 4th switch of described clock generating electronic circuit output/disconnection, and described the first switch, second switch, the 3rd switch and the 4th switch are all closed when the control clock pulse is high level.
3. optimize integrator circuit zero point as claimed in claim 2, it is characterized in that, described sampling electronic circuit comprises the 5th switch, the 6th switch, minion is closed, the 8th switch and the 3rd electric capacity, described the 5th switch one end is connected with the external signal output, the other end is connected with an end of the 3rd electric capacity and an end of the 6th switch, the other end of described the 6th switch is connected with outside common-mode voltage end, the end that the other end of described the 3rd electric capacity and described minion are closed and an end of the 8th switch are connected, the other end that described minion is closed is connected with the inverting input of amplifier, the other end of described the 8th switch is connected with outside common-mode voltage end.
4. optimize integrator circuit zero point as claimed in claim 3, it is characterized in that, described the 5th switch, the 8th switch are connected with the first output of clock generating electronic circuit, described the 6th switch, minion are closed and are connected with the second output of clock generating electronic circuit, the clock pulse of described clock generating electronic circuit output is controlled described the 5th switch, the 6th switch, minion is closed and the closure of the 8th switch/disconnection, and described the 5th switch, the 6th switch, minion pass and the 8th switch are all closed when the control clock pulse is high level.
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| CN 201320295736 CN203278797U (en) | 2013-05-27 | 2013-05-27 | Zero optimization integrator circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103312333A (en) * | 2013-05-27 | 2013-09-18 | 四川和芯微电子股份有限公司 | Zero-optimization integrator circuit suitable for Sigma-Delta ADC (Analog To Digital Conversion) circuit |
| CN109510601A (en) * | 2017-09-14 | 2019-03-22 | 深圳指芯智能科技有限公司 | Switching capacity subtraction circuit and sensor device |
| CN115882864A (en) * | 2021-09-29 | 2023-03-31 | 圣邦微电子（北京）股份有限公司 | Switch capacitor integrator circuit capable of preventing overshoot and undershoot |
| TWI812949B (en) * | 2020-06-03 | 2023-08-21 | 美商高通公司 | Circuits and methods providing a switched capacitor integrator and system on chip (soc) including the circuits |
-
2013
- 2013-05-27 CN CN 201320295736 patent/CN203278797U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103312333A (en) * | 2013-05-27 | 2013-09-18 | 四川和芯微电子股份有限公司 | Zero-optimization integrator circuit suitable for Sigma-Delta ADC (Analog To Digital Conversion) circuit |
| CN109510601A (en) * | 2017-09-14 | 2019-03-22 | 深圳指芯智能科技有限公司 | Switching capacity subtraction circuit and sensor device |
| TWI812949B (en) * | 2020-06-03 | 2023-08-21 | 美商高通公司 | Circuits and methods providing a switched capacitor integrator and system on chip (soc) including the circuits |
| CN115882864A (en) * | 2021-09-29 | 2023-03-31 | 圣邦微电子（北京）股份有限公司 | Switch capacitor integrator circuit capable of preventing overshoot and undershoot |
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Granted publication date: 20131106 Termination date: 20170527 |