CN203278793U - Integrator circuit - Google Patents
Integrator circuit Download PDFInfo
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- CN203278793U CN203278793U CN 201320295234 CN201320295234U CN203278793U CN 203278793 U CN203278793 U CN 203278793U CN 201320295234 CN201320295234 CN 201320295234 CN 201320295234 U CN201320295234 U CN 201320295234U CN 203278793 U CN203278793 U CN 203278793U
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Abstract
The utility model discloses an integrator circuit. The integrator circuit is suitable for a Sigma-delta ADC circuit. The circuit comprises a clock generation sub circuit, a feedback sub circuit, a sampling sub circuit and an integration amplifier. The integration amplifier comprises an amplifier, an integration capacitor, a first capacitor, a first switch and a second switch. A positive phase input terminal of the amplifier is connected with an external common-mode voltage terminal and an inverting input terminal is connected with the feedback sub circuit, the sampling sub circuit, one end of the integration capacitor and one end of the first switch respectively. The other end of the first switch is connected with one end of the second switch and one end of the first capacitor. The other end of the second switch is connected with the external common-mode voltage terminal. The other end of the integration capacitor and the other end of the first capacitor are connected with an output terminal of the amplifier. By using the integrator circuit of the utility model, a chip area occupied by the circuit is small; a parasitic capacitor is not sensitive; power consumption is low and design cost is low too.
Description
Technical field
The utility model relates to integrated circuit fields, relates more specifically to a kind of integrator circuit of the Sigma-Delta of being applicable to adc circuit.
Background technology
Analog to digital converter (ADC) plays very important effect in signal is processed.Need a large amount of analog to digital converters in fields such as digital audio, Digital Television, Image Coding and frequency synthesis.Because size and the bias voltage of very lagre scale integrated circuit (VLSIC) constantly reduces, the precision of analogue device and dynamic range also constantly reduce, for realizing that high-resolution ADC is a kind of challenge.And Sigma-delta ADC exchanges precision for speed, can realize higher resolution, therefore is widely used in practice.Sigma-delta ADC adopts oversampling technique and noise shaping technology to combine, and to the quantizing noise double inhibition, thereby realizes the high precision analogue conversion.The structure that Sigma-delta ADC adopts is that the cascade of multiple-pole switch capacitance integrator and a coarse quantizer that is arranged in feedback control loop consist of.Wherein the multiple-pole switch capacitance integrator is the pith of completing noise shaping.
The structure of the integrator circuit of the existing Sigma-delta of being applicable to adc circuit (also being Sigma-delta ADC switched-capacitor integrator circuit) as shown in Figure 1.It comprises clock generating electronic circuit, feedback sub-circuit, sampling electronic circuit and integral amplifier; The clock generating electronic circuit is connected with feedback sub-circuit and sampling electronic circuit respectively, control the work of feedback sub-circuit and sampling electronic circuit to produce clock pulse, and the clock generating electronic circuit has the first output L1 and the second output L2, the clock pulse that the first output L1 and the second output L2 output are complementary; Feedback sub-circuit is connected with feedback end and the integral amplifier of Sigma-Delta adc circuit respectively, the sampling electronic circuit is connected with external signal input and integral amplifier respectively, and integral amplifier is pressed the preset proportion Coefficient Integrals to the voltage signal of sampling electronic circuit and feedback sub-circuit output.Wherein, feedback sub-circuit comprises four switch S 1, S2, S3, S4, capacitor C 12, and an end of switch S 1 is connected with the feedback end of Sigma-delta adc circuit, this feedback end output feedback voltage signal V
REF1To feedback sub-circuit, the end of switch S 2, S3 respectively with outside common-mode voltage end V
CM1Connect; The composition structure of sampling electronic circuit and the composition structure of feedback sub-circuit are identical, it comprises four switch S 5, S6, S7, S8, capacitor C 11, difference only is that an end of switch S 5 is connected with the external signal input, this external signal input output voltage signal V
IN1To the electronic circuit of sampling; Integral amplifier comprises amplifier OP1 and integrating capacitor Cf1, the normal phase input end of amplifier OP1 and outside common-mode voltage end V
CM1Connect, its inverting input is connected with feedback sub-circuit with the sampling electronic circuit respectively, and integrating capacitor Cf1 is connected across between the inverting input and output of amplifier OP1.Separately, the concrete annexation of existing each device of integrator circuit that is applicable to the Sigma-delta adc circuit and the annexation between the first output L1, the second output L2 and each switch are not carefully stated at this as shown in Figure 1.
In the foregoing circuit structure, it is closed when controlling clock pulse and being high level that each switch is it, disconnect during low level, and feedback voltage signal V
REF1Phase place and input voltage signal V
IN1Voltage-phase opposite, the output output voltage V of amplifier OP1
OUT1The course of work of above-mentioned existing Sigma-delta ADC switched-capacitor integrator circuit is as follows:
Sample phase: the clock pulse of the first output L1 output of clock generating electronic circuit is high level, and the clock pulse of the second output L2 output is low level, at this moment switch S 1, S3, S5, S7 closure, capacitor C 11 sampling input voltage signal V
IN1, capacitor C 12 sampling feedback voltage signal V
REF1, and the voltage signal after sampling converts charge storage in capacitor C 11, C12.
Integral process: the clock pulse of the first output L1 output of clock generating electronic circuit is low level, the clock pulse high-low level of the second output L2 output, this moment, switch S 2, S4, S6, S8 were closed, capacitor C 11, C12 to the integrating capacitor Cf1 of integral amplifier, convert the charge transfer on it to output voltage V simultaneously
OUT1
Analyze by the z domain model, the transfer function of above-mentioned switch capacitance integrator circuit is:
Can be found out by (1) formula, existing switched-capacitor integrator is for input voltage signal V
IN1, its gain coefficient is C11/Cf1, for feedback voltage signal V
REF1Be C12/Cf1, in order to satisfy the requirement of noise shaping, gain coefficient is approximately 10
-1The order of magnitude.Suppose that here above-mentioned gain coefficient is all 1/10, because the capacitance of the minimum precision that technique can realize is limited, simultaneously in order to make circuit obtain high signal to noise ratio, capacitor C 11, C12 are can not value too little, if value is 2pF, in order to satisfy the requirement of gain coefficient, integrating capacitor approximately appearance value is 20pF so, and whole circuit needs the electric capacity of 24pF altogether.The electric capacity of 24pF has taken very large chip area, has greatly increased design cost; And the parasitic capacitance of large electric capacity is larger, can affect the Slew Rate of amplifier, affects the precision of integrator; In addition, circuit has increased the power consumption of circuit to large capacitor charge and discharge.
Therefore be necessary to provide and look for a chip occupying area little, parasitic capacitance is insensitive, and the integrator circuit that is applicable to the Sigma-delta adc circuit low in energy consumption overcomes defects.
The utility model content
The purpose of this utility model is to provide a kind of integrator circuit of the Sigma-delta of being applicable to adc circuit, and this circuit chip occupying area is little, and parasitic capacitance is insensitive, and is low in energy consumption and design cost is low.
for achieving the above object, the utility model provides a kind of integrator circuit, and this integrator circuit is applicable to the Sigma-delta adc circuit, it comprises the clock generating electronic circuit, feedback sub-circuit, sampling electronic circuit and integral amplifier, described clock generating electronic circuit respectively with described feedback sub-circuit, sampling electronic circuit and integral amplifier connect, control described feedback sub-circuit to produce clock pulse, the work of sampling electronic circuit and integral amplifier, and described clock generating electronic circuit has the first output and the second output, the clock pulse that described the first output and the output of the second output are complementary, described feedback sub-circuit is connected with feedback end and the integral amplifier of Sigma-Delta adc circuit respectively, described sampling electronic circuit is connected with external signal input and integral amplifier respectively, described integral amplifier is pressed the preset proportion Coefficient Integrals to the voltage signal of described sampling electronic circuit and feedback sub-circuit output, wherein, described integral amplifier comprises amplifier, integrating capacitor, the first electric capacity, the first switch and second switch, the normal phase input end of described amplifier is connected with outside common-mode voltage end, its inverting input respectively with feedback sub-circuit, the sampling electronic circuit, one end of one end of integrating capacitor and the first switch connects, the other end of described the first switch is connected with an end of described second switch and the first electric capacity, the other end of described second switch is connected with outside common-mode voltage end, described integrating capacitor is connected with the output of described amplifier with the other end of the first electric capacity.
Preferably, described the first switch is connected with the first output of clock generating electronic circuit, described second switch is connected with the second output of clock generating electronic circuit, the clock pulse of described clock generating electronic circuit output is controlled the closure of described the first switch and second switch/disconnections, and the equal closure when the control clock pulse is high level of described the first switch and second switch.
Preferably, described sampling electronic circuit comprises the 3rd switch, the 4th switch and the second electric capacity, described the 3rd switch one end is connected with the external signal input, the other end is connected with an end of the second electric capacity and an end of the 4th switch, the other end of described the 4th switch is connected with outside common-mode voltage end, and the other end of described the second electric capacity is connected with the inverting input of amplifier.
Preferably, described the 3rd switch is connected with the first output of clock generating electronic circuit, described the 4th switch is connected with the second output of clock generating electronic circuit, the clock pulse of described clock generating electronic circuit output is controlled the closure of described the 3rd switch and the 4th switch/disconnections, and the equal closure when the control clock pulse is high level of described the 3rd switch and the 4th switch.
Preferably, described feedback sub-circuit comprises the 5th switch, the 6th switch and the 3rd electric capacity, described the 5th switch one end is connected with the feedback end of Sigma-Delta adc circuit, the other end is connected with an end of the 3rd electric capacity and an end of the 6th switch, the other end of described the 6th switch is connected with outside common-mode voltage end, and the other end of described the 3rd electric capacity is connected with the inverting input of amplifier.
Preferably, described the 5th switch is connected with the first output of clock generating electronic circuit, described the 6th switch is connected with the second output of clock generating electronic circuit, the clock pulse of described clock generating electronic circuit output is controlled the closure of described the 5th switch and the 6th switch/disconnections, and the equal closure when the control clock pulse is high level of described the 5th switch and the 6th switch.
compared with prior art, integrator circuit of the present utility model is because described integrating amplification circuit also comprises the first electric capacity, by coordinating of described the first electric capacity and integrating amplification circuit, make the gain coefficient of whole integrator circuit smaller, and then make total appearance value of whole circuit electric capacity used greatly reduce, and because the power consumption of capacitor charge and discharge consumption is directly proportional to the appearance value size of electric capacity, therefore the power consumption that discharges and recharges consumption of little electric capacity also reduces relatively, the parasitic capacitance of little electric capacity is smaller simultaneously, the amplifier Slew Rate is required to reduce, therefore the performance index of circuit have been improved.
By following description also by reference to the accompanying drawings, it is more clear that the utility model will become, and these accompanying drawings are used for explaining the utility model.
Description of drawings
Fig. 1 is existing integrator circuit structure chart.
Fig. 2 is integrator circuit structure chart of the present utility model
Embodiment
With reference now to accompanying drawing, describe embodiment of the present utility model, in accompanying drawing, similar element numbers represents similar element.As mentioned above, the utility model provides a kind of integrator circuit, and this circuit chip occupying area is little, and parasitic capacitance is insensitive, and is low in energy consumption and design cost is low.
Please refer to Fig. 2, Fig. 2 is the utility model integrator circuit structure chart.As shown in the figure, integrator circuit of the present utility model is applicable to the Sigma-delta adc circuit, and it comprises clock generating electronic circuit, feedback sub-circuit, sampling electronic circuit and integral amplifier; Described clock generating electronic circuit is connected with described feedback sub-circuit, sampling electronic circuit and integral amplifier respectively, control the work of described feedback sub-circuit, sampling electronic circuit and integral amplifier to produce clock pulse, and the clock generating electronic circuit has the first output Φ 1 and the second output Φ 2, the clock pulse that the first output Φ 1 and the second output Φ 2 outputs are complementary, when namely the clock pulse of the first output Φ 1 output is high level, the clock pulse of described the second output Φ 2 outputs is low level, and vice versa; The sampling electronic circuit is connected with external signal input and integral amplifier respectively, the voltage signal after also keeping sampling with the voltage signal sampling to input; Described feedback sub-circuit is connected with feedback end and the integral amplifier of Sigma-Delta adc circuit respectively, to complete the noise shaping process in conjunction with the sampling electronic circuit, improves the signal to noise ratio of circuit; Described integral amplifier is to the signal of input integral amplifier Coefficient Integrals by a certain percentage.
Particularly, described integral amplifier comprises amplifier OP, integrating capacitor Cf, the first capacitor C 1, the first K switch 1 and second switch K2; The normal phase input end of described amplifier OP is connected with outside common-mode voltage end VCM, and its inverting input is connected with feedback sub-circuit, sampling electronic circuit, the end of integrating capacitor Cf and an end of the first K switch 1 respectively; The other end of described the first K switch 1 is connected with an end of described second switch K2 and the first capacitor C 1, and the closure of described first K switch 1 of clock pulse control of described the first output Φ 1 output/disconnection; The other end of described second switch K2 and outside common-mode voltage end V
CMConnect, and the closure of the described second switch K2 of clock pulse control of described the second output Φ 2 outputs/disconnection.Described sampling electronic circuit comprises the 3rd K switch 3, the 4th K switch 4 and the second capacitor C 2, described the 3rd K switch 3 one ends are connected with the external signal input, the other end is connected with an end of the second capacitor C 2 and an end of the 4th K switch 4, and the clock pulse of described the first output Φ 1 output is controlled the closure of described the 3rd K switch 3/disconnection; The other end of described the 4th K switch 4 and outside common-mode voltage end V
CMConnect, the clock pulse of described the second output Φ 2 outputs is controlled the closure of described the 4th K switch 4/disconnection; The other end of described the second capacitor C 2 is connected with the inverting input of amplifier OP; Described external signal input output voltage signal V
INTo described sampling electronic circuit, thereby described sampling electronic circuit is to described voltage signal V
INSample, and the signal after sampling remains on described the second capacitor C 2.Described feedback sub-circuit comprises the 5th K switch 5, the 6th K switch 6 and the 3rd capacitor C 3, described the 5th K switch 5 one ends are connected with the feedback end of Sigma-Delta adc circuit, the other end is connected with an end of the 3rd capacitor C 3 and an end of the 6th K switch 6, and the closure of described the 5th K switch 5 of clock pulse control of described the first output Φ 1 output/disconnection, the feedback end output feedback voltage signal V of Sigma-Delta adc circuit
REFTo described feedback sub-circuit; The other end of described the 6th K switch 6 is connected with outside common-mode voltage end VCM, and the closure of described the 6th K switch 6 of clock pulse control of described the second output Φ 2 outputs/disconnection; The other end of described the 3rd capacitor C 3 is connected with the inverting input of amplifier OP.In preferred implementation of the present utility model, it is closed when controlling clock pulse and being high level that each described switch is it, disconnects during low level.
Refer again to Fig. 2, describe the course of work of the utility model integrator circuit.Separately, for simplified characterization, at this integral process of analytical sampling electronic circuit only, because feedback sub-circuit is identical with structure and the function of sampling electronic circuit, no longer be repeated in this description at this.
Sample phase: the clock pulse of the first output Φ 1 output of clock generating electronic circuit is high level, and the clock pulse of the second output Φ 2 outputs is low level, at this moment described the second capacitor C 2 sampling input voltage signal V
IN, and with electric charge C2*V
INBe delivered to by amplifier OP on the first capacitor C 1 of integrating capacitor Cf and parallel connection.
Integration phase: the clock pulse of the first output Φ 1 output of clock generating electronic circuit is low level, the clock pulse of the second output Φ 2 outputs is high level, under the effect of described amplifier OP, described the second capacitor C 2 is drawn electric charge from integrating capacitor Cf, and making described the second capacitor C 2 left and right polar plate voltages is all finally common-mode voltage V
CM, simultaneously described the first capacitor C 1 keeps output voltage.
For feedback sub-circuit, principle is identical with process, analyzes by the z domain model, and the transfer function of the switch capacitance integrator circuit after improvement is:
Can be found out by (2) formula, by increasing by first capacitor C 1 that the appearance value is less, can obtain little gain coefficient.If reach the gain coefficient 1/10 of traditional structure hypothesis, and described the second capacitor C 2, the 3rd capacitor C 3 are 2pF, described integrating capacitor Cf be 4pF and the first capacitor C 1 is 1/10 requirement for 1pF just can reach gain coefficient, so altogether use the appearance value of electric capacity to be 9pF, much smaller than the 24pF of traditional structure total capacitance value.And the power consumption that discharges and recharges consumption of little electric capacity also reduces relatively, and the parasitic capacitance of little electric capacity is smaller simultaneously, and the amplifier Slew Rate is required to reduce, and has therefore improved the performance index of circuit.
Abovely in conjunction with most preferred embodiment, the utility model is described, but the utility model is not limited to the embodiment of above announcement, and should contains various modification, equivalent combinations of carrying out according to essence of the present utility model.
Claims (6)
1. integrator circuit, it is applicable to the Sigma-delta adc circuit, comprise the clock generating electronic circuit, feedback sub-circuit, sampling electronic circuit and integral amplifier, described clock generating electronic circuit respectively with described feedback sub-circuit, sampling electronic circuit and integral amplifier connect, control described feedback sub-circuit to produce clock pulse, the work of sampling electronic circuit and integral amplifier, and described clock generating electronic circuit has the first output and the second output, the clock pulse that described the first output and the output of the second output are complementary, described feedback sub-circuit is connected with feedback end and the described integral amplifier of Sigma-Delta adc circuit respectively, described sampling electronic circuit is connected with external signal input and described integral amplifier respectively, described integral amplifier is pressed the preset proportion Coefficient Integrals to the voltage signal of described sampling electronic circuit and feedback sub-circuit output, it is characterized in that, described integral amplifier comprises amplifier, integrating capacitor, the first electric capacity, the first switch and second switch, the normal phase input end of described amplifier is connected with outside common-mode voltage end, its inverting input respectively with described feedback sub-circuit, described sampling electronic circuit, one end of one end of described integrating capacitor and described the first switch connects, the other end of described the first switch is connected with an end of described second switch and the first electric capacity, the other end of described second switch is connected with described outside common-mode voltage end, described integrating capacitor is connected with the other end of described the first electric capacity and the output of described amplifier.
2. integrator circuit as claimed in claim 1, it is characterized in that, described the first switch is connected with the first output of described clock generating electronic circuit, described second switch is connected with the second output of described clock generating electronic circuit, the clock pulse of described clock generating electronic circuit output is controlled the closure of described the first switch and second switch/disconnections, and the equal closure when the control clock pulse is high level of described the first switch and second switch.
3. integrator circuit as claimed in claim 2, it is characterized in that, described sampling electronic circuit comprises the 3rd switch, the 4th switch and the second electric capacity, described the 3rd switch one end is connected with the external signal input, the other end is connected with an end of described the second electric capacity and an end of the 4th switch, the other end of described the 4th switch is connected with described outside common-mode voltage end, and the other end of described the second electric capacity is connected with the inverting input of described amplifier.
4. integrator circuit as claimed in claim 3, it is characterized in that, described the 3rd switch is connected with the first output of described clock generating electronic circuit, described the 4th switch is connected with the second output of described clock generating electronic circuit, the clock pulse of described clock generating electronic circuit output is controlled the closure of described the 3rd switch and the 4th switch/disconnections, and the equal closure when the control clock pulse is high level of described the 3rd switch and the 4th switch.
5. integrator circuit as claimed in claim 4, it is characterized in that, described feedback sub-circuit comprises the 5th switch, the 6th switch and the 3rd electric capacity, described the 5th switch one end is connected with the feedback end of described Sigma-Delta adc circuit, the other end is connected with an end of described the 3rd electric capacity and an end of the 6th switch, the other end of described the 6th switch is connected with described outside common-mode voltage end, and the other end of described the 3rd electric capacity is connected with the inverting input of described amplifier.
6. integrator circuit as claimed in claim 5, it is characterized in that, described the 5th switch is connected with the first output of described clock generating electronic circuit, described the 6th switch is connected with the second output of described clock generating electronic circuit, the clock pulse of described clock generating electronic circuit output is controlled the closure of described the 5th switch and the 6th switch/disconnections, and the equal closure when the control clock pulse is high level of described the 5th switch and the 6th switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320295234 CN203278793U (en) | 2013-05-27 | 2013-05-27 | Integrator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320295234 CN203278793U (en) | 2013-05-27 | 2013-05-27 | Integrator circuit |
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| Publication Number | Publication Date |
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| CN203278793U true CN203278793U (en) | 2013-11-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320295234 Withdrawn - After Issue CN203278793U (en) | 2013-05-27 | 2013-05-27 | Integrator circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103312334A (en) * | 2013-05-27 | 2013-09-18 | 四川和芯微电子股份有限公司 | Integrator circuit suitable for Sigma-Delta ADC (Analog To Digital Conversion) circuit |
| TWI812949B (en) * | 2020-06-03 | 2023-08-21 | 美商高通公司 | Circuits and methods providing a switched capacitor integrator and system on chip (soc) including the circuits |
-
2013
- 2013-05-27 CN CN 201320295234 patent/CN203278793U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103312334A (en) * | 2013-05-27 | 2013-09-18 | 四川和芯微电子股份有限公司 | Integrator circuit suitable for Sigma-Delta ADC (Analog To Digital Conversion) circuit |
| CN103312334B (en) * | 2013-05-27 | 2016-04-13 | 四川和芯微电子股份有限公司 | Be applicable to the integrator circuit of Sigma-Delta adc circuit |
| TWI812949B (en) * | 2020-06-03 | 2023-08-21 | 美商高通公司 | Circuits and methods providing a switched capacitor integrator and system on chip (soc) including the circuits |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20131106 Effective date of abandoning: 20160413 |
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| C25 | Abandonment of patent right or utility model to avoid double patenting |