CN208589978U - Capacity sensor circuit based on Sigma-Delta modulation - Google Patents
Capacity sensor circuit based on Sigma-Delta modulation Download PDFInfo
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- CN208589978U CN208589978U CN201820442933.XU CN201820442933U CN208589978U CN 208589978 U CN208589978 U CN 208589978U CN 201820442933 U CN201820442933 U CN 201820442933U CN 208589978 U CN208589978 U CN 208589978U
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Abstract
The utility model relates to a kind of capacity sensor circuits based on Sigma-Delta modulation, comprising: inductance capacitance, one are for being converted to charge signal for the variable quantity of the inductance capacitance and carrying out the capacitive digital converter of Sigma-Delta modulation to charge signal, one be used to be filtered the digital code stream that the capacitive digital converter exports and down-sampled processing and provide and be used to characterize the decimation filter of digital and sequential control circuit of the digital quantity of the inductance capacitance；The inductance capacitance is connected with the capacitive digital converter, and the decimation filter of digital is connected with the capacitive digital converter, and the sequential control circuit is connected with the capacitive digital converter and the decimation filter of digital respectively；The capacitive digital converter uses Sigma-Delta modulator.The utility model proposes it is a kind of based on Sigma-Delta modulation capacity sensor circuit, have the advantages of simple structure and easy realization.
Description
Technical field
The utility model relates to a kind of capacity sensor circuits based on Sigma-Delta modulation.
Background technique
Capacitance sensor is the sensor for being changed using capacitance with environmental parameter and being changed.It is to utilize capacitor
Non electrical quantity is converted capacitance by principle, and all amounts that can be converted to spacing, area and dielectric constant can be with capacitive
Sensor measures.Capacitance sensor testing capacitance value is generally the even smaller magnitude of pF magnitude, believes in many cases
Parasitic capacitance in number capacity ratio measuring circuit is much smaller, therefore requires capacitor reading circuit relatively high, commonly uses Sigma-
Delta modulator structure is converted.In many cases, since inductance capacitance variable quantity to be measured is small compared to its baseline value
More, directly conversion needs Sigma-Delta modulator to have higher over-sampling rate and longer change-over period, thus electricity to be measured
Appearance range, which also receives, greatly to be limited.
Summary of the invention
The purpose of this utility model is to provide it is a kind of based on Sigma-Delta modulation capacity sensor circuit, with gram
Take defect existing in the prior art.
To achieve the above object, the technical solution of the utility model is: a kind of capacitor biography based on Sigma-Delta modulation
Sensor circuit, comprising: inductance capacitance, one are for being converted to charge signal for the variable quantity of the inductance capacitance and to charge signal
Carry out capacitive digital converter, the digital code stream for exporting to the capacitive digital converter of Sigma-Delta modulation
Be filtered with it is down-sampled processing and offer for characterize the digital quantity of the inductance capacitance decimation filter of digital and
Sequential control circuit；The inductance capacitance is connected with the capacitive digital converter, the decimation filter of digital and the electricity
Hold digital quantizer be connected, the sequential control circuit respectively with the capacitive digital converter and the digital program-con-trolled exchange
Device is connected；The capacitive digital converter uses Sigma-Delta modulator.
In an embodiment of the utility model, the Sigma-Delta modulator is three rank Sigma-Delta modulators.
In an embodiment of the utility model, the three ranks Sigma-Delta modulator includes first order integrator, second
Grade integrator and third level integrator.
In an embodiment of the utility model, the first order integrator, the second level integrator and the third
Grade integrator include a spaning waveguide operational amplifier and respectively with the matched forward path of the spaning waveguide operational amplifier and negative sense access；It is described just
It is symmetrical arranged to access and the negative sense access, and includes: that first switch, second switch, first switch corresponding first are prolonged
Corresponding second delay switch of Shi Kaiguan, second switch, storage capacitor and integrating capacitor.
In an embodiment of the utility model, the both ends of the first delay switch in the forward path respectively with it is described across
The negative input and positive output end for leading amplifier are connected；One end of integrating capacitor in the forward path and the mutual conductance
The positive output end of amplifier is connected, and the other end is connected with one end of the second switch；The other end of the second switch and institute
State one end connection of the storage capacitor in forward path；The other end of storage capacitor in the forward path and the mutual conductance are transported
The negative input put is connected；One end of first switch is connected with one end of the second switch in the forward path, another
Terminate common-mode voltage.
In an embodiment of the utility model, the both ends of the first delay switch in the negative sense access respectively with it is described across
The positive input and negative sense output end for leading amplifier are connected；One end of integrating capacitor in the negative sense access and the mutual conductance
The negative sense output end of amplifier is connected, and the other end is connected with one end of the second switch；The other end of the second switch and institute
State one end connection of the storage capacitor in negative sense access；The other end of storage capacitor in the negative sense access and the mutual conductance are transported
The positive input put is connected；One end of first switch is connected with one end of the second switch in the negative sense access, another
Terminate common-mode voltage.
In an embodiment of the utility model, the input of the forward path in the first order integrator and negative sense access
End is connected with corresponding inductance capacitance and matched compensating electric capacity respectively.
In an embodiment of the utility model, the spaning waveguide operational amplifier uses the current-steering based on inverter structure
OTA。
In an embodiment of the utility model, the decimation filter of digital uses sinc4Filter.
Compared to the prior art, the utility model has the following beneficial effects: provided by the utility model be based on Sigma-
The capacity sensor circuit of Delta modulation, the equivalent input capacitance of capacitor reading circuit is reduced by compensating electric capacity, to reduce
The dynamic range of Sigma-Delta reading circuit consumes, and passes through controlled capacitance matrix-expand capacitive measurement scales.For main body
Circuit module Sigma-Delta modulator is improved current utilization rate, is using the current-steering OTA based on inverter structure
Amplifier output voltage swing is improved, output is all made of high threshold voltage pipe to pipe.It superior design and continues to optimize, realizes that 3 ranks are made an uproar
Sound shaping feature, can survey capacitance range is 0-8pF, has very big application space in micro capacitance field.
Detailed description of the invention
Fig. 1 is the frame diagram of the capacitive sensor system based on Sigma-Delta modulation in the utility model.
Fig. 2 is single order Sigma-Delta modulator structural schematic diagram.
Fig. 3 is third order sigma-delta modulator structural block diagram in the utility model.
Fig. 4 is CDC electrical block diagram in the utility model.
Fig. 5 is that CX capacitance matrix diagram is intended in the utility model.
Fig. 6 is current-steering OTA schematic diagram in the utility model.
Fig. 7 is the first working state schematic representation of integrator in the utility model.
Fig. 8 is the second working state schematic representation of integrator in the utility model.
Fig. 9 is the circuit diagram of decimation filter of digital in the utility model.
Figure 10 is the circuit diagram of control sequential module in the utility model.
Figure 11 is transmission gate switch schematic diagram in the utility model.
Specific embodiment
With reference to the accompanying drawing and existing software, the technical solution of the utility model is specifically described.In the explanation
Existing software involved in the process is not the object that the utility model is protected, and the utility model only protects the knot of the device
Structure and connection relationship.
The utility model provides a kind of capacity sensor circuit based on Sigma-Delta modulation, comprising: inductance capacitance
CX, capacitor reading circuit CDC, control sequential module and decimation filter of digital.Wherein, capacitor reading circuit uses three ranks
Sigma-Delta modulator structure realizes the conversion of capacitor-number, inductance capacitance CXAs Sigma-Delta modulator first
Sampling capacitance in grade integrator, Sigma-Delta modulator are capacitor reading circuit.Decimation filter of digital is by real outside piece
It is existing.CDC is first by inductance capacitance CXVariable quantity be converted to charge signal, then to charge signal carry out Sigma-Delta tune
System, exports digital code stream, and decimation filter of digital carries out filtering and down-sampled processing to digital code stream.The present invention, which has, to be easy to
The advantages that CMOS is not integrated, high to the required precision of analog circuit.
Further, Fig. 1 is capacitive sensor system frame, CXIt is the inductance capacitance of sensor, CDC is surveyed using ratio
Amount method inputs inductance capacitance CXWith piece internal reference capacitor CrefRatio represent the density of sensor output code flow bs, then by counting
Word decimation filter is filtered CDC output code flow and fits a digital quantity Dout, which can be used to characterize
Input inductance capacitance CX.Capacitive digital converter (CDC) is similar with common Sigma-Delta modulator working principle, but not
Be the input signal of CDC be the capacitor of variation, rather than voltage.Sigma-Delta modulator in Fig. 1, as shown in Fig. 2,
By taking single order as an example, illustrate the charge balance equilibrium process of CDC.Within each change-over period, a positive voltage VDD is to (CX-
Coff) charge, while a voltage is to CrefCharging, and this polarity of voltage depends on the polarity of output bs.Integrator exists
In feedback loop, effect is to control the polarity of reference charge, makes the output average out to zero of integrator, i.e., average reference charge is big
It is small equal with input charge, that is, charge balance, finally make output code flow density μ ∝ (CX-Coff)/Cref, due to CrefIt is
Fixed capacity, so input inductance capacitance CXIt can be by code stream density μ Precise Representation.
Further, capacitance sensor is usually used in low-power consumption application, in order to obtain the CDC of optimised power consumption, sigma-delta modulation
The over-sampling rate of device and required change-over period should be as small as possible.Since single order sigma-delta modulator needs higher over-sampling rate ability
Its quantizing noise is reduced to peer-level, it is possible to which over-sampling rate is reduced using higher order modulator.However, it should sufficiently
Consider effective input range of higher order modulator.A usual nd order modulator is full scale input, and the maximum of higher order modulator is defeated
Enter, can be limited, to prevent integrator from overloading.In general, effective input range of second-order modulator is ± 0.75Cref, three
Effective input range of nd order modulator further reduces as ± 0.67Cref.Equally, under 13bit resolution ratio, second-order modulator is needed
Want 400-500 period that quantizing noise could be reduced to the level, and three nd order modulators need 100-200 period.Second order
Modulator requires higher change-over period, and the change-over period of fourth-order modulator of Figure is lower but to will increase circuit complexity.In this implementation
In example, three nd order modulator structures, sample frequency 250kHZ are selected.Fig. 3 is third order sigma-delta modulator structural block diagram, is illustrated as
CIFF (cascade integrators with feedforward) structure, this structure reduce integrator output output pendulum
Width improves modulator linearity degree.Integrator coefficients at different levels such as Fig. 3 shows, in effective input range, to reach 13bit precision,
Need 200 change-over periods.
Further, Fig. 4 is CDC circuit structure, and wherein the second level, third level structure and the first order use identical circuit
Structure.
First order integrator, second level integrator and third level integrator include a spaning waveguide operational amplifier and respectively with across
Lead the matched forward path of amplifier and negative sense access；Forward path and negative sense access are symmetrical arranged, and include: first switch,
Corresponding first delay switch of second switch, first switch, corresponding second delay switch of second switch, storage capacitor and product
Divide capacitor.
In the present embodiment, the both ends of the first delay switch in forward path respectively with the negative input of spaning waveguide operational amplifier
And positive output end is connected；One end of integrating capacitor in forward path is connected with the positive output end of spaning waveguide operational amplifier, another
End is connected with one end of second switch；One end of storage capacitor in the other end and forward path of second switch connects；It is positive
The other end of storage capacitor in access is connected with the negative input of spaning waveguide operational amplifier；In forward path one end of first switch with
One end of second switch is connected, another termination common-mode voltage；
The both ends of the first delay switch in negative sense access are exported with the positive input of spaning waveguide operational amplifier and negative sense respectively
End is connected；One end of integrating capacitor in negative sense access is connected with the negative sense output end of spaning waveguide operational amplifier, the other end and second switch
One end be connected；The other end of second switch is connect with one end of the storage capacitor in negative sense access；Energy storage in negative sense access
The other end of capacitor is connected with the positive input of spaning waveguide operational amplifier；The one of one end of first switch and second switch in negative sense access
End is connected, another termination common-mode voltage.
In the present embodiment, the input terminal of the forward path in first order integrator and negative sense access respectively with it is corresponding
Inductance capacitance one end and matched compensating electric capacity be connected.
Further, it is specifically described in conjunction with Fig. 4.Switch ψ1、ψ1d、ψ2、ψ2dWith spaning waveguide operational amplifier OTA and sampling electricity
Hold CX, integrating capacitor CintConstitute first order integrator.In Fig. 4 with the negative input end of OTA1 from the point of view of, switch ψ 1, ψ 1d be closed when
To sample phase, capacitor CXIt is charged to VDD；It is integral phase, capacitor C when switch ψ 2, ψ 2d are closedX1On electric charge transfer to integral
Device CintOn.Wherein, ψ1d、ψ2dRespectively ψ1、ψ2Delay, ψ1With ψ2Using non-overlapping clock control.
Further, switch ψ1、ψ1d、ψ2、ψ2dIt is switched using cmos transmission gate, NMOS tube and PMOS pipe connect into parallel connection
Structure, conducting resistance is equal to NMOS tube and PMOS tube conducting resistance is in parallel, and usual conducting resistance is smaller, and the linearity is preferable,
Transmission gate switch schematic diagram is as shown in figure 11.
Further, CDC uses fully differential structure, inductance capacitance CX1And CX2Directly as the input of first order integrator
Capacitor.Compensating electric capacity Coff1And Coff2Cross-coupling is in inductance capacitance, so that the effective input capacitance of the first order is (CX-Coff)。
Reference capacitance Cref1And Cref2Driving method and CXIt is the same, but its polarity connecting with integrator depends on output code
Stream, so that charge balance, it is 0 that integrator, which averagely exports,.Fig. 5 is inductance capacitance CXMatrix diagram, it is contemplated that circuit design stage system
It unites the test job after the correctness of work, flow, and the range of extension input capacitance, in the present embodiment, inductance capacitance CX
With compensating electric capacity CoffIt is made of the capacitance matrix of 7 binary scales, specific capacitance is respectively 64fF and 32fF, different electricity
The selection of appearance is then controlled by switching signal, and the switch as controlled capacitance selection in Fig. 5 is S000~S111, passes through low and high level reality
It is existing.Due to inductance capacitance CXMaximum can reach 8pF, that is, the load of first order integrator is larger, in order to guarantee first order product
Divide device precise and stable, to ensure that modulator works normally, so first order amplifier will have enough Slew Rates, thus, first order fortune
Putting branch current must be sufficiently large.
Further, using the capacitor reading circuit modulated based on Sigma-Delta, since capacitor does not consume static function
Consumption, the main power consumption of circuit are concentrated mainly on operational transconductance amplifier in integrator.Operational transconductance amplifier OTA conduct in Fig. 4
The nucleus module of integrator, performance largely affect the performance of Sigma-Delta modulator.Fig. 6 is based on reverse phase
The current-steering OTA of device structure, input to pipe include NMOS to and PMOS pairs, and be only distributed in two branch roads, every
Respectively there is 1/2 electric current in branch road, consumes electric current I in total.Its current utilization efficiency are as follows:
4 times are improved compared to traditional Foldable cascade OTA current utilization rate, improves 2 times than telescopic OTA,
Therefore this structure has the advantage of low-power consumption.I in Fig. 6biasIt is obtained by bias current mirror image, tail current is by common mode feedback circuit
It adjusts.In order to improve its DC current gain, PMOS and NMOS cascade structure increases OTA output impedance in Fig. 6, thus improves increasing
Benefit.OTA compared to conventional inverter structure is easy to be caused quiescent point to change by technique change, and DC current gain is lower
Characteristic, the structure effectively improve OTA performance.
Further, the switched-capacitor integrator in Fig. 4 is by the non-overlapping clock control of two-phase, and uses automatic zero set technology
Eliminate the input offset voltage of phase inverter OTA, wherein the input offset voltage of OTA is stored on capacitor CC, and offset voltage is not
Influence the output voltage of integrator.Integrator works in sampling and integral two states.ψ in Fig. 41And ψ1dXiang Shi, that is, working as ψ1
And ψ1dWhen closure, integrator works in sample states, and voltage VDD is to sampling capacitance CX1It charges；ψ2And ψ2dXiang Shi, integral
Device is in integrating state, sampling capacitance CX1On electric charge transfer to integrating capacitor CintOn.
By taking single-ended structure as an example, the two states of integrator work are described shown in Fig. 7 and Fig. 8.
When work is in ψ1When, as shown in fig. 7, spaning waveguide operational amplifier is switched to unit gain mode, the input offset voltage of amplifier
For VXTo capacitor CCCharging, and it is stored in capacitor CCOn.Wherein, the input offset voltage of amplifier is remembered it is assumed that for VX, as ψ 1
When closing the switch with ψ 1d, voltage VDD charges to capacitor CX；Offset voltage charges to capacitor CC.It inputs at the same time
Capacitor CXIt is charged to voltage VDD.
When working in ψ2When, as shown in figure 8, capacitor CCIt connects with the input of phase inverter holding, integrating capacitor CintIt is switched to
On negative feedback paths.Due to negative-feedback, VXIt is generally kept at input offset voltage level, so node VGIt is maintained at signal ground.Institute
With capacitor C at this timeXOn charge will be transferred completely into integrating capacitor CintOn, amplifier input offset voltage exports electricity to integrator
Press VoutIt has substantially no effect on.In order to ensure integrator is precise and stable, ψ2Duration must be big compared to the time constant of electric charge transfer
It is more.
Further, as shown in figure 9, decimation filter of digital uses sinc4 filter, the filtering is built using Matlab
Device model carries out filtering and down-sampled processing to digital code stream.
Further, as shown in Figure 10, the control signal of switch is non-overlapping clock, and is generated by clock generation circuit,
Delay is time delay module.
Further, the present invention uses 0.18 μm of technique of SMIC, is emulated and has been tested using Spectre emulation tool
Card.In the conversion time of 0.8ms (200 periods), relative to compensating electric capacity Coff, under ± 260fF equivalent input capacitance, three
Nd order modulator realizes 13bit precision.By the way that C is arrangedoffThe range of surveying of capacitance matrix, input capacitance can reach 0-8pF.
The present invention is based on the capacitance sensors of Sigma-Delta modulation, using three rank Sigma-Delta modulation technologies
Direct conversion of the capacitor to digital signal, and capacitance range can be surveyed by compensating electric capacity matrix-expand, utilize current-steering
OTA improves amplifier current utilization rate, reduces overall power.Using 0.18 μm of CMOS technology of SMIC, Cadence tool pair is utilized
Circuit carries out simulating, verifying, and under the supply voltage of 2V, in 0.8ms conversion time, modulator realizes 3 rank noise shaping functions,
It is 0-8pF that input capacitance range, which can be surveyed, and realizes the good linearity.
It is the preferred embodiment of the utility model above, it is all to change according to made by technical solutions of the utility model, it is produced
Function without departing from technical solutions of the utility model range when, belong to the protection scope of the utility model.
Claims (9)
1. a kind of capacity sensor circuit based on Sigma-Delta modulation characterized by comprising inductance capacitance, one use
In by the variable quantity of the inductance capacitance be converted to charge signal and to charge signal carry out Sigma-Delta modulation capacitor
Digital quantizer, one handle and mention with down-sampled for being filtered to the digital code stream that the capacitive digital converter exports
For the decimation filter of digital and sequential control circuit of the digital quantity for characterizing the inductance capacitance；The inductance capacitance with
The capacitive digital converter is connected, and the decimation filter of digital is connected with the capacitive digital converter, the timing control
Circuit processed is connected with the capacitive digital converter and the decimation filter of digital respectively；The capacitive digital converter is adopted
With Sigma-Delta modulator.
2. a kind of capacity sensor circuit based on Sigma-Delta modulation according to claim 1, which is characterized in that
The Sigma-Delta modulator is three rank Sigma-Delta modulators.
3. a kind of capacity sensor circuit based on Sigma-Delta modulation according to claim 2, which is characterized in that
The three ranks Sigma-Delta modulator includes first order integrator, second level integrator and third level integrator.
4. a kind of capacity sensor circuit based on Sigma-Delta modulation according to claim 3, which is characterized in that
The first order integrator, the second level integrator and the third level integrator include a spaning waveguide operational amplifier and difference
With the matched forward path of the spaning waveguide operational amplifier and negative sense access；The forward path and the negative sense access are symmetrical arranged, and
It include: that first switch, second switch, corresponding second delay of corresponding first delay switch of first switch, second switch are opened
Pass, storage capacitor and integrating capacitor.
5. a kind of capacity sensor circuit based on Sigma-Delta modulation according to claim 4, which is characterized in that
The both ends of the first delay switch in the forward path are exported with the negative input of the spaning waveguide operational amplifier and forward direction respectively
End is connected；One end of integrating capacitor in the forward path is connected with the positive output end of the spaning waveguide operational amplifier, the other end with
One end of the second switch is connected；One end of storage capacitor in the other end of the second switch and the forward path connects
It connects；The other end of storage capacitor in the forward path is connected with the negative input of the spaning waveguide operational amplifier；It is described positive logical
One end of first switch is connected with one end of the second switch in road, another termination common-mode voltage.
6. a kind of capacity sensor circuit based on Sigma-Delta modulation according to claim 4, which is characterized in that
The both ends of the first delay switch in the negative sense access are exported with the positive input of the spaning waveguide operational amplifier and negative sense respectively
End is connected；One end of integrating capacitor in the negative sense access is connected with the negative sense output end of the spaning waveguide operational amplifier, the other end with
One end of the second switch is connected；One end of storage capacitor in the other end of the second switch and the negative sense access connects
It connects；The other end of storage capacitor in the negative sense access is connected with the positive input of the spaning waveguide operational amplifier；The negative sense is logical
One end of first switch is connected with one end of the second switch in road, another termination common-mode voltage.
7. a kind of capacity sensor circuit based on Sigma-Delta modulation according to claim 4, which is characterized in that
The input terminal of forward path and negative sense access in the first order integrator respectively with corresponding inductance capacitance and
The compensating electric capacity matched is connected.
8. a kind of capacity sensor circuit based on Sigma-Delta modulation according to claim 4, which is characterized in that
The spaning waveguide operational amplifier uses the current-steering OTA based on inverter structure.
9. a kind of capacity sensor circuit based on Sigma-Delta modulation according to claim 4, which is characterized in that
The decimation filter of digital uses sinc4Filter.
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| CN201820442933.XU CN208589978U (en) | 2018-03-30 | 2018-03-30 | Capacity sensor circuit based on Sigma-Delta modulation |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110146558A (en) * | 2019-06-18 | 2019-08-20 | 福州大学 | Reading circuit and its control method applied to capacitance type humidity sensor |
| CN110243883A (en) * | 2019-06-18 | 2019-09-17 | 福州大学 | A kind of relative humidity approximating method suitable for the intelligent humidity sensor-based system based on HS1101 |
-
2018
- 2018-03-30 CN CN201820442933.XU patent/CN208589978U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110146558A (en) * | 2019-06-18 | 2019-08-20 | 福州大学 | Reading circuit and its control method applied to capacitance type humidity sensor |
| CN110243883A (en) * | 2019-06-18 | 2019-09-17 | 福州大学 | A kind of relative humidity approximating method suitable for the intelligent humidity sensor-based system based on HS1101 |
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