CN210136195U - Reading circuit applied to capacitive humidity sensor - Google Patents
Reading circuit applied to capacitive humidity sensor Download PDFInfo
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- CN210136195U CN210136195U CN201920913323.8U CN201920913323U CN210136195U CN 210136195 U CN210136195 U CN 210136195U CN 201920913323 U CN201920913323 U CN 201920913323U CN 210136195 U CN210136195 U CN 210136195U
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Abstract
The utility model relates to a be applied to capacitanc humidity transducer's readout circuit. The system comprises a multiplexer and a capacitance digital converter, wherein the capacitance digital converter comprises a Sigma-Delta modulator and a digital decimation filter; the input end of the multi-path selector is connected with the output end of the capacitance type humidity sensor, the output end of the multi-path selector is connected with the input end of the digital extraction filter through the Sigma-Delta modulator, and the output end of the digital extraction filter is used as the digital signal output end of the whole reading circuit. The utility model discloses can use in multiple capacitanc humidity transducer's measurement, directly convert capacitanc humidity transducer's response electric capacity signal into digital signal output to in with modern digital signal processor lug connection.
Description
Technical Field
The utility model relates to a be applied to capacitanc humidity transducer's readout circuit.
Background
In recent years, people have more and more demands on monitoring the environmental humidity, and the environmental humidity and the temperature have the same important significance on life and manufacture of people. The humidity detection and control can not be separated in the aspects of meteorological monitoring, medical safety, logistics monitoring, food protection, aerospace, automobile electronics and the like. With the continuous development of science, various types of humidity sensors, such as a resistance-type humidity sensor, a capacitance-type humidity sensor, a piezoresistive-type humidity sensor, a cantilever-beam-type humidity sensor, and the like, appear in the market. Among them, the capacitive humidity sensor has the advantages of simple structure, high sensitivity, low power consumption, good temperature characteristics, and the like, and is widely used.
The capacitive humidity sensor mainly works on the principle that humidity to be measured in the environment is converted into capacitance change. The sensing capacitance of a capacitive moisture sensor is very small, typically in the order of pF. Capacitive humidity sensors therefore require a sensing circuit to read the minute signal. Capacitive humidity sensors are typically read by oscillator, ac bridge or switched capacitor circuits, which convert the humidity sensitive capacitance of the sensor into a frequency or voltage output. The output signal of this kind of readout circuit has only one measurement mode, can only carry out differential capacitance or single capacitance measurement, and can not be directly connected with the port of modern digital signal processor, and still need to be undergone the further conversion processing.
Disclosure of Invention
An object of the utility model is to provide a be applied to capacitanc humidity transducer's reading circuit can use in multiple capacitanc humidity transducer's measurement, directly converts capacitanc humidity transducer's response electric capacity signal into digital signal output to in with modern digital signal processor lug connection.
In order to achieve the above purpose, the technical scheme of the utility model is that: a readout circuit applied to a capacitive humidity sensor comprises a multiplexer, a capacitance-to-digital converter, a digital-to-analog converter and a digital decimation filter, wherein the capacitance-to-digital converter comprises a Sigma-Delta modulator and a digital decimation filter; the input end of the multi-path selector is connected with the output end of the capacitance type humidity sensor, the output end of the multi-path selector is connected with the input end of the digital extraction filter through the Sigma-Delta modulator, and the output end of the digital extraction filter is used as the digital signal output end of the whole reading circuit.
In an embodiment of the present invention, the multiplexer includes first to tenth and gates and first to fifth or gates, the first input end of the first to fifth and gates is connected to the first clock output end of the clock generator as the first input end of the whole multiplexer, the first input end of the sixth to tenth and gates is connected to the second input end of the whole multiplexer as the second input end of the whole multiplexer, the second input end of the first and gate is connected to the first clock output end of the clock generator as the clock signal input end, the second input end of the second and gate, the second input end of the third and gate, the second input end of the sixth and gate, the second input end of the eighth and gate, the second input end of the ninth and gate is connected to the digital power input end, the second input end of the fourth and gate, the second input end of the fifth and gate, the second input end of the seventh and gate, the second input end of the tenth and gate is connected to the digital ground end, the output end of the first and gate, The output ends of the sixth AND gate and the seventh AND gate are respectively connected with two input ends of the first OR gate, the output ends of the second AND gate and the seventh AND gate are respectively connected with two input ends of the second OR gate, the output ends of the third AND gate and the eighth AND gate are respectively connected with two input ends of the third OR gate, the output ends of the fourth AND gate and the ninth AND gate are respectively connected with two input ends of the fourth OR gate, the output end of the fifth AND gate and the output end of the tenth AND gate are respectively connected with two input ends of the fifth OR gate, and the output ends of the first to the fifth OR gates are respectively used as the first to the fifth output ends of the whole multi-way selector.
In an embodiment of the present invention, the Sigma-Delta modulator includes a feedback path, a switch circuit controlled by a multiplexer, a first-stage integrator, a second-stage integrator, a third-stage integrator, a feedforward path, and a quantizer; the Sigma-Delta modulator also comprises a first compensation capacitor and a second compensation capacitor which are connected with the first-stage integrator; the switch circuit comprises first to fifth multi-path selection switches, and control ends of the first to fifth multi-path selection switches are respectively connected with first to fifth output ends of the multi-path selector.
In an embodiment of the present invention, the first stage integrator includes first to ninth switches, a first reset switch, a second reset switch, a first capacitor, a second capacitor, a first sampling capacitor, a second sampling capacitor, a first integrating capacitor, a second integrating capacitor, and a first operational amplifier; one end of a first switch is connected to VDD, the other end of the first switch is connected with one end of a first sampling capacitor, one end of a second switch and one end of a second compensation capacitor, the other end of the second switch is connected to GND, the other end of the first sampling capacitor is connected with one end of the first compensation capacitor, one end of a fifth multi-way selection switch and one end of a third multi-way selection switch, the other end of the fifth multi-way selection switch and one end of a fourth multi-way selection switch are connected to GND, the other end of the third multi-way selection switch is connected with one end of a first capacitor, one end of a third switch and one end of a fourth switch, the other end of the third switch is connected with one end of the first multi-way selection switch to a common mode level, the other end of the fourth switch is connected with one end of a first reset switch and one end of a first integrating capacitor, the other end of the first capacitor is connected with, One end of a fifth switch is connected, the other end of the first reset switch is connected with the other end of the first integrating capacitor, the other end of the fifth switch and the first output end of the first operational amplifier and is used as the first output end of the first-stage integrator, one end of a sixth switch is connected to GND, the other end of the sixth switch is connected with one end of the second sampling capacitor, one end of a seventh switch and the other end of the first compensation capacitor, the other end of the seventh switch is connected to VDD, the other end of the second sampling capacitor is connected with the other end of the second compensation capacitor, the other end of a fourth multi-way selection switch and one end of a second multi-way selection switch, the other end of the second multi-way selection switch is connected with the other end of the first multi-way selection switch circuit, one end of the second capacitor and one end of an eighth switch, the other end of the eighth switch is connected with one end of the second reset switch and one end of the second integrating, the other end of the second capacitor is connected with one end of a ninth switch and the non-inverting input end of the first operational amplifier, and the other end of the ninth switch is connected with the other end of the second reset switch, the other end of the second integrating capacitor and the second output end of the first operational amplifier and serves as the second output end of the first-stage integrator.
In an embodiment of the present invention, the feedback path includes a first reference capacitor, a second reference capacitor, an eleventh to a twentieth switch, one end of the eleventh switch is connected to VDD, the other end of the eleventh switch is connected to one end of the twelfth switch and one end of the first reference capacitor, the other end of the twelfth switch is connected to GND, the other end of the first reference capacitor is connected to the common mode level via a thirteenth switch, the other end of the first reference capacitor is further connected to one end of the fourteenth switch and one end of the fifteenth switch, the other end of the fourteenth switch is connected to one end of the nineteenth switch and the other end of the second sampling capacitor, the other end of the fifteenth switch is connected to one end of the third multi-way selector switch and one end of the twentieth switch, one end of the sixteenth switch is connected to GND, the other end of the sixteenth switch is connected to one end of the seventeenth switch and one end of the second reference capacitor, the other end of the seventeenth switch is connected to VDD, the other end of the second reference capacitor is connected to the common mode level through the eighteenth switch, and the other end of the second reference capacitor is further connected to the other end of the nineteenth switch and the other end of the twentieth switch.
In an embodiment of the present invention, the second stage integrator includes twenty-first to thirty-third switches, a third reset switch, a fourth reset switch, a third capacitor, a fourth capacitor, a third sampling capacitor, a fourth sampling capacitor, a third integrating capacitor, a fourth integrating capacitor, and a second operational amplifier; one end of a twenty-first switch is connected to the first output end of the first integrator, the other end of the twenty-first switch is connected with one end of a third sampling capacitor and one end of a twenty-second switch, the other end of the twenty-second switch is connected with one end of a twenty-seventh switch to a common mode level, the other end of the third sampling capacitor is connected with one end of a twenty-third switch, one end of a twenty-fourteenth switch and one end of a third capacitor, the other end of the twenty-third switch is connected with one end of a twenty-eighteen switch to the common mode level, the other end of the twenty-fourteenth switch is connected with one end of a third reset switch and one end of a third integrating capacitor, the other end of the third capacitor is connected with an inverting input end of the second operational amplifier and one end of a twenty-fifth switch, the other end of the third reset switch, the other end of the third integrating capacitor, the other end of the twenty-fifth switch and the first, and the other end of the twenty-ninth switch is connected with one end of a fourth reset switch and one end of a fourth integrating capacitor, the other end of the fourth capacitor is connected with the non-inverting input end of a second operational amplifier and one end of a thirty-third switch, and the other end of the fourth reset switch is connected with the other end of the fourth integrating capacitor, the other end of the thirty-third switch and the second output end of the second operational amplifier and is used as the second output end of the second-stage integrator.
In an embodiment of the present invention, the third stage integrator includes thirty-first to forty-th switches, a fifth reset switch, a sixth reset switch, a fifth capacitor, a sixth capacitor, a fifth sampling capacitor, a sixth sampling capacitor, a fifth integrating capacitor, a sixth integrating capacitor, and a third operational amplifier; one end of a thirty-first switch is connected to the first output end of the second integrator, the other end of the thirty-first switch is connected to one end of a fifth sampling capacitor and one end of a thirty-second switch, the other end of the thirty-second switch is connected to one end of a seventeenth switch to a common mode level, the other end of the fifth sampling capacitor is connected to one end of a thirty-third switch, one end of a thirty-fourth switch and one end of a fifth capacitor, the other end of the thirty-third switch and one end of a thirty-eighth switch are connected to the common mode level, the other end of the thirty-fourth switch is connected to one end of a fifth reset switch and one end of a fifth integrating capacitor, the other end of the fifth reset switch, the other end of the fifth integrating capacitor, the other end of the thirty-fifth switch and the first output end of the third operational amplifier, and the other end of the thirty-ninth switch is connected with one end of a sixth reset switch and one end of a sixth integrating capacitor, the other end of the sixth capacitor is connected with a non-inverting input end of a third operational amplifier and one end of a forty-th switch, and the other end of the sixth reset switch is connected with the other end of the sixth integrating capacitor, the other end of the forty-th switch and a second output end of the third operational amplifier and is used as a second output end of the third-stage integrator.
In an embodiment of the present invention, the feed-forward path includes seventh to twelfth capacitors, forty-first to forty-sixth switches, one end of the seventh capacitor is connected to the other end of the twenty-first switch, the other end of the seventh capacitor is connected to one end of the ninth capacitor, one end of the twelfth capacitor, and one end of the forty-first switch, one end of the eighth capacitor is connected to the other end of the thirty-first switch, the other end of the eighth capacitor is connected to one end of the tenth capacitor, one end of the eleventh capacitor, and one end of the forty-second switch, the other end of the ninth capacitor is connected to one end of the forty-third switch and one end of the forty-fourteenth switch, the other end of the tenth capacitor is connected to one end of the forty-fifth switch and one end of the forty-fourth-sixth switch, the other end of the eleventh capacitor is connected to the other end of the thirty-sixth switch, and the other end of the twelfth capacitor is connected to the other end of, the other end of the forty-first switch and the other end of the forty-second switch are connected to a common mode level, the other end of the forty-third switch is connected with the first output end of the third-stage integrator, the other end of the forty-fourth switch and the other end of the forty-sixth switch are connected to the common mode level, the other end of the forty-fifth switch is connected with the second output end of the third-stage integrator, and one end of the forty-first switch and one end of the forty-second switch are respectively used as a first output end and a second output end of the feedforward path.
In an embodiment of the present invention, the control end of the third switch, the thirteenth switch, the eighteenth switch, the twenty-fourth switch, the twenty-ninth switch, the thirty-third switch and the thirty-eighth switch is connected to the first clock signal output end of the clock signal generator, the control end of the fourth switch, the eighth switch, the twenty-third switch, the twenty-eighth switch, the thirty-fourth switch and the thirty-ninth switch is connected to the second clock signal output end of the clock signal generator, the control end of the first switch, the fifth switch, the sixth switch, the ninth switch, the eleventh switch, the sixteenth switch, the twenty-second switch, the twenty-seventh switch, the thirty-fifth switch, the thirty-sixth switch and the forty switch is connected to the third clock signal output end of the clock signal generator, and the control end of the second switch, the seventh switch, the twelfth switch, the thirty-fourth switch, the twenty-ninth switch and the thirty-fifth switches are connected to the second, The control ends of the seventeenth switch, the twenty-first switch, the twenty-fifth switch, the twenty-sixth switch, the thirty-third switch, the thirty-second switch and the thirty-seventh switch are connected with the fourth clock signal output end of the clock signal generator, the control ends of the fourteenth switch and the twentieth switch are connected with the fifth clock signal output end of the clock signal generator, and the control end of the fifteenth switch and the control end of the nineteenth switch are connected with the sixth clock signal output end of the clock signal generator.
In an embodiment of the present invention, the relationship between the clock signals generated by the clock signal generator is: the first clock signal and the second clock signal are mutually reverse non-overlapped clocks; the third clock signal is a clock with synchronous rising edge and delayed falling edge of the first clock signal; the fourth clock signal is a clock delayed by the rising edge of the second clock signal; the fifth clock signal is the AND operation result of the fourth clock signal and the output signal of the Sigma-Delta modulator, and the sixth clock signal is the AND operation result of the fourth clock signal and the inverted signal of the output signal of the Sigma-Delta modulator.
Compared with the prior art, the utility model discloses following beneficial effect has: the utility model realizes two measuring modes by a multi-way selector, and obtains digital output by adopting Sigma-Delta modulation technology; the whole circuit has high precision and wide input range; the utility model discloses can use in multiple capacitanc humidity transducer's measurement to can directly be connected with modern digital processing system.
Drawings
Fig. 1 is a block diagram of an overall system of a capacitive humidity sensor.
FIG. 2 is a CDC system model.
FIG. 3 is a diagram of a specific circuit structure of a Sigma-Delta modulator.
FIG. 4 is a timing diagram of a Sigma-Delta modulator circuit.
Fig. 5 is a schematic diagram of a multiplexer.
Fig. 6 is a specific circuit configuration diagram of the multiplexer.
Fig. 7 illustrates the principle of operation of a switched capacitor integrator.
Fig. 8 is a circuit block diagram of the op-amp OTA 1.
Detailed Description
The technical solution of the present invention will be specifically described below with reference to the accompanying drawings.
The utility model provides a be applied to capacitanc humidity transducer's reading circuit, including multiplexer, electric capacity digital converter includes Sigma-Delta modulator and digital decimation wave filter; the input end of the multi-path selector is connected with the output end of the capacitance type humidity sensor, the output end of the multi-path selector is connected with the input end of the digital extraction filter through the Sigma-Delta modulator, and the output end of the digital extraction filter is used as the digital signal output end of the whole reading circuit.
The following is the specific implementation process of the present invention.
The utility model provides a capacitanc humidity transducer read-out circuit with multiple measurement mode and digital output can carry out the measurement of differential capacitance or single electric capacity, adopts Sigma-Delta modulation technique, directly converts capacitanc humidity transducer's response electric capacity signal into digital signal output, can directly be connected with present digital processor. The utility model relates to an adopt SMIC 0.18 mu m CMOS technology to realize, supply voltage is 1.8V, and sampling clock frequency is 250kHz, through the spectra emulation, under two kinds of measurement modes, the input capacitance common mode range of whole circuit is 0pF ~8pF, and dynamic range is-0.26 pF- +0.26pF, and the modulator precision reaches 13 bit.
The overall system structure is shown in fig. 1, and the readout circuit mainly comprises a multiplexer, a Sigma-Delta modulator and a digital decimation filter, wherein the modulator and the filter form a capacitance-to-digital converter CDC. Firstly, selecting a measurement mode by using a multi-path selector according to measurement requirements, then converting an induction capacitor of a capacitance type humidity sensor into a charge signal by using a Sigma-Delta modulator, modulating the charge signal to obtain a digital code stream, and finally processing the digital code stream by using a digital extraction filter to obtain a digital quantity corresponding to the induction capacitor.
The CDC system model is shown in FIG. 2, the Sigma-Delta modulator adopts a third-order CIFF (Cascade integrators with feed forward) structure, and the digital extraction filter is sincKFilter, where K = 4. In the figure, CXFor the input capacitance, is the inductive capacitance of the sensor, CoffTo compensate for capacitance, CrefFor reference capacitance, RESET is RESET signal, bs is output code stream of modulator, DoutIs the actual output digital quantity. The utility model discloses a CDC utilizes equivalent input capacitance (C)X-Coff) And a reference capacitance CrefThe charge balance between the two circuits is used for detecting the change of an unknown input capacitor, the working mode of the circuit is a discrete mode, namely the circuit is powered on, the integrator is reset before each conversion, a digital code is generated after one conversion is completed, a plurality of cycles are continuously converted, and finally, the digital code stream is filtered and down-sampled by a digital decimation filter to obtain digital output.
The specific circuit structure of the Sigma-Delta modulator is shown in fig. 3, for convenience of representation, components with the same characters in the figure represent that the parameters of the components are the sameWherein OTA1, OTA2 and OTA3 are operational amplifiers, 2ndInt, second stage integrator, 3rdInt is the third stage integrator. The integrator takes the form of a switched capacitor, which is composed of switches S1, S1d, S2, S2d, transconductance operational amplifier OTA and sampling capacitor C, as shown in fig. 3sIntegrating capacitor CintAnd (4) forming. When the circuit is in a double-end input mode, the SW1 and the S1 are connected with the same time sequence, the SW2 and the SW3 are connected, the SW4 and the SW5 are disconnected, the CDC adopts a fully differential structure, the structure can reduce the sensitivity to noise coupling, and the sensing capacitor C can reduce the noise couplingX1And CX2A sampling capacitor directly coupled to the first stage integrator as the first stage integrator, and a compensation capacitor Coff1And Coff2Cross-coupled to the sensing capacitor such that the effective input capacitance of the first stage is (C)X- Coff). When the circuit is in a single-ended input mode, the SW1, the SW3, the SW4 and the SW5 are conducted, the SW2 is disconnected, and the sensing capacitor CX1The positive input end of the first-stage integrator is fixedly connected to a common-mode level, and a compensation capacitor Coff1Excitation and C ofX1The excitation of (2) is reversed.
The circuit timing is shown in fig. 4, S1 and S2 are two mutually opposite non-overlapping clocks, S1d is a clock delayed by the rising edge and the falling edge of S1; s2d is the clock delayed by the rising edge of S2. The first stage integrator samples at phase S1 and integrates at phase S2. The second stage integrator samples at phase S2 and integrates at phase S1. The third stage integrator samples at phase S1 and integrates at phase S2. EVAL is the comparator clock and the falling edge is active. RESET is a RESET signal that RESETs the system after each transition is completed.
Multiplexer principle as shown in fig. 5, mode 1 and mode 2 are input terminals of the multiplexer, high level is active, and SW1-SW5 are output signals of the multiplexer. The input mode of the circuit is selected by controlling the levels of MODEL1 and MODEL 2. The specific circuit is shown in fig. 6, and is composed of a digital and gate and an or gate. When the MODEL1 is at high level and the MODEL2 is at low level, the circuit is in a two-terminal input mode, the SW1 and the S1 are connected with the same time sequence, the SW2 and the SW3 are connected, and the SW4 and the SW5 are disconnected; when the mode 1 is low and the mode 2 is high, the circuit is in single-ended input mode, SW1, SW3, SW4 and SW5 are on, and SW2 is off.
The switched capacitor integrator adopts an auto-zero technique to eliminate the input offset voltage of the operational amplifier, and when viewed from the negative input end of the OTA1 in fig. 3, the switches S1 and S1d are closed, which are sampling phases, and the capacitor CX1Is charged to VDD; when the switches S2 and S2d are closed, the switch is integrated phase, and the capacitor CX1The charge on is transferred to an integrator CintThe above. Taking the single-ended configuration as an example, fig. 7 (a) and (b) illustrate two states of operation of the switched capacitor integrator. In phase S1, the operational amplifier switches to unity gain mode, as shown in fig. 7 (a), and the input offset voltage (i.e., V) of the operational amplifierX) Is stored to a capacitor CCUp, the input capacitance Cs is charged to VDD; at the S2 phase, as shown in FIG. 7 (b), the capacitor CCAn integrating capacitor C connected in series with the operational amplifierintConnected to a feedback loop. Due to negative feedback, VXRemains approximately at the input offset voltage, so node VGHeld at virtual ground potential. Thus, the charge on the capacitor Cs will be transferred to C in its entiretyintInput offset voltage of operational amplifier to output voltage V of integratoroutSubstantially without effect. In order to meet the requirement that the circuit can normally work under two input modes and simultaneously meet the required precision requirement, the first-stage operational amplifier at least needs to reach 72 dB. Therefore, the first-stage operational amplifier OTA1 adopts a two-stage operational amplifier in a miller compensation mode, the gain reaches 120dB, the circuit structure is shown in fig. 8, the input stage adopts a folding cascade operational amplifier, PM2, PM3, NM4 and NM5 are input geminate transistors, an NMOS and PMOS parallel structure is adopted, a large input swing can be obtained, PM25, NM26, PM27 and NM28 are output stages, a Class-AB push-pull structure is adopted, a small direct current can be realized at an output tube in a static state, a large current is provided in a dynamic state, and the utilization rate of power consumption is improved. The average voltage of the two output ends is detected by using resistance voltage division and then is compared with an externally set common mode level VCMComparing, a feedback current is generated, which is injected into NM17 and NM18 through nodes a1 and a2, completing the feedback of the common mode signal.
Above is the utility model discloses a preferred embodiment, all rely on the utility model discloses the change that technical scheme made, produced functional action does not surpass the utility model discloses during technical scheme's scope, all belong to the utility model discloses a protection scope.
Claims (10)
1. A readout circuit for a capacitive humidity sensor, comprising a multiplexer, a capacitive digitizer, said capacitive digitizer comprising a Sigma-Delta modulator and a digital decimation filter; the input end of the multi-path selector is connected with the output end of the capacitance type humidity sensor, the output end of the multi-path selector is connected with the input end of the digital extraction filter through the Sigma-Delta modulator, and the output end of the digital extraction filter is used as the digital signal output end of the whole reading circuit.
2. The sensing circuit applied to the capacitive humidity sensor according to claim 1, wherein the multiplexer comprises first to tenth AND gates, first to fifth OR gates, first input terminals of the first to fifth AND gates serving as first input terminals of the entire multiplexer, first input terminals of the sixth to tenth AND gates serving as second input terminals of the entire multiplexer, a second input terminal of the first AND gate serving as a clock signal input terminal connected to the first clock signal output terminal of the clock signal generator, a second input terminal of the second AND gate, a second input terminal of the third AND gate, a second input terminal of the sixth AND gate, a second input terminal of the eighth AND gate, a second input terminal of the ninth AND gate serving as a digital power supply input terminal, a second input terminal of the fourth AND gate, a second input terminal of the fifth AND gate, a second input terminal of the seventh AND gate, and a second input terminal of the tenth AND gate serving as digital ground terminals, the output ends of the first and the sixth and the eighth and the fourth and the tenth are respectively connected with the two input ends of the fifth or gate, and the output ends of the first to the fifth or gates are respectively used as the first to the fifth output ends of the whole multi-way selector.
3. The readout circuit for use in a capacitive humidity sensor according to claim 2 wherein the Sigma Delta modulator comprises a feedback path, a switching circuit controlled by a multiplexer, a first stage integrator, a second stage integrator, a third stage integrator, a feed forward path, a quantizer; the Sigma-Delta modulator also comprises a first compensation capacitor and a second compensation capacitor which are connected with the first-stage integrator; the switch circuit comprises first to fifth multi-path selection switches, and control ends of the first to fifth multi-path selection switches are respectively connected with first to fifth output ends of the multi-path selector.
4. The readout circuit applied to the capacitive humidity sensor according to claim 3, wherein the first stage integrator comprises first to ninth switches, a first reset switch, a second reset switch, a first capacitor, a second capacitor, a first sampling capacitor, a second sampling capacitor, a first integration capacitor, a second integration capacitor, a first operational amplifier; one end of a first switch is connected to VDD, the other end of the first switch is connected with one end of a first sampling capacitor, one end of a second switch and one end of a second compensation capacitor, the other end of the second switch is connected to GND, the other end of the first sampling capacitor is connected with one end of the first compensation capacitor, one end of a fifth multi-way selection switch and one end of a third multi-way selection switch, the other end of the fifth multi-way selection switch and one end of a fourth multi-way selection switch are connected to GND, the other end of the third multi-way selection switch is connected with one end of a first capacitor, one end of a third switch and one end of a fourth switch, the other end of the third switch is connected with one end of the first multi-way selection switch to a common mode level, the other end of the fourth switch is connected with one end of a first reset switch and one end of a first integrating capacitor, the other end of the first capacitor is connected with, One end of a fifth switch is connected, the other end of the first reset switch is connected with the other end of the first integrating capacitor, the other end of the fifth switch and the first output end of the first operational amplifier and is used as the first output end of the first-stage integrator, one end of a sixth switch is connected to GND, the other end of the sixth switch is connected with one end of the second sampling capacitor, one end of a seventh switch and the other end of the first compensation capacitor, the other end of the seventh switch is connected to VDD, the other end of the second sampling capacitor is connected with the other end of the second compensation capacitor, the other end of a fourth multi-way selection switch and one end of a second multi-way selection switch, the other end of the second multi-way selection switch is connected with the other end of the first multi-way selection switch circuit, one end of the second capacitor and one end of an eighth switch, the other end of the eighth switch is connected with one end of the second reset switch and one end of the second integrating, the other end of the second capacitor is connected with one end of a ninth switch and the non-inverting input end of the first operational amplifier, and the other end of the ninth switch is connected with the other end of the second reset switch, the other end of the second integrating capacitor and the second output end of the first operational amplifier and serves as the second output end of the first-stage integrator.
5. The readout circuit applied to the capacitive humidity sensor according to claim 4, wherein the feedback path includes a first reference capacitor, a second reference capacitor, and eleventh to twentieth switches, one end of the eleventh switch is connected to VDD, the other end of the eleventh switch is connected to one end of a twelfth switch and one end of the first reference capacitor, the other end of the twelfth switch is connected to GND, the other end of the first reference capacitor is connected to the common mode level via a thirteenth switch, the other end of the first reference capacitor is further connected to one end of a fourteenth switch and one end of a fifteenth switch, the other end of the fourteenth switch is connected to one end of a nineteenth switch and the other end of the second sampling capacitor, the other end of the fifteenth switch is connected to one end of a third multiplexer switch and one end of a twentieth switch, one end of the sixteenth switch is connected to GND, the other end of the sixteenth switch is connected with one end of the seventeenth switch and one end of the second reference capacitor, the other end of the seventeenth switch is connected to the VDD, the other end of the second reference capacitor is connected to the common mode level through the eighteenth switch, and the other end of the second reference capacitor is further connected with the other end of the nineteenth switch and the other end of the twentieth switch.
6. The readout circuit applied to the capacitive humidity sensor according to claim 5, wherein the second stage integrator comprises twenty-first to thirty-third switches, a third reset switch, a fourth reset switch, a third capacitor, a fourth capacitor, a third sampling capacitor, a fourth sampling capacitor, a third integrating capacitor, a fourth integrating capacitor, and a second operational amplifier; one end of a twenty-first switch is connected to the first output end of the first integrator, the other end of the twenty-first switch is connected with one end of a third sampling capacitor and one end of a twenty-second switch, the other end of the twenty-second switch is connected with one end of a twenty-seventh switch to a common mode level, the other end of the third sampling capacitor is connected with one end of a twenty-third switch, one end of a twenty-fourteenth switch and one end of a third capacitor, the other end of the twenty-third switch is connected with one end of a twenty-eighteen switch to the common mode level, the other end of the twenty-fourteenth switch is connected with one end of a third reset switch and one end of a third integrating capacitor, the other end of the third capacitor is connected with an inverting input end of the second operational amplifier and one end of a twenty-fifth switch, the other end of the third reset switch, the other end of the third integrating capacitor, the other end of the twenty-fifth switch and the first, and the other end of the twenty-ninth switch is connected with one end of a fourth reset switch and one end of a fourth integrating capacitor, the other end of the fourth capacitor is connected with the non-inverting input end of a second operational amplifier and one end of a thirty-third switch, and the other end of the fourth reset switch is connected with the other end of the fourth integrating capacitor, the other end of the thirty-third switch and the second output end of the second operational amplifier and is used as the second output end of the second-stage integrator.
7. The readout circuit applied to the capacitive humidity sensor according to claim 6, wherein the third stage integrator comprises thirty-first to forty-fourth switches, a fifth reset switch, a sixth reset switch, a fifth capacitor, a sixth capacitor, a fifth sampling capacitor, a sixth sampling capacitor, a fifth integrating capacitor, a sixth integrating capacitor, and a third operational amplifier; one end of a thirty-first switch is connected to the first output end of the second integrator, the other end of the thirty-first switch is connected to one end of a fifth sampling capacitor and one end of a thirty-second switch, the other end of the thirty-second switch is connected to one end of a seventeenth switch to a common mode level, the other end of the fifth sampling capacitor is connected to one end of a thirty-third switch, one end of a thirty-fourth switch and one end of a fifth capacitor, the other end of the thirty-third switch and one end of a thirty-eighth switch are connected to the common mode level, the other end of the thirty-fourth switch is connected to one end of a fifth reset switch and one end of a fifth integrating capacitor, the other end of the fifth reset switch, the other end of the fifth integrating capacitor, the other end of the thirty-fifth switch and the first output end of the third operational amplifier, and the other end of the thirty-ninth switch is connected with one end of a sixth reset switch and one end of a sixth integrating capacitor, the other end of the sixth capacitor is connected with a non-inverting input end of a third operational amplifier and one end of a forty-th switch, and the other end of the sixth reset switch is connected with the other end of the sixth integrating capacitor, the other end of the forty-th switch and a second output end of the third operational amplifier and is used as a second output end of the third-stage integrator.
8. The readout circuit applied to the capacitive humidity sensor according to claim 7, wherein the feedforward path includes seventh to twelfth capacitors and forty-first to forty-sixth switches, one end of the seventh capacitor is connected to the other end of the twenty-first switch, the other end of the seventh capacitor is connected to one end of the ninth capacitor, one end of the twelfth capacitor and one end of the forty-first switch, one end of the eighth capacitor is connected to the other end of the thirty-first switch, the other end of the eighth capacitor is connected to one end of the tenth capacitor, one end of the eleventh capacitor and one end of the forty-second switch, the other end of the ninth capacitor is connected to one end of the forty-third switch and one end of the forty-fourteenth switch, the other end of the tenth capacitor is connected to one end of the forty-fifth switch and one end of the forty-sixth switch, the other end of the eleventh capacitor is connected to the other end of the thirty-sixth switch, the other end of the twelfth capacitor is connected with the other end of the twenty-sixth switch, the other end of the forty-first switch and the other end of the forty-second switch are connected to the common mode level, the other end of the forty-third switch is connected with the first output end of the third-stage integrator, the other end of the forty-fourth switch and the other end of the forty-sixth switch are connected to the common mode level, the other end of the forty-fifth switch is connected with the second output end of the third-stage integrator, and one end of the forty-first switch and one end of the forty-second switch are respectively used as the first output end and the second output end of the feedforward path.
9. The readout circuit applied to the capacitive humidity sensor according to claim 8, wherein the control terminals of the third switch, the thirteenth switch, the eighteenth switch, the fourteenth switch, the twenty-ninth switch, the thirty-third switch and the thirty-eighth switch are connected to the first clock signal output terminal of the clock signal generator, the control terminals of the fourth switch, the eighth switch, the twenty-third switch, the twenty-eighteen switch, the thirty-fourth switch and the thirty-ninth switch are connected to the second clock signal output terminal of the clock signal generator, the control terminals of the first switch, the fifth switch, the sixth switch, the ninth switch, the eleventh switch, the sixteenth switch, the twenty-second switch, the twenty-seventh switch, the thirty-eleventh switch, the thirty-fifth switch, the thirty-sixth switch and the forty switch are connected to the third clock signal output terminal of the clock signal generator, the control ends of the second switch, the seventh switch, the twelfth switch, the seventeenth switch, the twenty-first switch, the twenty-fifth switch, the twenty-sixth switch, the thirty-third switch, the thirty-twelfth switch and the seventeenth switch are connected with the fourth clock signal output end of the clock signal generator, the control ends of the fourteenth switch and the twentieth switch are connected with the fifth clock signal output end of the clock signal generator, and the control end of the fifteenth switch and the control end of the nineteenth switch are connected with the sixth clock signal output end of the clock signal generator.
10. A sensing circuit for a capacitive humidity sensor according to claim 9, wherein the relationship between the clock signals generated by the clock signal generator is: the first clock signal and the second clock signal are mutually reverse non-overlapped clocks; the third clock signal is a clock with synchronous rising edge and delayed falling edge of the first clock signal; the fourth clock signal is a clock delayed by the rising edge of the second clock signal; the fifth clock signal is the AND operation result of the fourth clock signal and the output signal of the Sigma-Delta modulator, and the sixth clock signal is the AND operation result of the fourth clock signal and the inverted signal of the output signal of the Sigma-Delta modulator.
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