CN105301284A - Low-power digital accelerometer interface circuit system - Google Patents
Low-power digital accelerometer interface circuit system Download PDFInfo
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- CN105301284A CN105301284A CN201510727317.XA CN201510727317A CN105301284A CN 105301284 A CN105301284 A CN 105301284A CN 201510727317 A CN201510727317 A CN 201510727317A CN 105301284 A CN105301284 A CN 105301284A
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- power consumption
- frequency
- delta modulator
- predistorter
- sigma delta
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Abstract
The invention belongs to the field of an MEMS inertia device, and specifically relates to a low-power digital accelerometer interface circuit system. The low-power digital accelerometer interface circuit system comprises a driving signal generation portion, a charge integrator, a front compensator, a sampling hold circuit, a third-order sigma-delta modulator and a one-bit electrostatic force feedback. The four parts does not have to work under a high frequency and can work under a quite low frequency, such that charge and discharge power consumption of mechanical capacitance and parasitic capacitance can be greatly reduced. An operational amplifier in the third-order sigma-delta modulator is replaced by an inverter, since the inverter can provide quite wide unit gain bandwidth under quite low static-state currents, though the 105 portion has a quite high work frequency, its power consumption is greatly reduced.
Description
Technical field
The invention belongs to MEMS inertia device field, be specifically related to a kind of low power consumption digital accelerometer interface circuit system.
Background technology
High-precision micromechanics MEMS (MicroElectromechanicalSystem) accelerometer is widely used in the fields such as Aero-Space, automobile, biomedicine, environmental monitoring because having the advantages such as miniaturization, intellectuality, integrated, high reliability, and noisiness, bias stability, DC precision are paid close attention in the mems accelerometer design being typically applied to these fields.But according to market analysis, consumer electronics remains the maximum application of current MESM accelerometer, in this type of application, except above several requirement, accelerometer also must have the characteristic of low-power consumption and numeral output.Sigma-Delta (Σ Δ) modulation technique realizes analog-to-digital important way, and along with the development of MEMS technology, Σ Δ modulation technique is introduced in the design of capacitor MEMS acceleration meter.The sensitive structure characteristic bandwidth of micro-mechanical accelerometer is usually narrower, therefore can obtain very high over-sampling rate (OSR) easily, thus restraint speckle effectively, improve sensing system performance.Adopt the close-loop feedback of Σ Δ modulation technology accelerometer, not only structure is simple, and bandwidth is high, is easy to adopt CMOS technology to realize, and, while realizing Closed loop operation mode, have also been obtained directly numeral export.
Have in a large number about the report of the capacitive accelerometer interface circuit of employing Σ Δ modulated structure at present, but all to there is a major issue in these circuit be exactly that power consumption is excessive, its reason has two: first, in order to reduce the quantizing noise of system, improve over-sampling rate, under whole system is all operated in a very high sample frequency, but too high sample frequency causes very large mechanical capacitance will carry out charging and discharging with identical frequency with stray capacitance, and then result in very high power consumption.Second, although the sensing unit with step low-pass characteristic can as the integrator in sigma Delta modulator, but because its low-down DC current gain causes system to have very low signal-quantizing noise ratio (SQNR), in order to improve SQNR, must after Sensitive Units the several electricity integrator of cascade, and this electricity integrator works equally in high frequency, operational amplifier wherein also consumes a large amount of power consumption.
The present invention invents based on above problem, its objective is to provide a kind of method that effectively can reduce system power dissipation, and provides a kind of low-power consumption, the high-precision micro-acceleration gauge interface circuit with digital output function.
Summary of the invention
The object of the present invention is to provide the low power consumption digital accelerometer interface circuit system of a kind of low-power consumption, high accuracy number output.
The object of the present invention is achieved like this:
The present invention includes drive singal generating unit (101), charge integrator (102), predistorter (103), sampling hold circuit (104), three rank sigma Delta modulators (105) and 1 electrostatic force feedback (106)
Drive singal generating unit (101), produces two-phase high-frequency drive square-wave signal, is carried in two fixed electordes up and down of sensitive structure respectively;
Charge integrator (102) forms capacitance-voltage change-over circuit jointly with sensing unit and drive singal generating unit (101), the change of the small capacitance of sensitive structure is converted to voltage signal, flows to the predistorter (104) of rear class;
Predistorter (103) provides preceding phase by increasing the mode at zero point near sensitive structure two open loop poles;
The discrete voltage signal that front stage circuits produces is converted into continuous voltage signal and flows to three rank electricity sigma Delta modulator (105) process of rear class by sampling hold circuit (104); The capacitance variations that drive singal generating unit (101), charge integrator (102), predistorter (103) and sampling hold circuit (104) sense acceleration meter sensing unit are small, and be converted into continuous print magnitude of voltage;
Three rank electricity sigma Delta modulator (105) complete AD conversion and reduce quantizing noise, the continuous voltage signal that prime sampling hold circuit (104) produces are converted into the pulse-width signal (PWM) of 1bit;
1 electrostatic force feedback (106), according to the 1bitPWM signal that three rank electricity sigma Delta modulator (105) export, judges the feedback force direction feeding back to sensitive structure.
Drive singal generating unit (101), charge integrator (102), predistorter (103) and sampling hold circuit (104) frequency of operation are f
1, three rank electricity sigma Delta modulator (105) frequency of operation are f
2, and f
1be less than f
2; The power consumption of drive singal generating unit (101), charge integrator (102), predistorter (103) and sampling hold circuit (104) all and frequency f
1be directly proportional.
Three rank electricity sigma Delta modulator (105) work in high frequency f
2under, operational amplifier cascade phase inverter wherein substitutes.
Beneficial effect of the present invention is:
The present invention is with two important difference of existing document structure: the first, and drive singal generating unit (101), charge integrator (102), predistorter (103), sampling hold circuit (104) frequency of operation are f
1, three rank electricity sigma Delta modulator (105) frequency of operation are f
2, and f
1much smaller than f
2.In the structure that this invention proposes, 101,102,103,104 mainly complete the change of sensitization capacitance are converted into continuous print magnitude of voltage, and be supplied to 105, these four parts can not need work in high frequency like this, and only need to work in lower frequency, can greatly reduce mechanical capacitance and stray capacitance discharge and recharge power consumption.Three rank electricity sigma Delta modulator (105) then complete Σ Δ AD conversion, and therefore its frequency of operation must be very high, to provide higher over-sampling rate.Second, in the present invention, operational amplifier phase inverter in three rank electricity sigma Delta modulator (105) substitutes, because phase inverter can provide very wide unity gain bandwidth under extremely low quiescent current, although so 105 have very high frequency of operation, its power consumption greatly reduces.
Accompanying drawing explanation
Fig. 1 is low power consumption digital accelerometer interface circuit system chart;
Fig. 2 is switched-capacitor integrator;
Fig. 3 is the three rank electricity sigma Delta modulators based on phase inverter.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described further:
The invention belongs to MEMS inertia device field, the interface circuitry that the capacitance microaccelerator numeral being specifically related to a kind of low-power consumption exports.Present system structure comprises drive singal generating unit, charge integrator, predistorter, sampling hold circuit, electricity integrator and 1 electrostatic force feedback.Fundamental purpose of the present invention proposes the Low-power Technology that a kind of numeral exports accelerometer interface circuit, low frequency is worked in by making the drive singal generating unit in Circuits System, charge integrator, predistorter, sampling hold circuit, and under electricity integrator works in high frequency, and use phase inverter substitutes the operational amplifier in electricity integrator, both system power dissipation was greatly reduced, reduce chip area, effectively can improve system accuracy again.
The present invention includes drive singal generating unit (101), charge integrator (102), predistorter (103), sampling hold circuit (104), three rank electricity sigma Delta modulator (105) and 1 electrostatic force feedback (106)
Drive singal generating unit (101), produces two-phase high-frequency drive square-wave signal, is carried in two fixed electordes up and down of sensitive structure respectively;
Charge integrator (102) forms capacitance-voltage change-over circuit jointly with sensing unit and drive singal generating unit (101), the change of the small capacitance of sensitive structure is converted to voltage signal, flows to the predistorter (104) of rear class;
Predistorter (103) provides preceding phase by increasing the mode at zero point near sensitive structure two open loop poles, improves the stability of system;
The discrete voltage signal that front stage circuits produces is converted into continuous voltage signal by sampling hold circuit (104), and flows to three rank electricity sigma Delta modulator (105) process of rear class;
Three rank electricity sigma Delta modulator (105) have been AD conversion and the critical component reducing quantizing noise, the continuous voltage signal that prime sampling hold circuit (104) produces are converted into the pulse-width signal (PWM) of 1bit;
1 electrostatic force feedback (106), according to the 1bitPWM signal that three rank electricity sigma Delta modulator (105) export, judges the feedback force direction feeding back to sensitive structure.
Fig. 1 represents the low power consumption digital accelerometer interface circuit system chart of present embodiment.
As shown in Figure 1, this interface circuitry has: drive singal generating unit (101), charge integrator (102), predistorter (103), sampling hold circuit (104), three rank electricity sigma Delta modulator (105), 1 electrostatic force feedback (106).
In FIG, C
s1and C
s2two variable capacitances be made up of two fixed electordes and the intermediate active mass of sensing unit, switch S 1, S2, S3, S4 are under the not overlapping clock clk1 of two-phase and clk2 effect, produce two opposite polarity square-wave signals, be carried on two fixed electordes of sensing unit respectively, composition drive singal generating unit (101).Under the effect of drive singal generating unit (101), the converts displacement of sensing unit movable mass block is the change of the quantity of electric charge, the change of this quantity of electric charge is converted to magnitude of voltage by charge integrator (102), therefore, drive singal generating unit (101), sensing unit and charge integrator (102) constitute Capacitance to Voltage Converter jointly.Amplifier AMP1, switch S 7, S8, S9, electric capacity C
iand C
cDScomposition charge integrator (102), its output can be expressed as:
C
cDSfor correlated-double-sampling electric capacity, at clk1 clock phase time C
cDSthe imbalance of sampling amplifier AMP1 and the 1/f noise of circuit, complete imbalance and the 1/f noise of subtraction operation in order to eliminate circuit in the identical amount of clk2 clock phase sampler.Switch S 10-S20 and electric capacity C
cP1-C
cP3composition predistorter (103), its z territory transition function can be expressed as:
Wherein C
cP2=C
cP3=α C
cP1.Amplifier AMP2, switch S 21, electric capacity C
sHcomposition sampling hold circuit (104), is converted to continuous signal by voltage signal discrete for front stage circuits.This continuous voltage signal enters into three rank electricity sigma Delta modulator (105), at high sample frequency f
2under effect, by the pwm signal of simulating signal conversion in order to 1bit, this signal is also the output signal of system.Switch S 22, S23, S24, under 1bitPWM and clock clk7 controls, select the voltage feeding back to sensing unit to be V
fbor-V
fb, complete 1bit electrostatic force feedback function.
Below in conjunction with the acquisition of Fig. 1 illustrative system low-power consumption.
The total power consumption of this interface circuit can be expressed as:
Wherein Section 1 represents in frequency f
1under dynamic power consumption to sensitization capacitance discharge and recharge, under normal circumstances, sensitization capacitance C
s1and C
s2capacitance all very large (being generally tens to hundreds of pF), therefore Section 1 is the most important components of total system power consumption, from formula (3), reduces f
1effectively can reduce power consumption.In addition, P
int, P
comp, P
sHrepresent the power consumption of charge integrator (102), potential quality compensator (103) and sampling hold circuit (104) respectively, in the invention, the frequency of operation of these three modules is also f
1, and its power consumption and f
1be directly proportional, therefore reduce f
1greatly can reduce the power consumption of system.
Work as f
1when frequency is lower, system cannot obtain high over-sampling rate, also effectively cannot reduce quantizing noise, improves system accuracy.For addressing this problem, drive singal generating unit (101) is utilized in the present invention, charge integrator (102), predistorter (103), with sampling hold circuit (104), sensitization capacitance change is converted to continuous print analog voltage signal, there is provided high over-sampling rate by three rank electricity sigma Delta modulator (105), and effectively reduce system quantifies noise.Therefore the frequency of operation f on three rank electricity sigma Delta modulator (105)
2will far above f
1, due to f
2far above f
1, the operational amplifier in electricity integrator becomes another important component part in total power consumption.For addressing this problem, have employed cascade phase inverter in the present invention and substituting operational amplifier, effectively reducing power consumption, reduce area.
Below in conjunction with the realization of Fig. 2 and Fig. 3 introduction based on low-power consumption three rank electricity sigma Delta modulator (105) of phase inverter.
Because integrator is most important ingredient in sigma Delta modulator, first introduce the realization of the switched-capacitor integrator based on phase inverter.Fig. 2 left-half is the traditional switch capacitance integrator based on operational amplifier, wherein φ
1and φ
2it is the not overlapping clock of two-phase.Fig. 2 right half part is the switched-capacitor integrator based on phase inverter, and its implementation procedure is as follows: at φ
1phase, input signal is sampled sampling capacitance C
son, the input end V of phase inverter
xbe approximately equal to the offset voltage V of phase inverter
oFF, therefore electric capacity C
cDSthe voltage difference at two ends is V
oFF.At φ
2the phase place incipient stage, electric capacity C
sone end be connected to ground, the V therefore in Fig. 2 right half part
gpoint voltage becomes-V
i, V
ifor φ
1clock phase finish time samples C
son voltage, and V
xbecome V
oFF-V
i. when closed loop is formed, because negative feedback forces V
xvoltage is V
oFF, and due to C
cDSmaintain voltage V
oFFand make V
gpoint becomes signal ground.Therefore V
gpoint can be regarded as virtually, and electric charge is by electric capacity C
stransfer to C
i, the relation between input and output can be expressed as:
C
Sv
I(n+1/2)+C
Iv
O(n)＝C
Iv
O(n+1)
Its z territory transition function can be expressed as
Visible, although phase inverter only has an input end, but still switched-capacitor integrator function can be realized.Phase inverter can be easy to obtain high gain bandwidth (GB) under very low quiescent dissipation, can work at higher frequencies.This phase inverter have employed cascade phase inverter in the present invention, and the common bank tube of N-type and P type can separate stray capacitance, improve signal and set up precision, and cascode structure can improve the DC current gain of phase inverter greatly.
Fig. 3 gives the realization of the three rank sigma Delta modulators (105) based on phase inverter, and three rank sigma Delta modulators (105) form by based on the integrator of phase inverter, 1bitDA converter, summing circuit and comparer.Wherein, switch S
1-1-S
5-1, electric capacity C
sp1, C
ip1, C
cDS1form first integrator with phase inverter INV1, in like manner second is made up of identical switch, electric capacity and phase inverter with the 3rd integrator.Switch S
6-S
11, electric capacity C
p1-C
p4constitute node summing circuit, switch S
12, S
13and reference voltage Vh, Vl constitute 1bitDA converter.Three rank sigma Delta modulators (105) in the present invention have employed low imbalance structure, input signal is not directly added in switched-capacitor integrator input end in such an embodiment, reduce the requirement to Amplifier linearity, be very suitable for the operation of phase inverter, feedforward path summation adopts electric capacity arranged side by side to realize in the input node of comparer.Due to the use of phase inverter, the power consumption of three rank sigma Delta modulators (105) is greatly reduced.
Claims (3)
1. a low power consumption digital accelerometer interface circuit system, comprise drive singal generating unit (101), charge integrator (102), predistorter (103), sampling hold circuit (104), three rank sigma Delta modulators (105) and 1 electrostatic force feedback (106), it is characterized in that:
Drive singal generating unit (101), produces two-phase high-frequency drive square-wave signal, is carried in two fixed electordes up and down of sensitive structure respectively;
Charge integrator (102) forms capacitance-voltage change-over circuit jointly with sensing unit and drive singal generating unit (101), the change of the small capacitance of sensitive structure is converted to voltage signal, flows to the predistorter (104) of rear class;
Predistorter (103) provides preceding phase by increasing the mode at zero point near sensitive structure two open loop poles;
The discrete voltage signal that front stage circuits produces is converted into continuous voltage signal and flows to three rank electricity sigma Delta modulator (105) process of rear class by sampling hold circuit (104); The capacitance variations that drive singal generating unit (101), charge integrator (102), predistorter (103) and sampling hold circuit (104) sense acceleration meter sensing unit are small, and be converted into continuous print magnitude of voltage;
Three rank electricity sigma Delta modulator (105) complete AD conversion and reduce quantizing noise, the continuous voltage signal that prime sampling hold circuit (104) produces are converted into the pulse-width signal (PWM) of 1bit;
1 electrostatic force feedback (106), according to the 1bitPWM signal that three rank electricity sigma Delta modulator (105) export, judges the feedback force direction feeding back to sensitive structure.
2. a kind of low power consumption digital accelerometer interface circuit system according to claim 1, is characterized in that: drive singal generating unit (101), charge integrator (102), predistorter (103) and sampling hold circuit (104) frequency of operation are f
1, three rank electricity sigma Delta modulator (105) frequency of operation are f
2, and f
1be less than f
2; The power consumption of drive singal generating unit (101), charge integrator (102), predistorter (103) and sampling hold circuit (104) all and frequency f
1be directly proportional.
3. a kind of low power consumption digital accelerometer interface circuit system according to claim 1, is characterized in that: three rank electricity sigma Delta modulator (105) work in high frequency f
2under, operational amplifier cascade phase inverter wherein substitutes.
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| CN201510727317.XA CN105301284B (en) | 2015-10-30 | 2015-10-30 | A kind of low power consumption digital accelerometer interface circuit system |
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| CN105785075A (en) * | 2016-02-25 | 2016-07-20 | 中国科学院地质与地球物理研究所 | Capacitance-type inertial sensor digital servo circuit |
| CN109029437A (en) * | 2018-10-25 | 2018-12-18 | 哈尔滨工业大学 | Three Degree Of Freedom closed loop gyro digital interface circuit |
| CN109708669A (en) * | 2019-02-28 | 2019-05-03 | 重庆理工大学 | A kind of accelerometer signal processing system and method |
| CN110470861A (en) * | 2018-05-11 | 2019-11-19 | 中国科学院声学研究所 | A kind of MEMS capacitive accelerometer interface circuit |
| CN117155070A (en) * | 2023-10-30 | 2023-12-01 | 湃晟芯(苏州)科技有限公司 | Detection circuit of high-frequency DCDC switching power supply |
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