CN105301284B - A kind of low power consumption digital accelerometer interface circuit system - Google Patents
A kind of low power consumption digital accelerometer interface circuit system Download PDFInfo
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- CN105301284B CN105301284B CN201510727317.XA CN201510727317A CN105301284B CN 105301284 B CN105301284 B CN 105301284B CN 201510727317 A CN201510727317 A CN 201510727317A CN 105301284 B CN105301284 B CN 105301284B
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Abstract
The invention belongs to MEMS inertia devices fields, and in particular to a kind of low power consumption digital accelerometer interface circuit system.The present invention includes drive signal generating unit, charge integrator, predistorter, sampling hold circuit, three rank sigma Delta modulators and 1 electrostatic force feedback.Work can be not required in high frequency in four parts, and only needs to work in lower frequency, can substantially reduce to mechanical capacitance and parasitic capacitance charge and discharge electrical power consumed.Operational amplifier in three rank electricity sigma Delta modulators is substituted with phase inverter, and since phase inverter can provide very wide unity gain bandwidth under extremely low quiescent current, so while 105 have very high working frequency, but its power consumption greatly reduces.
Description
Technical field
The invention belongs to MEMS inertia devices fields, and in particular to a kind of low power consumption digital accelerometer interface circuit system
System.
Background technology
High-precision micromechanics MEMS (Micro Electromechanical System) accelerometers are because with small-sized
Change, intelligent, integrated, high reliability the advantages that and be widely used in aerospace, automobile, biomedicine, environmental monitoring
Noise characteristic, bias stability, direct current essence are focused in the fields of grade, typically the mems accelerometer design applied to these fields
Degree.But according to market analysis, consumer electronics is still the application field of current MESM accelerometers maximum, in this kind of application
In, except above several requirements, accelerometer must also have the characteristic of low-power consumption and numeral output.Sigma-Delta(Σ
Δ) modulation technique be realize analog-to-digital conversion important way, with the development of MEMS technology, Σ Δ modulation techniques are introduced in electricity
In the design of appearance formula mems accelerometer.The sensitive structure characteristic bandwidth of micro-mechanical accelerometer is usually relatively narrow, therefore can hold very much
It changes places and obtains very high over-sampling rate (OSR), so as to effectively inhibit noise, improve sensing system performance.Using Σ Δ tune
Technology processed realizes the closed loop feedback of accelerometer, is not only simple in structure, and bandwidth is high, is easy to realize using CMOS technology, moreover,
Direct numeral output has also been obtained while realizing Closed loop operation mode.
There is the report largely on the capacitive accelerometer interface circuit using Σ Δ modulated structures at present, however
These circuits are exactly that power consumption is excessive all there are a major issue, and there are two reasons：First, in order to which the quantization for reducing system is made an uproar
Sound improves over-sampling rate, and whole system is all operated under a very high sample frequency, however excessively high sample frequency cause it is non-
Often big mechanical capacitance and parasitic capacitance will be charged and discharged with identical frequency, and then result in very high power consumption.The
Two, although the sensing unit with step low-pass characteristic can be as the integrator in sigma Delta modulator, since it is very low
DC current gain cause system that there is very low signal-quantizing noise ratio (SQNR), in order to improve SQNR, it is necessary to sensitive single
Several electricity integrators are cascaded after position, and the electricity integrator equally works in high frequency, operational amplifier therein also disappears
A large amount of power consumptions are consumed.
The present invention is invented based on problem above, and its purpose is to provide a kind of can effectively reduce system power dissipation
Method, and a kind of low-power consumption, the high-precision micro-acceleration gauge interface circuit with numeral output are provided.
The content of the invention
It is an object of the invention to provide the low power consumption digital accelerometer interfaces that a kind of low-power consumption, high accuracy number export
Circuit system.
The object of the present invention is achieved like this：
The present invention includes drive signal generating unit (101), charge integrator (102), predistorter (103), sampling guarantor
Circuit (104), three rank sigma Delta modulators (105) and 1 electrostatic force feedback (106) are held,
Drive signal generating unit (101) generates two-phase high-frequency drive square-wave signal, loads respectively above and below sensitive structure
Two fixed electrodes；
Charge integrator (102) collectively constitutes capacitance-voltage conversion electricity with sensing unit and drive signal generating unit (101)
The small capacitance variation of sensitive structure is converted to voltage signal, is conveyed to the predistorter (104) of rear class by road；
Predistorter (103) provides preposition phase by way of increasing zero point near two open loop poles of sensitive structure
Position；
The discrete voltage signal that front stage circuits generate is converted into continuous voltage signal and conveyed by sampling hold circuit (104)
It is handled to three rank electricity sigma Delta modulators (105) of rear class；It is drive signal generating unit (101), charge integrator (102), preposition
Compensator (103) and sampling hold circuit (104) detect the small capacitance variations of accelerometer sensitive unit, and are converted into continuous
Voltage value；
Three rank electricity sigma Delta modulators (105) complete AD conversion and reduce quantizing noise, by prime sampling hold circuit
(104) the continuous voltage signal generated is converted into the pulse-width signal (PWM) of 1bit；
1 electrostatic force feedback (106) according to the 1bit pwm signals that three rank electricity sigma Delta modulators (105) export, judges
Feed back to the feedback force direction of sensitive structure.
Drive signal generating unit (101), charge integrator (102), predistorter (103) and sampling hold circuit
(104) working frequency is f1, three rank electricity sigma Delta modulator (105) working frequencies are f2, and f1Less than f2；Drive signal generates
Portion (101), charge integrator (102), the power consumption of predistorter (103) and sampling hold circuit (104) with frequency f1Into
Direct ratio.
Three rank electricity sigma Delta modulators (105) work in high frequency f2Under, operational amplifier therein cascade reverse phase
Device substitutes.
The beneficial effects of the present invention are：
The present invention is compared with two important differences of document structure：First, drive signal generating unit (101), charge
Integrator (102), predistorter (103), sampling hold circuit (104) working frequency are f1, three rank electricity sigma Delta modulators
(105) working frequency is f2, and f1Much smaller than f2.In the structure proposed in the invention, 101,102,103,104 main completions
The variation of sensitization capacitance is converted into continuous voltage value, and is supplied to 105, so this four parts can need not be operated in
It under high frequency, and only needs to work in lower frequency, can substantially reduce to mechanical capacitance and parasitic capacitance charge and discharge electrical power consumed.
Three rank electricity sigma Delta modulators (105) then complete Σ Δ AD conversion, therefore its working frequency must be very high, to provide higher mistake
Sample rate.Second, in of the invention, the operational amplifier in three rank electricity sigma Delta modulators (105) is substituted with phase inverter, due to
Phase inverter can provide very wide unity gain bandwidth under extremely low quiescent current, so while 105 have very high work
Working frequency, but its power consumption greatly reduces.
Description of the drawings
Fig. 1 is low power consumption digital accelerometer interface circuit system block diagram；
Fig. 2 is switched-capacitor integrator；
Fig. 3 is the three rank electricity sigma Delta modulators based on phase inverter.
Specific embodiment
The present invention is described further below in conjunction with the accompanying drawings：
The invention belongs to MEMS inertia devices fields, and in particular to a kind of capacitance microaccelerator number of low-power consumption is defeated
The interface circuitry gone out.Present system structure includes drive signal generating unit, charge integrator, predistorter, sampling
Holding circuit, electricity integrator and 1 electrostatic force feedback.The main object of the present invention is to propose a kind of numeral output accelerometer
The Low-power Technology of interface circuit, by make drive signal generating unit in circuit system, charge integrator, predistorter,
Sampling hold circuit works in low frequency, and electricity integrator is worked under high frequency, and is substituted using phase inverter in electricity integrator
Operational amplifier, both greatly reduce system power dissipation, reduce chip area, and system accuracy can be effectively improved.
The present invention includes drive signal generating unit (101), charge integrator (102), predistorter (103), sampling guarantor
Circuit (104), three rank electricity sigma Delta modulators (105) and 1 electrostatic force feedback (106) are held,
Drive signal generating unit (101) generates two-phase high-frequency drive square-wave signal, loads respectively above and below sensitive structure
Two fixed electrodes；
Charge integrator (102) collectively constitutes capacitance-voltage conversion electricity with sensing unit and drive signal generating unit (101)
The small capacitance variation of sensitive structure is converted to voltage signal, is conveyed to the predistorter (104) of rear class by road；
Predistorter (103) provides preposition phase by way of increasing zero point near two open loop poles of sensitive structure
The stability of system is improved in position；
The discrete voltage signal that front stage circuits generate is converted into continuous voltage signal by sampling hold circuit (104), and defeated
Give three rank electricity sigma Delta modulators (105) processing of rear class；
Three rank electricity sigma Delta modulators (105) are the critical components completed AD conversion and reduce quantizing noise, and prime is adopted
The continuous voltage signal that sample holding circuit (104) generates is converted into the pulse-width signal (PWM) of 1bit；
1 electrostatic force feedback (106) according to the 1bit pwm signals that three rank electricity sigma Delta modulators (105) export, judges
Feed back to the feedback force direction of sensitive structure.
Fig. 1 shows the low power consumption digital accelerometer interface circuit system block diagrams of present embodiment.
As shown in Figure 1, the interface circuitry has：Drive signal generating unit (101), charge integrator (102) are preposition
Compensator (103), sampling hold circuit (104), three rank electricity sigma Delta modulators (105), 1 electrostatic force feedback (106).
In Fig. 1, CS1And CS2Two be made of two fixation electrodes and intermediate active mass blocks of sensing unit are variable
Capacitance, switch S1, S2, S3, S4 generate two opposite polarity square wave letters under not overlapping clock clk1 and the clk2 effect of two-phase
Number, it loads respectively on two fixed electrodes of sensing unit, composition drive signal generating unit (101).It is generated in drive signal
Under the action of portion (101), the displacement of sensing unit movable mass block is converted into the variation of the quantity of electric charge, which changes by charge
Integrator (102) is converted to voltage value, and therefore, drive signal generating unit (101), sensing unit and charge integrator (102) are altogether
It is same to constitute Capacitance to Voltage Converter.Amplifier AMP1, S7, S8, S9, capacitance C are switchedIAnd CCDSForm charge integrator
(102), output is represented by：
CCDSFor correlated-double-sampling capacitance, the C in clk1 clock phasesCDSThe imbalance of sampling amplifier AMP1 and the 1/f of circuit
Noise, mutually samples identical amount in clk2 clocks and completes subtraction operation to eliminate imbalance and the 1/f noise of circuit.Switch
S10-S20 and capacitance CCP1-CCP3Predistorter (103) is formed, z domains transfer function is represented by：
Wherein CCP2=CCP3=α CCP1.Amplifier AMP2, switch S21, capacitance CSHSampling hold circuit (104) is formed, it will
The discrete voltage signal of front stage circuits is converted to continuous signal.The continuous voltage signal enters three rank electricity sigma Delta modulators
(105) in, in high sample frequency f2Under effect, the pwm signal of 1bit is converted analog signals into, which is also system
Export signal.S22, S23, S24 are switched under 1bit PWM and clock clk7 controls, select to feed back to the voltage of sensing unit for
VfbOr-Vfb, complete 1bit electrostatic force feedback functions.
Illustrate the acquisition of system low-power consumption with reference to Fig. 1.
The total power consumption of the interface circuit is represented by：
Wherein Section 1 is represented in frequency f1Under to the dynamic power consumptions of sensitization capacitance charge and discharge, it is generally the case that sensitive electrical
Hold CS1And CS2Capacitance is all very big (generally tens to hundreds of pF), therefore Section 1 is the most important composition of total system power consumption
Part, by formula (3) as it can be seen that reducing f1Power consumption can be effectively reduced.In addition, Pint、Pcomp、PSHCharge integrator is represented respectively
(102), the power consumption of potential quality compensator (103) and sampling hold circuit (104), in the invention, the work frequency of these three modules
Rate is also f1, and its power consumption and f1It is directly proportional, therefore reduce f1The power consumption of system can be substantially reduced.
Work as f1When frequency is relatively low, system can not obtain high over-sampling rate, can not also be effectively reduced quantizing noise, improve
System accuracy.To solve the problems, such as this, drive signal generating unit (101) is utilized in the present invention, charge integrator (102) is preposition
Sensitization capacitance variation is converted to continuous analog voltage signal by compensator (103) and sampling hold circuit (104), by three ranks
Electricity sigma Delta modulator (105) provides high over-sampling rate, and effectively reduces system quantifies noise.Therefore three rank electricity Σ Δ tune
The working frequency f of device (105) processed2To be far above f1, due to f2Far above f1, the operational amplifier in electricity integrator becomes total
Another important component in power consumption.To solve this problem, cascade phase inverter is employed in the present invention and substitutes fortune
Amplifier is calculated, power consumption is effectively reduced, reduces area.
With reference to the realization of low-power consumption three rank electricity sigma Delta modulator (105) of Fig. 2 and Fig. 3 introductions based on phase inverter.
Since integrator is most important component in sigma Delta modulator, the switching capacity based on phase inverter is introduced first
The realization of integrator.Fig. 2 left-halfs are the traditional switch capacitance integrators based on operational amplifier, wherein φ1And φ2It is double
Clock is not overlapped mutually.Fig. 2 right half parts are the switched-capacitor integrators based on phase inverter, realize that process is as follows：In φ1Phase,
Input signal is sampled sampling capacitance CSOn, the input terminal V of phase inverterXIt is approximately equal to the offset voltage V of phase inverterOFF, therefore
Capacitance CCDSThe voltage difference at both ends is VOFF.In φ2Phase incipient stage, capacitance CSOne end be connected to ground, therefore Fig. 2 right sides
V in pointGPoint voltage becomes-VI, VIFor φ1Clock phase finish time samples CSOn voltage, and VXBecome VOFF-VIWhen
During closed loop formation, since negative feedback forces VXVoltage is VOFF, and due to CCDSMaintain voltage VOFFAnd cause VGPoint becomes
Signal ground.Therefore VGPoint is considered as virtually, and charge is by capacitance CSIt is transferred to CI, the relation between input and output can represent
For：
CSvI(n+1/2)+CIvO(n)=CIvO(n+1)
Its z domains transfer function is represented by
As it can be seen that although phase inverter is only there are one input terminal, but still switched-capacitor integrator function can be realized.Phase inverter
It can be easy to obtain high gain bandwidth under very low quiescent dissipation, can work at higher frequencies.In the present invention
The phase inverter employs cascade phase inverter, and the common bank tube of N-type and p-type can separate parasitic capacitance, improves signal and establishes essence
Degree, and cascode structure can greatly improve the DC current gain of phase inverter.
Fig. 3 gives the realization of the three rank sigma Delta modulators (105) based on phase inverter, three rank sigma Delta modulators (105) by
Integrator based on phase inverter, 1bit D/A converters, summing circuit and comparator composition.Wherein, S is switched1-1-S5-1, capacitance
Csp1、Cip1、CCDS1First integrator is formed with phase inverter INV1, similarly second and the 3rd integrator are opened by identical
It closes, capacitance and phase inverter form.Switch S6-S11, capacitance Cp1-Cp4Node summing circuit is constituted, switchs S12、S13And with reference to electricity
Pressure Vh, Vl constitute 1bit D/A converters.Three rank sigma Delta modulators (105) in the present invention employ low imbalance structure, at this
Input signal is not applied directly to switched-capacitor integrator input terminal in kind structure, reduces the requirement to Amplifier linearity, non-
The operation of phase inverter is very suitable for, feedforward path summation is realized using the input node of capacitance arranged side by side in comparator.Due to anti-
The use of phase device so that the power consumption of three rank sigma Delta modulators (105) greatly reduces.
Claims (1)
1. a kind of digital accelerometer interface circuitry, including drive signal generating unit (101), charge integrator (102), preceding
Compensator (103), sampling hold circuit (104), three rank sigma Delta modulators (105) and 1 electrostatic force feedback (106) are put, it is special
Sign is：
Drive signal generating unit (101) generates two-phase high-frequency drive square-wave signal, loads two up and down in sensitive structure respectively
Fixed electrode；
Charge integrator (102) collectively constitutes capacitance-voltage conversion circuit with sensing unit and drive signal generating unit (101),
The small capacitance variation of sensitive structure is converted into voltage signal, is conveyed to the predistorter (104) of rear class；
Predistorter (103) provides preceding phase by way of increasing zero point near two open loop poles of sensitive structure；
After the discrete voltage signal that front stage circuits generate is converted into continuous voltage signal and is conveyed to by sampling hold circuit (104)
Three rank electricity sigma Delta modulators (105) processing of grade；Drive signal generating unit (101), charge integrator (102), pre-compensating
Device (103) and sampling hold circuit (104) detect the small capacitance variations of accelerometer sensitive unit, and are converted into continuous electricity
Pressure value；
Three rank electricity sigma Delta modulators (105) complete AD conversion and reduce quantizing noise, and prime sampling hold circuit (104) is produced
Raw continuous voltage signal is converted into the pulse-width signal (PWM) of 1bit；
1 electrostatic force feedback (106) according to the 1bit pwm signals that three rank electricity sigma Delta modulators (105) export, judges to feed back
Return the feedback force direction of sensitive structure.
Drive signal generating unit (101), charge integrator (102), predistorter (103) and sampling hold circuit (104) work
Working frequency is f1, three rank electricity sigma Delta modulator (105) working frequencies are f2, and f1Less than f2；Drive signal generating unit (101),
The power consumption of charge integrator (102), predistorter (103) and sampling hold circuit (104) with frequency f1It is directly proportional；
Three rank electricity sigma Delta modulators (105) work in high frequency f2Under, operational amplifier therein is replaced with cascade phase inverter
Generation.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105785075B (en) * | 2016-02-25 | 2018-09-14 | 中国科学院地质与地球物理研究所 | A kind of condenser type inertial sensor digital servo circuit |
| CN105785074B (en) * | 2016-02-25 | 2018-07-20 | 中国科学院地质与地球物理研究所 | A kind of inertial sensor capacitance detecting accelerometer |
| CN110470861B (en) * | 2018-05-11 | 2020-12-25 | 中国科学院声学研究所 | MEMS capacitive accelerometer interface circuit |
| CN109029437B (en) * | 2018-10-25 | 2021-03-30 | 哈尔滨工业大学 | Three-freedom closed-loop gyro digital interface circuit |
| CN109708669B (en) * | 2019-02-28 | 2020-10-02 | 重庆理工大学 | Accelerometer signal processing system and method |
| CN117155070B (en) * | 2023-10-30 | 2023-12-29 | 湃晟芯(苏州)科技有限公司 | Detection circuit of high-frequency DCDC switching power supply |
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