CN110146558A - Reading circuit and its control method applied to capacitance type humidity sensor - Google Patents
Reading circuit and its control method applied to capacitance type humidity sensor Download PDFInfo
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- CN110146558A CN110146558A CN201910525011.4A CN201910525011A CN110146558A CN 110146558 A CN110146558 A CN 110146558A CN 201910525011 A CN201910525011 A CN 201910525011A CN 110146558 A CN110146558 A CN 110146558A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/02—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance
- G01N27/22—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance
- G01N27/223—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance for determining moisture content, e.g. humidity
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/02—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance
- G01N27/22—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance
- G01N27/228—Circuits therefor
Abstract
The present invention relates to a kind of reading circuits and its control method applied to capacitance type humidity sensor.The reading circuit includes multiple selector, capacitive digital converter, and the capacitive digital converter includes Sigma-Delta modulator and decimation filter of digital；The input terminal of the multiple selector and the output end of capacitance type humidity sensor connect, the output end of multiple selector is connected through the input terminal of Sigma-Delta modulator and decimation filter of digital, digital signal output end of the output end of decimation filter of digital as entire reading circuit.The present invention can apply the measurement in a variety of capacitance type humidity sensors, the inductance capacitance signal of capacitance type humidity sensor is converted directly into digital signal output, in order to be directly connected to modern digital signal processor.
Description
Technical field
The present invention relates to a kind of reading circuits and its control method applied to capacitance type humidity sensor.
Background technique
In recent years, the demand that people monitor ambient humidity is more and more, ambient humidity and temperature to people's lives with
Manufacture has the meaning of no less important.In weather monitoring, medical safety, logistics monitoring, food protection, aerospace, automobile electricity
Son etc. all be unable to do without detecting and controlling for humidity.With the continuous development of science, occur in the market various types of wet
Spend sensor, such as electric resistance moisture sensor, capacitance type humidity sensor, pressure resistance type humidity sensor, beam type humidity
Sensor etc..Wherein, the property such as capacitance type humidity sensor has simple structure, high sensitivity, low in energy consumption, temperature characterisitic is good
Can, it is widely applied.
The main working principle of capacitance type humidity sensor is will to be converted to capacitance variations to measuring moisture in environment.Capacitor
The inductance capacitance of formula humidity sensor is very small, usually pF magnitude.Therefore capacitance type humidity sensor needs a reading electricity
Road reads small signal.Generally by oscillator type, alternating current bridge-type or switched capacitive circuit to condenser type humidity
Sensor carries out signal-obtaining, and the humicap of sensor is converted to frequency or voltage output by these reading circuits.This kind of reading
The output signal of circuit only has a kind of measurement pattern out, can only carry out the measurement of the perhaps single capacitor of differential electrical, and cannot
It is directly connected to the port of modern digital signal processor, it is also necessary to pass through further conversion process.
Summary of the invention
The purpose of the present invention is to provide a kind of reading circuit and its control method applied to capacitance type humidity sensor,
The measurement in a variety of capacitance type humidity sensors can be applied, the inductance capacitance signal of capacitance type humidity sensor is directly converted
It is exported for digital signal, in order to be directly connected to modern digital signal processor.
To achieve the above object, the technical scheme is that a kind of reading electricity applied to capacitance type humidity sensor
Road, including multiple selector, capacitive digital converter, the capacitive digital converter include Sigma-Delta modulator sum number
Word decimation filter；The input terminal of the multiple selector and the output end of capacitance type humidity sensor connect, multiple selector
Output end through the input terminal of Sigma-Delta modulator and decimation filter of digital connect, the output of decimation filter of digital
Hold the digital signal output end as entire reading circuit.
In an embodiment of the present invention, the multiple selector includes first to the tenth and door, first to the 5th or door, the
One to the 5th first input end with the first input end of door as entire multiple selector, the 6th to the tenth is defeated with the first of door
Enter second input terminal of the end as entire multiple selector, first and door the second input terminal as clock signal input terminal, with
First clock signal output terminal of clock signal generator connects, and second is defeated with the second of the second input terminal of door, third and door
Enter end, the 6th with the second input terminal of door, the 8th with the second input terminal of door, the 9th with the second input terminal of door as number electricity
Source input terminal, the 4th with the second input terminal of door, the 5th with the second input terminal of door, the 7th with the second input terminal of door, the tenth
With the second input terminal of door as digital ground terminal, first with the output end of door, the 6th with the output end of door respectively with first or door
Two input terminals connection, second connect with two input terminals of second or door with the output end of door, the 7th with the output end of door respectively,
The output end of third and door, the 8th connect with two input terminals of third or door respectively with the output end of door, the 4th with the output of door
End the 9th is connect with two input terminals of the 4th or door respectively with the output end of door, and the 5th is defeated with door with the output end of door, the tenth
Outlet is connect with two input terminals of the 5th or door respectively, first to the 5th or door output end respectively as entire multiple selector
The first to the 5th output end.
In an embodiment of the present invention, the Sigma-Delta modulator includes feedback network, is controlled by multiple selector
Switching circuit, first order integrator, second level integrator, third level integrator, feedforward path, quantizer；The Sigma-
Delta modulator further includes the first compensating electric capacity connecting with first order integrator, the second compensating electric capacity；The switching circuit packet
Include the first to the 5th multidiameter option switch, the control terminal of the first to the 5th multidiameter option switch respectively with multiple selector first
It is connected to the 5th output end.
In an embodiment of the present invention, the first order integrator includes resetting to open including the first to the 9th switch, first
Pass, the second reset switch, first capacitor, the second capacitor, the first sampling capacitance, the second sampling capacitance, first integral capacitor, second
Integrating capacitor, the first operational amplifier；One end of first switch is connected to VDD, the other end of first switch and the first sampling electricity
One end connection of one end of appearance, one end of second switch, the second compensating electric capacity, the other end of second switch are connected to GND, and first
One end of the other end of sampling capacitance and the first compensating electric capacity, one end of the 5th multidiameter option switch, third multidiameter option switch
One end connection, the other end of the 5th multidiameter option switch and one end of the 4th multidiameter option switch are connected to GND, third multichannel
One end connection of the other end of switch and one end of first capacitor, one end of third switch, the 4th switch is selected, third switch
The other end is connected with one end of the first multidiameter option switch is connected to common mode electrical level, the other end and the first reset switch of the 4th switch
One end, first integral capacitor one end connection, the inverting input terminal of the other end of first capacitor and the first operational amplifier, the
The other end of one end connection of five switches, the other end of the first reset switch and first integral capacitor, the 5th switch the other end,
First output end of the first operational amplifier connects, and the first output end as first order integrator, one end of the 6th switch
It is connected to GND, the other end of the 6th switch and the one end switched with one end of the second sampling capacitance, the 7th, the first compensating electric capacity
The other end connection, the 7th switch the other end be connected to VDD, the other end of the second sampling capacitance is another with the second compensating electric capacity
One end, the other end of the 4th multidiameter option switch, the second multidiameter option switch one end connection, the second multidiameter option switch it is another
One end is connect with one end of the first multidiameter option switch circuit other end, one end of the second capacitor, the 8th switch, the 8th switch
The other end is connect with one end of one end of the second reset switch, second integral capacitor, the other end of the second capacitor and the 9th switch
One end, the first operational amplifier non-inverting input terminal connection, the 9th switch the other end and the second reset switch the other end,
The second output terminal connection of the other end of second integral capacitor, the first operational amplifier, and second as first order integrator
Output end.
In an embodiment of the present invention, the feedback network include the first reference capacitance, the second reference capacitance, the 11st to
One end of 20th switch, the 11st switch connect with VDD, the 11st other end switched and the 12nd switch one end, the
One end of one reference capacitance connects, and the other end of the 12nd switch is connected to GND, and the other end of the first reference capacitance is through the 13rd
Switch is connected to common mode electrical level, the one end of the other end of the first reference capacitance also with one end of the 14th switch, the 15th switch
Connection, the other end of the 14th switch are connect with the other end of one end of the 19th switch, the second sampling capacitance, the 15th switch
The other end and one end of third multidiameter option switch, the 20th switch one end connect, one end of sixteenmo pass is connected to
GND, the other end that sixteenmo closes are connect with one end of one end of the 17th switch, the second reference capacitance, the 17th switch
The other end is connected to VDD, and the other end of the second reference capacitance is connected to common mode electrical level through eighteenmo connection, the second reference capacitance
The other end is also connect with the other end of the other end of the 19th switch, the 20th switch.
In an embodiment of the present invention, the second level integrator includes the 21st to the 30th switch, third reset
Switch, the 4th reset switch, third capacitor, the 4th capacitor, third sampling capacitance, the 4th sampling capacitance, third integral capacitor,
Four integrating capacitors, second operational amplifier；One end of 21st switch is connected to the first output end of first integrator, and second
The other ends and one end of third sampling capacitance of 11 switches, the 22nd switch one end connect, the 22nd switch it is another
One end is connected with one end of the 27th switch and is connected to common mode electrical level, and the other end of third sampling capacitance and the 23rd switchs
One end connection of one end, one end of the 24th switch, third capacitor, the other end and the second eighteenmo of the 23rd switch close
One end be connected to common mode electrical level, one end of the other end of the 24th switch and third reset switch, third integral capacitor
One end connection, one end connection of the inverting input terminal, the 25th switch of the other end and second operational amplifier of third capacitor,
The other end of third reset switch, the other end of third integral capacitor, the other end of the 25th switch, second operational amplifier
The connection of the first output end, and the first output end as second level integrator, one end and first order product that the second sixteenmo closes
Divide the second output terminal connection of device, the other end, the 4th sampling capacitance of the other end and the 27th switch that the second sixteenmo closes
One end connection, one end that the other end that the other end of the 4th sampling capacitance and the second eighteenmo close, the 29th switch, the 4th
One end of capacitor connects, and one end of the 29th other end switched and the 4th reset switch, one end of the 4th integrating capacitor connect
It connects, one end connection of the non-inverting input terminal, the 30th switch of the other end and second operational amplifier of the 4th capacitor, the 4th resets
The other end of the other end of switch and the 4th integrating capacitor, the other end of the 30th switch, second operational amplifier it is second defeated
Outlet connection, and the second output terminal as second level integrator.
In an embodiment of the present invention, the third level integrator includes the 31st to the 40th switch, the 5th reset
Switch, the 6th reset switch, the 5th capacitor, the 6th capacitor, the 5th sampling capacitance, the 6th sampling capacitance, the 5th integrating capacitor,
Six integrating capacitors, third operational amplifier；One end of 31st switch is connected to the first output end of second integral device, third
The other ends and one end of the 5th sampling capacitance of 11 switches, the 32nd switch one end connect, the 32nd switch it is another
One end is connected with one end of the 37th switch and is connected to common mode electrical level, and the other end of the 5th sampling capacitance and the 33rd switchs
One end connection of one end, one end of the 34th switch, the 5th capacitor, the other end and third eighteenmo of the 33rd switch close
One end be connected to common mode electrical level, one end of the other end of the 34th switch and the 5th reset switch, the 5th integrating capacitor
The other end of one end connection, the 5th capacitor is connect with one end of the inverting input terminal of third operational amplifier, the 35th switch,
The other end of 5th reset switch, the other end of the 5th integrating capacitor, the 35th other end, the third operational amplifier switched
The connection of the first output end, and the first output end as third level integrator, one end and second level product that third sixteenmo closes
Divide the second output terminal connection of device, the other end, the 6th sampling capacitance of the other end and the 37th switch that third sixteenmo closes
One end connection, one end of the other end, the 39th switch that the other end of the 6th sampling capacitance and third eighteenmo close, the 6th
One end of capacitor connects, and one end of the 39th other end switched and the 6th reset switch, one end of the 6th integrating capacitor connect
It connects, the other end of the 6th capacitor is connect with one end of the non-inverting input terminal of third operational amplifier, the 40th switch, and the 6th resets
The other end of the other end of switch and the 6th integrating capacitor, the other end of the 40th switch, third operational amplifier it is second defeated
Outlet connection, and the second output terminal as third level integrator.
In an embodiment of the present invention, the feedforward path includes the 7th to the 12nd capacitor, the 41st to the 40th
Six switches, the other end that one end of the 7th capacitor is switched with the 21st are connect, the other end of the 7th capacitor and the 9th capacitor
One end connection of one end, one end of the 12nd capacitor, the 41st switch, one end of the 8th capacitor are another with the 31st switch
One end connection, the other end of the 8th capacitor and one end of the tenth capacitor, one end of the 11st capacitor, the 42nd one end switched
Connection, the other end of the 9th capacitor with the 43rd switch one end, the 44th switch one end connect, the tenth capacitor it is another
One end is connect with one end that one end of the 45th switch, the 4th sixteenmo close, the other end and the 36th of the 11st capacitor
The other end of switch connects, and the other end of the 12nd capacitor is connect with the other end that the second sixteenmo closes, the 41st switch
The other end is connected with the other end of the 42nd switch is connected to common mode electrical level, and the other end of the 43rd switch and the third level integrate
First output end of device connects, and the other end of the 44th switch is connected with the other end that the 4th sixteenmo closes is connected to common mode electricity
Flat, the other end of the 45th switch is connect with the second output terminal of third level integrator, one end of the 41st switch, the 4th
One end of 12 switches is respectively as the first output end of the feedforward path, second output terminal.
In an embodiment of the present invention, third switch, the 13rd switch, eighteenmo close, the 24th switch, the
29 switch, the 33rd switch, third eighteenmo close control terminal and clock signal generator the first clock signal it is defeated
Outlet connection, the 4th switch, the 8th switch, the 23rd switch, the second eighteenmo pass, the 34th switch, the 39th are opened
The control terminal of pass and the second clock signal output end of clock signal generator connect, and first switch, the 5th switch, the 6th open
It closes, the 9th switch, the 11st switch, sixteenmo close, the 22nd switch, the 27th switch, the 31st switch, third
15 switch, third sixteenmo closes, the third clock signal output terminal of the control terminal of the 40th switch and clock signal generator
Connection, second switch, the 7th switch, the 12nd switch, the 17th switch, the 21st switch, the 25th switch, the 20th
Six switch, the 30th switchs, the 4th clock of the 32nd switch, the 37th control terminal switched and clock signal generator
Signal output end connection, the 14th switch control terminal, the 20th switch control terminal and clock signal generator the 5th when
The connection of clock signal output end, the 6th of the 15th control terminal, the control terminal of the 19th switch and the clock signal generator switched the
Clock signal output terminal connection；The relationship between clock signal that the clock signal generator generates are as follows: the first clock signal
With the non-overlapping clock of second clock signal reverse phase each other；Third clock signal is the rising edge synch of the first clock signal, under
Drop is along delay clock；4th clock signal is the rising edge synch of second clock signal, failing edge delay clock；5th clock letter
Number for the 4th clock signal and the Sigma-Delta modulator output signal and operation result, the 6th clock signal be the
The inversion signal of four clock signals and the Sigma-Delta modulator output signal and operation result.
The present invention also provides a kind of controls based on the reading circuit applied to capacitance type humidity sensor described above
Method processed first selects measurement pattern using multiple selector according to measurement demand, then passes through Sigma-Delta tune
The inductance capacitance of capacitance type humidity sensor is converted to charge signal by device processed, then is modulated to obtain digital code to charge signal
Stream finally handles digital code stream to obtain a digital quantity corresponding with inductance capacitance by decimation filter of digital.
Compared to the prior art, the invention has the following advantages: the present invention realizes two kinds of surveys by multiple selector
Amount mode obtains numeral output using Sigma-Delta modulation technique；Integrated circuit has high-precision and wide input range；This
Invention can apply the measurement in a variety of capacitance type humidity sensors, and can directly be connected with modern digital processing system
It connects.
Detailed description of the invention
Fig. 1 is capacitance type humidity sensor overall system diagram.
Fig. 2 is CDC system model.
Fig. 3 is Sigma-Delta modulator particular circuit configurations figure.
Fig. 4 is the timing diagram of Sigma-Delta modulator circuit.
Fig. 5 is multiple selector schematic diagram.
Fig. 6 is multiple selector particular circuit configurations figure.
Fig. 7 is switched-capacitor integrator working principle.
Fig. 8 is amplifier OTA1 circuit structure diagram.
Specific embodiment
With reference to the accompanying drawing, technical solution of the present invention is specifically described.
The present invention provides a kind of reading circuits applied to capacitance type humidity sensor, including multiple selector, capacitor
Digital quantizer, the capacitive digital converter include Sigma-Delta modulator and decimation filter of digital；The multichannel choosing
The output end of the input terminal and capacitance type humidity sensor of selecting device connects, and the output end of multiple selector is through Sigma-Delta tune
The input terminal of device and decimation filter of digital processed connects, number of the output end of decimation filter of digital as entire reading circuit
Signal output end.
The present invention also provides a kind of controls based on the reading circuit applied to capacitance type humidity sensor described above
Method processed first selects measurement pattern using multiple selector according to measurement demand, then passes through Sigma-Delta tune
The inductance capacitance of capacitance type humidity sensor is converted to charge signal by device processed, then is modulated to obtain digital code to charge signal
Stream finally handles digital code stream to obtain a digital quantity corresponding with inductance capacitance by decimation filter of digital.
The following are specific implementation processes of the invention.
The invention proposes a kind of capacitance type humidity sensor reading circuit with a variety of measurement patterns and numeral output,
The measurement that can carry out the perhaps single capacitor of differential electrical, using Sigma-Delta modulation technique, by capacitance type humidity sensor
Inductance capacitance signal is converted directly into digital signal output, can directly be attached with modern digital processor.Present invention design
Realize that supply voltage 1.8V, sample clock frequency 250kHz pass through Spectre using 0.18 μm of CMOS technology of SMIC
Emulation, under two kinds of measurement patterns, the input capacitance common mode range of integrated circuit is 0pF ~ 8pF, dynamic range be -0.26pF ~+
0.26pF, modulator precision reach 13bit.
Overall system structure as shown in Figure 1, reading circuit mainly by multiple selector, Sigma-Delta modulator sum number
Word decimation filter composition, wherein modulator and filter form capacitive digital converter CDC.First according to measurement demand benefit
Measurement pattern is selected with multiple selector, then passes through Sigma-Delta modulator for capacitance type humidity sensor
Inductance capacitance is converted to charge signal, then is modulated to obtain digital code stream to charge signal, finally passes through digital program-con-trolled exchange
Device handles digital code stream to obtain a digital quantity corresponding with inductance capacitance.
CDC system model is as shown in Fig. 2, Sigma-Delta modulator uses three rank CIFF(Cascade
Integrators with Feedforward) structure, decimation filter of digital sincKFilter, wherein K=4.In figure, CX
It is the inductance capacitance of sensor, C for input capacitanceoffFor compensating electric capacity, CrefFor reference capacitance, RESET is reset signal, bs
For modulator output code flow, DoutFor reality output digital quantity.CDC of the invention utilizes equivalent input capacitance (CX-Coff) and ginseng
Examine capacitor CrefBetween charge balance detect the variation of Unknown worm capacitor, operating mode is discrete mode, i.e., on circuit
Electricity resets integrator before each conversion, and a digital code will be generated by completing primary conversion, continuously converts several weeks
Phase carries out filtering to digital code stream finally by decimation filter of digital and obtains numeral output with down-sampled.
Sigma-Delta modulator particular circuit configurations as shown in figure 3, indicate, the identical first device of character in figure for convenience
Part i.e. indicate that those component parameters are identical, wherein OTA1, OTA2, OTA3 be operational amplifier, 2ndIt Int. is second level product
Point device, 3rdIt Int. is third level integrator.Integrator use switching capacity form, as shown in figure 3, integrator by switch S1,
S1d, S2, S2d and spaning waveguide operational amplifier OTA and sampling capacitance Cs, integrating capacitor CintComposition.When circuit is double-width grinding mode
When, SW1 and S1 connect identical timing, SW2 and SW3 conducting, and SW4 and SW5 are disconnected, and CDC uses fully differential structure, and this structure can
To reduce the sensibility to noise coupling, inductance capacitance CX1And CX2It is directly coupled to first order integrator, is integrated as the first order
The sampling capacitance of device, compensating electric capacity Coff1And Coff2Cross-coupling is in inductance capacitance, so that the effective input capacitance of the first order is
(CX - Coff).When circuit is single ended input mode, SW1, SW3, SW4 and SW5 conducting, SW2 are disconnected, inductance capacitance CX1
It is connected to the negative input end of first order integrator amplifier, the positive input terminal fixation of first order integrator amplifier is connected to common mode electrical level, mends
Repay capacitor Coff1Excitation and CX1Excitation reverse phase.
For circuit sequence as shown in figure 4, S1 and S2 is the non-overlapping clock of two reverse phases each other, S1d is that the rising edge of S1 is same
Step, failing edge delay clock；S2d is the rising edge synch of S2, failing edge delay clock.First order integrator is carried out in S1 phase
Sampling, is integrated in S2 phase.Second level integrator is sampled in S2 phase, and when S1 phase integrates.Third level integral
Device is sampled in S1 phase, and when S2 phase integrates.EVAL is comparator clock, and failing edge is effective.RESET is to reset letter
Number, after each completion conversion, all system is resetted.
As shown in figure 5, MODEL1 and MODEL2 is the input terminal of multiple selector, high level has multiple selector principle
Effect, SW1-SW5 are the output signal of multiple selector.By controlling the level of MODEL1 and MODEL2 come the input of selection circuit
Mode.Its physical circuit is as shown in fig. 6, it is made of number with door and/or door.MODEL1 is high level, and MODEL2 is low level
When, circuit is double-width grinding mode, and SW1 and S1 connect identical timing, SW2 and SW3 conducting, and SW4 and SW5 are disconnected；MODEL1 is low
Level, when MODEL2 is high level, circuit is single ended input mode, SW1, SW3, SW4 and SW5 conducting, SW2 disconnection.
Switched-capacitor integrator eliminates the input offset voltage of amplifier using auto zero technology, with OTA1's in Fig. 3
It is sampling phase, capacitor C when switch S1, S1d are closed from the point of view of negative input endX1It is charged to VDD；Switch S2, S2d are closed Shi Weiji
Split-phase, capacitor CX1On electric charge transfer to integrator CintOn.By taking single-ended structure as an example, Fig. 7 (a) and (b) describe switching capacity
The two states of integrator work.In S1 phase, as shown in Figure 7 (a), amplifier is switched to unit gain mode, the input of amplifier
Offset voltage (i.e. VX) store and arrive capacitor CCOn, input capacitance Cs is charged to VDD；In S2 phase, as shown in Figure 7 (b), capacitor
CCIt connects with amplifier, integrating capacitor CintIt is connected in feedback control loop.Due to negative-feedback, VXIt is generally kept at input offset voltage, institute
With node VGIt is maintained at virtual earth potential.Therefore, capacitor CsOn charge will be transferred completely into CintOn, amplifier input offset voltage
To the output voltage V of integratoroutSubstantially it does not have an impact.It can be worked normally to meet circuit under two kinds of input patterns,
Reach required required precision simultaneously, first order amplifier at least needs to reach 72dB.Therefore first order amplifier OTA1 uses Miller
The two-level configuration amplifier of compensating form, gain reach 120dB, and circuit structure is as shown in figure 8, input stage uses collapsible common source
Grid amplifier altogether, PM2 and PM3, NM4 and NM5 are input to pipe, use NMOS and PMOS parallel-connection structure, can obtain biggish
The amplitude of oscillation is inputted, PM25 and NM26, PM27 and NM28 are that output stage may be implemented using Class-AB push-pull type structure in static state
When efferent duct have lesser DC current, in dynamic provide required for high current, to improve the utilization of power supply power consumption
Rate.The average voltage of two output ends is detected using electric resistance partial pressure, the common mode electrical level V being then arranged with outsideCMIt is compared, produces
Raw feedback current, the electric current are injected into NM17 and NM18 by node A1 and A2, complete the feedback of common-mode signal.
The above are preferred embodiments of the present invention, all any changes made according to the technical solution of the present invention, and generated function is made
When with range without departing from technical solution of the present invention, all belong to the scope of protection of the present invention.
Claims (10)
1. a kind of reading circuit applied to capacitance type humidity sensor, which is characterized in that including multiple selector, capacitor number
Converter, the capacitive digital converter include Sigma-Delta modulator and decimation filter of digital；The multiple selector
Input terminal and capacitance type humidity sensor output end connect, the output end of multiple selector is through Sigma-Delta modulator
It is connect with the input terminal of decimation filter of digital, digital signal of the output end of decimation filter of digital as entire reading circuit
Output end.
2. the reading circuit according to claim 1 applied to capacitance type humidity sensor, which is characterized in that the multichannel
Selector includes first to the tenth and door, first to the 5th or door, first to the 5th with the first input end of door as entire more
The first input end of road selector, the 6th to the tenth the second input with the first input end of door as entire multiple selector
End, first is used as clock signal input terminal with the second input terminal of door, the first clock signal output with clock signal generator
End connection, second with the second input terminal of door, the second input terminal of third and door, the 6th with the second input terminal of door, the 8th with
Second input terminal of door, the 9th are used as digital power input terminal with the second input terminal of door, the 4th and door the second input terminal, the
Five with the second input terminal of door, the 7th with the second input terminal of door, the tenth with the second input terminal of door as digital ground terminal, first
Connect respectively with two input terminals of first or door with the output end of door, the 6th with the output end of door, second with the output end of door, the
Seven connect with two input terminals of second or door respectively with the output end of door, the output end of third and door, the 8th with the output end of door
Connect respectively with two input terminals of third or door, the 4th with the output end of door, the 9th with the output end of door respectively with the 4th or door
Two input terminals connection, the 5th connect with two input terminals of the 5th or door with the output end of door, the tenth with the output end of door respectively,
First to the 5th or door output end respectively as entire multiple selector the first to the 5th output end.
3. the reading circuit according to claim 2 applied to capacitance type humidity sensor, which is characterized in that described
Sigma-Delta modulator includes feedback network, the switching circuit by multiple selector control, first order integrator, the second level
Integrator, third level integrator, feedforward path, quantizer；The Sigma-Delta modulator further includes and first order integrator
The first compensating electric capacity, the second compensating electric capacity of connection；The switching circuit include the first to the 5th multidiameter option switch, first to
The control terminal of 5th multidiameter option switch is connect with the first to the 5th output end of multiple selector respectively.
4. the reading circuit according to claim 3 applied to capacitance type humidity sensor, which is characterized in that described first
Grade integrator includes including the first to the 9th switch, the first reset switch, the second reset switch, first capacitor, the second capacitor, the
One sampling capacitance, the second sampling capacitance, first integral capacitor, second integral capacitor, the first operational amplifier；The one of first switch
End is connected to VDD, the other end of first switch and one end of the first sampling capacitance, one end of second switch, the second compensating electric capacity
One end connection, the other end of second switch is connected to GND, the one of the other end of the first sampling capacitance and the first compensating electric capacity
One end connection at end, one end of the 5th multidiameter option switch, third multidiameter option switch, the other end of the 5th multidiameter option switch
GND is connected to one end of the 4th multidiameter option switch, one end of the other end of third multidiameter option switch and first capacitor,
One end connection of one end of three switches, the 4th switch, the other end of third switch are connected with one end of the first multidiameter option switch
It is connected to common mode electrical level, the other end of the 4th switch is connect with one end of one end of the first reset switch, first integral capacitor, and first
The other end of capacitor and the inverting input terminal of the first operational amplifier, the 5th switch one end connect, the first reset switch it is another
One end is connect with the first output end of the other end of first integral capacitor, the other end of the 5th switch, the first operational amplifier, and
As the first output end of first order integrator, one end of the 6th switch is connected to GND, the other end of the 6th switch with second
The other end connection of one end of sampling capacitance, one end of the 7th switch, the first compensating electric capacity, the other end of the 7th switch are connected to
The other end of VDD, the other end of the second sampling capacitance and the second compensating electric capacity, the other end of the 4th multidiameter option switch, second
One end connection of multidiameter option switch, the other end of the second multidiameter option switch and the first multidiameter option switch circuit other end,
One end connection of one end of the second capacitor, the 8th switch, the other end of the 8th switch and one end, the second product of the second reset switch
Divide one end connection of capacitor, the non-inverting input terminal of one end, the first operational amplifier that the other end of the second capacitor and the 9th switch
Connection, the other end and the other end of the second reset switch, the other end of second integral capacitor, the first operation amplifier of the 9th switch
The second output terminal of device connects, and the second output terminal as first order integrator.
5. the reading circuit according to claim 4 applied to capacitance type humidity sensor, which is characterized in that the feedback
Access includes the first reference capacitance, the second reference capacitance, the 11st to the 20th switch, and one end of the 11st switch and VDD connect
Connect, the 11st switch the other end with the 12nd switch one end, the first reference capacitance one end connect, the 12nd switch it is another
One end is connected to GND, and the other end of the first reference capacitance is connected to common mode electrical level through the 13rd switch, the first reference capacitance it is another
One end is also connect with one end of one end of the 14th switch, the 15th switch, the other end of the 14th switch and the 19th switch
One end, the second sampling capacitance other end connection, one end of the other end of the 15th switch and third multidiameter option switch, the
One end connection of 20 switches, one end that sixteenmo closes are connected to GND, what the other end and the 17th that sixteenmo closes switched
One end connection of one end, the second reference capacitance, the other end of the 17th switch are connected to VDD, the other end of the second reference capacitance
Be connected to common mode electrical level through eighteenmo connection, the other end of the second reference capacitance also with the other end of the 19th switch, the 20th
The other end of switch connects.
6. the reading circuit according to claim 5 applied to capacitance type humidity sensor, which is characterized in that described second
Grade integrator include the 21st to the 30th switch, third reset switch, the 4th reset switch, third capacitor, the 4th capacitor,
Third sampling capacitance, the 4th sampling capacitance, third integral capacitor, the 4th integrating capacitor, second operational amplifier；21st opens
One end of pass is connected to the first output end of first integrator, the other end of the 21st switch and the one of third sampling capacitance
One end connection at end, the 22nd switch, the other end of the 22nd switch is connected with one end of the 27th switch to be connected to altogether
Mould level, the other end of third sampling capacitance and one end of the 23rd switch, one end of the 24th switch, third capacitor
One end connection, one end that the other end and the second eighteenmo of the 23rd switch close are connected to common mode electrical level, the 24th switch
The other end connect with one end of one end of third reset switch, third integral capacitor, the other end of third capacitor and second fortune
Calculate the inverting input terminal of amplifier, one end connection of the 25th switch, the other end, the third integral capacitor of third reset switch
The other end, the 25th switch the other end, second operational amplifier the first output end connection, and as the second level integrate
First output end of device, one end that the second sixteenmo closes are connect with the second output terminal of first order integrator, and the second sixteenmo closes
The other end with the 27th switch the other end, the 4th sampling capacitance one end connect, the other end of the 4th sampling capacitance and
Second eighteenmo close the other end, the 29th switch one end, the 4th capacitor one end connection, the 29th switch it is another
End is connect with one end of one end of the 4th reset switch, the 4th integrating capacitor, the other end and the second operation amplifier of the 4th capacitor
One end connection of the non-inverting input terminal of device, the 30th switch, the other end of the 4th reset switch are another with the 4th integrating capacitor
The second output terminal connection at end, the other end of the 30th switch, second operational amplifier, and second as second level integrator
Output end.
7. the reading circuit according to claim 6 applied to capacitance type humidity sensor, which is characterized in that the third
Grade integrator include the 31st to the 40th switch, the 5th reset switch, the 6th reset switch, the 5th capacitor, the 6th capacitor,
5th sampling capacitance, the 6th sampling capacitance, the 5th integrating capacitor, the 6th integrating capacitor, third operational amplifier；31st opens
One end of pass is connected to the first output end of second integral device, and the one of the other end of the 31st switch and the 5th sampling capacitance
One end connection at end, the 32nd switch, the other end of the 32nd switch is connected with one end of the 37th switch to be connected to altogether
Mould level, the other end of the 5th sampling capacitance and one end of the 33rd switch, one end of the 34th switch, the 5th capacitor
One end connection, one end that the other end and third eighteenmo of the 33rd switch close are connected to common mode electrical level, the 34th switch
The other end connect with one end of one end of the 5th reset switch, the 5th integrating capacitor, the other end of the 5th capacitor and third are transported
Calculate the inverting input terminal of amplifier, one end connection of the 35th switch, the other end of the 5th reset switch, the 5th integrating capacitor
The other end, the 35th switch the other end, third operational amplifier the first output end connection, and as the third level integrate
First output end of device, one end that third sixteenmo closes are connect with the second output terminal of second level integrator, and third sixteenmo closes
The other end with the 37th switch the other end, the 6th sampling capacitance one end connect, the other end of the 6th sampling capacitance and
Third eighteenmo close the other end, the 39th switch one end, the 6th capacitor one end connection, the 39th switch it is another
End is connect with one end of one end of the 6th reset switch, the 6th integrating capacitor, the other end and third operation amplifier of the 6th capacitor
One end connection of the non-inverting input terminal of device, the 40th switch, the other end of the 6th reset switch are another with the 6th integrating capacitor
The second output terminal connection at end, the other end of the 40th switch, third operational amplifier, and second as third level integrator
Output end.
8. the reading circuit according to claim 7 applied to capacitance type humidity sensor, which is characterized in that the feedforward
Access includes the 7th to the 12nd capacitor, the 41st to the 4th sixteenmo pass, and one end of the 7th capacitor is switched with the 21st
Other end connection, what one end of the other end of the 7th capacitor and the 9th capacitor, one end of the 12nd capacitor, the 41st switched
One end connection, one end of the 8th capacitor are connect with the other end of the 31st switch, the other end and the tenth capacitor of the 8th capacitor
One end, the 11st capacitor one end, the 42nd switch one end connection, the other end of the 9th capacitor with the 43rd switch
One end, the 44th switch one end connection, the other end of the tenth capacitor with the 45th switch one end, the 4th sixteenmo
One end of pass connects, and the other end of the 11st capacitor is connect with the other end that third sixteenmo closes, the other end of the 12nd capacitor
The other end closed with the second sixteenmo is connect, and the other end of the 41st switch is connected with the other end of the 42nd switch to be connected to
Common mode electrical level, the 43rd switch the other end connect with the first output end of third level integrator, the 44th switch it is another
One end is connected with the other end that the 4th sixteenmo closes is connected to common mode electrical level, the other end and third level integrator of the 45th switch
Second output terminal connection, the 41st switch one end, the 42nd switch one end respectively as the feedforward path
First output end, second output terminal.
9. the reading circuit according to claim 8 applied to capacitance type humidity sensor, which is characterized in that the third
Switch, the 13rd switch, eighteenmo close, the 24th switchs, the 29th switch, the 33rd switch, third eighteenmo
The control terminal of pass and the first clock signal output terminal of clock signal generator connect, the 4th switch, the 8th switch, the 23rd
Switch, the second eighteenmo close, the 34th switchs, the second clock of the control terminal of the 39th switch and clock signal generator
Signal output end connects, first switch, the 5th switch, the 6th switch, the 9th switch, the 11st switch, sixteenmo pass, second
The control of 12 switches, the 27th switch, the 31st switch, the 35th switch, third sixteenmo pass, the 40th switch
End is connect with the third clock signal output terminal of clock signal generator, second switch, the 7th switch, the 12nd switch, the tenth
Seven switches, the 21st switch, the 25th switch, the second sixteenmo close, the 30th switchs, the 32nd switch, the 30th
The control terminals of seven switches and the 4th clock signal output terminal of clock signal generator connect, the control terminal of the 14th switch, the
The control terminal of 20 switches and the 5th clock signal output terminal of clock signal generator connect, the control terminal of the 15th switch,
The control terminal of 19th switch and the 6th clock signal output terminal of clock signal generator connect；The clock signal generator
Relationship between the clock signal of generation are as follows: the non-overlapping clock of the first clock signal and second clock signal reverse phase each other；The
Three clock signals are the rising edge synch of the first clock signal, failing edge delay clock；4th clock signal is second clock letter
Number rising edge synch, failing edge delay clock；5th clock signal is that the 4th clock signal and the Sigma-Delta are modulated
Device output signal and operation result, the 6th clock signal be that the 4th clock signal and the Sigma-Delta modulator export
The inversion signal of signal and operation result.
10. a kind of controlling party based on any reading circuit applied to capacitance type humidity sensor of claim 1-9
Method, which is characterized in that measurement pattern is selected using multiple selector according to measurement demand first, then passes through Sigma-
The inductance capacitance of capacitance type humidity sensor is converted to charge signal by Delta modulator, then is modulated to charge signal
To digital code stream, finally by decimation filter of digital to digital code stream handled to obtain one it is corresponding with inductance capacitance
Digital quantity.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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Application publication date: 20190820 |