CN113783574B - Modulation circuit - Google Patents
Modulation circuit Download PDFInfo
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- CN113783574B CN113783574B CN202111166457.6A CN202111166457A CN113783574B CN 113783574 B CN113783574 B CN 113783574B CN 202111166457 A CN202111166457 A CN 202111166457A CN 113783574 B CN113783574 B CN 113783574B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/368—Continuously compensating for, or preventing, undesired influence of physical parameters of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators
- H03M3/376—Prevention or reduction of switching transients, e.g. glitches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
Abstract
The present application relates to a modulation circuit. The modulation circuit includes a data selector, a multi-stage modulation circuit, a clock generation circuit, and a power supply circuit. The data selector includes a data selector output and a plurality of data selector inputs. The plurality of data selector inputs are for connection with external sense signals. The input end of the multi-stage modulation circuit is electrically connected with the output end of the data selector. The output end of the clock generation circuit is electrically connected with the clock signal input end of the multi-stage modulation circuit. The clock generation circuit is used for outputting clock signals which are not overlapped with each other to the multi-stage modulation circuit so that the output end of the multi-stage modulation circuit outputs a modulation signal. The power supply circuit is electrically connected with the power supply input end of the multistage modulation circuit. The modulation circuit provided by the embodiment is high in precision, fine fluctuation of signals in the intelligent power grid can be accurately detected, and monitoring requirements of the intelligent power grid can be well met.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a modulation circuit.
Background
The intelligent power grid, also called as the intellectualization of the power grid, is a power control system which utilizes data acquisition technologies such as sensors and the like to realize rapidness, safety, green economy and intelligence through high-speed two-way communication. With the popularization of the internet of things and smart grids, more and more large data volumes of electric power need to be analyzed and processed. Of these large data, analog data occupies a large component. In order to facilitate processing by the terminal, analog data typically needs to be converted to digital data by an analog-to-digital converter. Therefore, analog-to-digital converters become an integral part of the smart grid.
The analog-to-digital converter forms the current situation of various application scenes with advantages and disadvantages through long-time development and technical innovation. The types of analog-to-digital converters commonly used are Flash analog-to-digital converters, SAR analog-to-digital converters, integral analog-to-digital converters, sigma-Delta analog-to-digital converters, and the like. The analog-to-digital converter applied to the smart grid needs to detect the fluctuation in the power system, but the fluctuation in the power system is often not much different from the reference amount. Therefore, a high resolution Sigma-Delta analog-to-digital converter is necessary to accurately resolve the fine fluctuations in the circuit signal. However, the prior art Sigma-Delta analog-to-digital converter does not meet the resolution requirements.
Disclosure of Invention
Based on this, it is necessary to provide a modulation circuit for solving the problem that the existing Sigma-Delta analog-to-digital converter cannot meet the resolution requirement and cannot accurately distinguish the fine fluctuation in the circuit signal.
A modulation circuit includes a data selector, a multi-stage modulation circuit, a clock generation circuit, and a power supply circuit. The data selector includes a data selector output and a plurality of data selector inputs for connection with external sense signals. The input end of the multi-stage modulation circuit is electrically connected with the output end of the data selector. The output end of the clock generation circuit is electrically connected with the clock signal input end of the multi-stage modulation circuit. The clock generation circuit is used for outputting clock signals which are not overlapped with each other to the multi-stage modulation circuit so that the output end of the multi-stage modulation circuit outputs a modulation signal. The power supply circuit is electrically connected with the power supply input end of the multistage modulation circuit.
In one embodiment, the signal at the output of the data selector comprises a differential signal.
In one embodiment, the multi-stage modulation circuit includes a first stage modulation circuit, a second stage modulation circuit, and a third stage modulation circuit. The output end of the data selector is electrically connected with the input end of the first-stage modulation circuit. The feedback output end of the first-stage modulation circuit is electrically connected with the feedback input end of the first-stage modulation circuit. The first-stage modulation circuit is used for carrying out analog-to-digital conversion and noise shaping on the signal output by the data selector. The output end of the first-stage modulation circuit is electrically connected with the input end of the second-stage modulation circuit. And the feedback output end of the second-stage modulation circuit is electrically connected with the feedback input end of the second-stage modulation circuit. And the feedback output end of the first-stage modulation circuit is electrically connected with the feedback input end of the second-stage modulation circuit. The second-stage modulation circuit is used for shaping noise of the output signal of the first-stage modulation circuit. The output end of the second-stage modulation circuit is electrically connected with the input end of the third-stage modulation circuit. And the feedback output end of the third-stage modulation circuit is electrically connected with the feedback input end of the third-stage modulation circuit. And the feedback output end of the first-stage modulation circuit is electrically connected with the feedback input end of the third-stage modulation circuit. And the feedback output end of the second-stage modulation circuit is electrically connected with the feedback input end of the third-stage modulation circuit. The third-stage modulation circuit is used for shaping noise of the output signal of the first-stage modulation circuit and outputting the modulation signal.
In one embodiment, the first stage modulation circuit includes a first one-stage modulation circuit, a first two-stage modulation circuit, and a first comparator. The input end of the first-stage modulation circuit comprises the input end of the first-stage modulation circuit. The feedback output of the first stage modulation circuit comprises the output of the first comparator. The feedback input end of the first-stage modulation circuit comprises the feedback input end of the first-stage modulation circuit and the feedback input end of the first second-stage modulation circuit. The output end of the first-stage modulation circuit comprises the output end of the first second-stage modulation circuit. The output end of the data selector is electrically connected with the input end of the first-order modulation circuit. The output end of the first-order modulation circuit is electrically connected with the input end of the first second-order modulation circuit. The output end of the first second-order modulation circuit is electrically connected with the input end of the first comparator. The output end of the first comparator is electrically connected with the feedback input end of the first one-step modulation circuit. The output end of the first comparator is also electrically connected with the feedback input end of the first second-order modulation circuit.
In one embodiment, the second stage modulation circuit includes a second first stage modulation circuit and a second comparator. The input end of the second-stage modulation circuit comprises the input end of the second first-stage modulation circuit. The output end of the second-stage modulation circuit comprises the output end of the second first-stage modulation circuit. The feedback output of the second stage modulation circuit comprises the output of the second comparator. The feedback input of the second-stage modulation circuit comprises the feedback input of the second first-stage modulation circuit. The input end of the second first-order modulation circuit is electrically connected with the output end of the first second-order modulation circuit. The output end of the second first-order modulation circuit is electrically connected with the input end of the third-order modulation circuit. The output end of the second first-order modulation circuit is electrically connected with the input end of the second comparator. The output end of the second comparator is electrically connected with the feedback input end of the second first-order modulation circuit. The feedback input end of the second first-order modulation circuit is electrically connected with the output end of the first comparator. The feedback input end of the second first-order modulation circuit is electrically connected with the output end of the first second-order modulation circuit.
In one embodiment, the third stage modulation circuit includes a third first stage modulation circuit and a third comparator. The input of the third-stage modulation circuit comprises the input of the third first-stage modulation circuit. The feedback input end of the third-stage modulation circuit comprises the feedback input end of the third first-stage modulation circuit, and the feedback output end of the third-stage modulation circuit comprises the output end of the third comparator. The output end of the third first-order modulation circuit is electrically connected with the input end of the third comparator. The output end of the third comparator is electrically connected with the feedback input end of the third first-order modulation circuit. And the feedback input end of the third first-order modulation circuit is electrically connected with the output end of the second comparator. The feedback input end of the third first-order modulation circuit is electrically connected with the output end of the second first-order modulation circuit. And the output end of the third first-order modulation circuit outputs the modulation signal.
In one embodiment, the first order modulation circuit, the first second order modulation circuit, the second first order modulation circuit, and the third first order modulation circuit each comprise a switched capacitor integration circuit.
In one embodiment, the first comparator, the second comparator and the third comparator each comprise the same circuit structure. The circuit structure comprises a differential amplifying circuit, a voltage amplifying circuit and a positive feedback circuit. The two input ends of the differential amplifying circuit are respectively and correspondingly and electrically connected with the two output ends of the first second-order modulation circuit, the second first-order modulation circuit or the third first-order modulation circuit. And two output ends of the differential amplifying circuit are respectively and electrically connected with two input ends of the voltage amplifying circuit in a one-to-one correspondence manner. The two output ends of the differential amplifying circuit are also respectively and electrically connected with the two input ends of the positive feedback circuit in a one-to-one correspondence manner. The two output ends of the positive feedback circuit are respectively and correspondingly electrically connected with the two output ends of the voltage amplifying circuit, and the two output ends of the voltage amplifying circuit output feedback signals.
In one embodiment, the mutually non-overlapping clock signals include a first clock signal and a second clock signal. The non-overlapping clock signals further include a first sub-clock signal and a second sub-clock signal. The first sub-clock signal is in opposite phase to the first clock signal. The second sub-clock signal is in opposite phase to the second clock signal. The differential amplifying circuit is connected with the first clock signal or the second clock signal. The positive feedback circuit is connected with the first clock signal or the second clock signal.
In one embodiment, the clock generation circuit includes a first NOT gate, a first NAND gate, a second NOT gate, a third NOT gate, a first delay, a second delay, a fourth NOT gate, a third delay, a fifth NOT gate, a sixth NOT gate, a fourth delay, and a seventh NOT gate. The external circuit outputs a clock signal. The external clock signal is coupled to an input of the first NAND gate and to an input of the second NAND gate. The output of the first NAND gate is electrically connected to one input of the first NAND gate. The output end of the first NAND gate is electrically connected with the input end of the second NAND gate. The output end of the second NOT gate is electrically connected with the input end of the first delayer, the input end of the fourth NOT gate and the input end of the third delayer respectively. The output end of the first delayer is electrically connected with the input end of the fifth NOT gate. The output end of the fifth NOT gate is electrically connected with the other input end of the second NOT gate. The output end of the second NAND gate is electrically connected with the input end of the third NAND gate. The output end of the third NOT gate is electrically connected with the input end of the second delayer, the input end of the fourth delayer and the input end of the seventh NOT gate respectively, and the output end of the second delayer is electrically connected with the input end of the sixth NOT gate. The output end of the sixth NAND gate is electrically connected with the other input end of the first NAND gate. The fourth NOT outputs the first clock signal. The seventh NOT outputs the second clock signal. The third delay outputs the first sub-clock signal. The fourth delay outputs the second sub-clock signal.
In summary, a modulation circuit includes a data selector, a multi-stage modulation circuit, a clock generation circuit, and a power supply circuit. The data selector includes a data selector output and a plurality of data selector inputs coupled to an external sense signal. The input end of the multi-stage modulation circuit is electrically connected with the output end of the data selector. The output end of the clock generation circuit is electrically connected with the clock signal input end of the multi-stage modulation circuit. The clock generation circuit is used for outputting clock signals which are not overlapped with each other to the multi-stage modulation circuit so that the output end of the multi-stage modulation circuit outputs a modulation signal. The power supply circuit is electrically connected with the power supply input end of the multistage modulation circuit. The modulation circuit provided in this embodiment selectively accesses the differential signal through the data selector, and provides non-overlapping clock signals for the multi-stage modulation circuit through the clock generation circuit. The modulation circuit provided by the embodiment has better noise shaping capability through the multistage modulation circuit. The modulation circuit provided by the embodiment has higher gain and signal-to-noise ratio, better stability, greatly improves the precision of the whole modulator, can accurately detect the fine fluctuation of the signal in the smart grid, and can well meet the monitoring requirement of the smart grid.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic diagram of a modulation circuit according to an embodiment of the present application;
fig. 2 is a schematic diagram of a second structure of the modulation circuit according to an embodiment of the present application;
fig. 3 is a schematic diagram of a modulation circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a multi-stage modulation circuit according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a circuit schematic of a first comparator, a second comparator and a third comparator according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of a clock generating circuit according to an embodiment of the present application.
Reference numerals:
a modulation circuit 10; a data selector 100; a multi-stage modulation circuit 200; a first stage modulation circuit 210; a first-order modulation circuit 211; a first two-step modulation circuit 212; a first comparator 213; a second-stage modulation circuit 220; a second first-order modulation circuit 221; a second comparator 222; a third stage modulation circuit 230; a third first-order modulation circuit 231; a third comparator 232; a clock generation circuit 300; a power supply circuit 400.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below by way of examples with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated. In the description of the present application, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," etc. indicate or refer to an orientation or positional relationship based on that shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
In this application, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
Referring to fig. 1, the embodiment of the present application provides a modulation circuit 10 including a data selector 100, a multi-stage modulation circuit 200, a clock generation circuit 300, and a power supply circuit 400. The data selector 100 includes a data selector output and a plurality of data selector inputs for connection with external sense signals. An input of the multi-stage modulation circuit 200 is electrically connected to the data selector output. The output of the clock generation circuit 300 is electrically connected to the clock signal input of the multi-stage modulation circuit 200. The clock generation circuit 300 is configured to output clock signals to the multi-stage modulation circuit 200 that do not overlap each other, so that the output terminal of the multi-stage modulation circuit 200 outputs a modulation signal. The power supply circuit 400 is electrically connected to a power supply input terminal of the multi-stage modulation circuit 200.
The modulation circuit 10 facilitates access to multiple signals through the data selector 100. The clock generation circuit 300 provides non-overlapping clock signals to the multi-level modulation circuit 200. The modulation circuit 10 has better noise shaping capability, higher gain and signal to noise ratio through the multistage modulation circuit 200, better stability and high precision, can accurately detect the fine fluctuation of the signal in the smart grid, and can well meet the monitoring requirement of the smart grid.
In one embodiment, the signal at the output of the data selector 100 comprises a differential signal.
The differential signal is two signals with the same amplitude and opposite phases.
Referring also to fig. 2, in one embodiment, the multi-level modulation circuit 200 includes a first level modulation circuit 210, a second level modulation circuit 220, and a third level modulation circuit 230. An output of the data selector 100 is electrically connected to an input of the first stage modulation circuit 210. The feedback output of the first stage modulation circuit 210 is electrically connected to the feedback input of the first stage modulation circuit 210. The first stage modulation circuit 210 is configured to perform analog-to-digital conversion and noise shaping on the signal output from the data selector 100. An output of the first stage modulation circuit 210 is electrically connected to an input of the second stage modulation circuit 220. The feedback output of the second stage modulation circuit 220 is electrically connected to the feedback input of the second stage modulation circuit 220. The feedback output of the first stage modulation circuit 210 is electrically connected to the feedback input of the second stage modulation circuit 220. The second-stage modulation circuit 220 is configured to shape noise of the signal output from the first-stage modulation circuit 210. An output of the second stage modulation circuit 220 is electrically connected to an input of the third stage modulation circuit 230. The feedback output of the third stage modulation circuit 230 is electrically connected to the feedback input of the third stage modulation circuit 230. The feedback output of the first stage modulation circuit 210 is electrically connected to the feedback input of the third stage modulation circuit 230. The feedback output of the second stage modulation circuit 220 is electrically connected to the feedback input of the third stage modulation circuit 230. The third stage modulation circuit 230 is configured to shape noise of the signal output from the first stage modulation circuit 210 and output the modulated signal.
The first stage modulation circuit 210 includes the first stage modulation circuit 210 of the second order. The second stage modulation circuit 220 includes a first stage second stage modulation circuit 220. The third stage modulation circuit 230 of the first stage of the third stage modulation circuit 230. The multistage modulation circuit 200 can remarkably improve the noise shaping capability of the whole modulation circuit and improve the signal to noise ratio. The first-stage noise leakage of the modulation circuit is relatively large, the noise shaping can be performed on the modulation circuit through the second-stage first-stage modulation circuit 210, meanwhile, the stability of the whole modulation circuit can be ensured by adopting a modulation circuit which is not higher than the second-stage modulation circuit, and the stability of the whole modulation circuit can be further enhanced by the first-stage second-stage modulation circuit 220 and the first-stage third-stage modulation circuit 230.
Referring to fig. 3, in one embodiment, the first stage modulation circuit 210 includes a first-order modulation circuit 211, a first second-order modulation circuit 212, and a first comparator 213. The input of the first stage modulation circuit 210 includes the input of the first one-stage modulation circuit 211. The feedback output of the first stage modulation circuit 210 includes the output of the first comparator 213. The feedback input of the first stage modulation circuit 210 includes the feedback input of the first one-order modulation circuit 211 and the feedback input of the first two-order modulation circuit 212. The output of the first stage modulation circuit 210 includes the output of the first second stage modulation circuit 212. The output of the data selector 100 is electrically connected to the input of the first one-level modulation circuit 211. The output end of the first-order modulation circuit 211 is electrically connected to the input end of the first second-order modulation circuit 212. An output terminal of the first second-order modulation circuit 212 is electrically connected to an input terminal of the first comparator 213. An output terminal of the first comparator 213 is electrically connected to a feedback input terminal of the first one-step modulation circuit 211. The output of the first comparator 213 is also electrically connected to the feedback input of the first second-order modulation circuit 212.
The first-order modulation circuit 211 performs second-order modulation on the accessed differential signal, including sampling, weighting, integral filtering and quantization processing, to obtain a digital signal. And then, performing secondary modulation processing through the first-stage and second-stage modulation circuits 212 respectively to obtain primary modulation signals, and then outputting the primary modulation signals to the second-stage modulation circuit 220. Meanwhile, the primary modulation signal is output to the first comparator 213, and the output signal of the first comparator 213 is input to the feedback input end of the first-order modulation circuit 211 and the feedback input end of the first second-order modulation circuit 212, so that noise shaping is realized, and modulation precision is greatly improved.
In one embodiment, the second stage modulation circuit 220 includes a second first stage modulation circuit 221 and a second comparator 222. The input of the second stage modulation circuit 220 comprises the input of the second first stage modulation circuit 221. The output of the second-stage modulation circuit 220 includes the output of the second first-stage modulation circuit 221. The feedback output of the second stage modulation circuit 220 includes the output of the second comparator 222. The feedback input of the second stage modulation circuit 220 comprises the feedback input of the second first stage modulation circuit 221. An input terminal of the second first-order modulation circuit 221 is electrically connected to an output terminal of the first second-order modulation circuit 212. An output terminal of the second first-order modulation circuit 221 is electrically connected to an input terminal of the third-order modulation circuit 230. An output terminal of the second first-order modulation circuit 221 is electrically connected to an input terminal of the second comparator 222. An output terminal of the second comparator 222 is electrically connected to a feedback input terminal of the second first-order modulation circuit 221. The feedback input of the second first-order modulation circuit 221 is electrically connected to the output of the first comparator 213. The feedback input of the second first-order modulation circuit 221 is electrically connected to the output of the first second-order modulation circuit 212.
The primary modulation signal output from the first stage modulation circuit 210 is modulated again by the second first stage modulation circuit 221, so as to obtain an intermediate modulation signal. Then, the intermediate modulation signal is output to the third-stage modulation circuit 230. Meanwhile, the intermediate modulation signal is output to the second comparator 222, and the output signal of the first comparator 213 and the output signal of the second comparator 222 are output to the feedback input end of the second first-order modulation circuit 221, so that noise shaping is realized, and modulation precision is greatly improved.
In one embodiment, the third stage modulation circuit 230 includes a third first stage modulation circuit 231 and a third comparator 232. The input of the third stage modulation circuit 230 includes the input of the third first stage modulation circuit 231. The feedback input of the third stage modulation circuit 230 comprises the feedback input of the third first stage modulation circuit 231, and the feedback output of the third stage modulation circuit 230 comprises the output of the third comparator 232. An output terminal of the third first-order modulation circuit 231 is electrically connected to an input terminal of the third comparator 232. An output terminal of the third comparator 232 is electrically connected to a feedback input terminal of the third first-order modulation circuit 231. The feedback input of the third first-order modulation circuit 231 is electrically connected to the output of the second comparator 222. The feedback input terminal of the third first-order modulation circuit 231 is electrically connected to the output terminal of the second first-order modulation circuit 221. The output terminal of the third first-order modulation circuit 231 outputs the modulation signal.
The intermediate modulation signal output from the second first-order modulation circuit 221 is modulated again by the third first-order modulation circuit 231, and then the final modulation signal is output. Meanwhile, the final modulation signal is output to the third comparator 232, and the output signal of the second comparator 222 and the output signal of the third comparator 232 are output to the feedback input end of the third first-order modulation circuit 231, so that noise shaping is realized, and modulation precision is greatly improved.
In one embodiment, the first order modulation circuit 211, the first second order modulation circuit 212, the second first order modulation circuit 221, and the third first order modulation circuit 231 each comprise a switched capacitor integration circuit.
The switch capacitor integration circuit can overcome the influence of process deviation on indexes such as circuit working frequency, building time, integration precision, power consumption and the like, and greatly improves the stability and the robustness of the integrator under the condition of not obviously increasing the power consumption.
The switched capacitor integrating circuit realizes the coefficient of the modulating circuit by adjusting the ratio of the sampling capacitor to the integrating capacitor. For the operational amplifier in the switched capacitor integrating circuit, in order to obtain better swing amplitude, a folded cascode structure is selected instead of a sleeve structure in consideration of factors such as gain, bandwidth, swing amplitude and swing rate. In order to obtain high gain to meet the gain requirement, a gain-gating structure is employed. In order to improve the output slew rate, the current of each branch is properly improved, so that the current is balanced between the power consumption and the slew rate. The operational amplifier in the switched capacitor integrating circuit may employ a process of Hua Honghong force 110 nm.
Referring to fig. 4, the first-order modulation circuit 211 includes two switch capacitors respectively disposed at the non-inverting input terminal and the inverting input terminal of the operational amplifier U1 for inputting signals to the operational amplifier U1. The first-order modulation circuit 211 further includes two integrating capacitors, which are respectively connected between the non-inverting input terminal and the output terminal of the operational amplifier U1 and between the inverting input terminal and the output terminal, and are used for integrating signals.
Specifically, the two switch capacitors are a non-inverting input terminal switch capacitor and an inverting input terminal switch capacitor respectively. The inverting input terminal switch capacitor includes a MOS switch clk1, a capacitor C11, a MOS switch clk2e, a MOS switch clk1e, and a MOS switch clk2. One end of the capacitor C11 is electrically connected to the MOS switch clk 1. The other end of the capacitor C11 is electrically connected to the inverting input terminal of the operational amplifier U1 through the MOS switch clk2 e. One end of the capacitor C11 is further electrically connected to the feedback output end of the first comparator 213 through the MOS switch clk2. The other end of the capacitor C11 is also electrically connected to the common-mode input voltage Vcm through the MOS switch clk1 e. Similarly, the in-phase input end switch capacitor comprises a MOS switch clk1, a capacitor C12, a MOS switch clk2e, a MOS switch clk1e and a MOS switch clk2. One end of the capacitor C12 is electrically connected to the MOS switch clk 1. The other end of the capacitor C12 is electrically connected with the non-inverting input end of the operational amplifier U1 through the MOS switch clk2 e. One end of the capacitor C12 is further electrically connected to the feedback output end of the first comparator 213 through the MOS switch clk2. The other end of the capacitor C12 is also electrically connected to the common-mode input voltage Vcm through the MOS switch clk1 e.
Specifically, the two integrating capacitances include C2n and C2p, respectively. The integrating capacitor C2n is electrically connected between the inverting input terminal and the output terminal of the operational amplifier U1, and the integrating capacitor C2p is electrically connected between the non-inverting input terminal and the output terminal of the operational amplifier U1.
Here, the MOS switch clk1 and the MOS switch clk1e in the non-inverting input side switch capacitor or the inverting input side switch capacitor are controlled by the clock signal clk1 outputted from the clock generating circuit. The MOS switch clk2 and the MOS switch clk2e are controlled by a clock signal clk2 output from a clock generation circuit. Since the two clock signals clk1 and clk2 are clock signals that do not overlap each other. In the embodiment of the invention, the MOS tube clk1e advances to work in advance of the MOS tube clk1, and the MOS tube clk2e advances to work in advance of the MOS tube clk2, so that the over-sampling of an input signal is realized, and the signal to noise ratio is improved. In particular, in this embodiment, for convenience of understanding, MOS switches in the in-phase input side switch capacitor and the inverting input side switch capacitor are not strictly distinguished by a reference number, and only packet distinction is performed inside the in-phase input side switch capacitor and the inverting input side switch capacitor by the clock signal that is connected. Here, different MOS switches of the same reference number of the non-inverting input terminal switch capacitor and the inverting input terminal switch capacitor actually represent different physical devices.
In the embodiment of the invention, the operation of the switched capacitor integration circuit is divided into two parts: sampling and transfer amplification. Wherein sampling is controlled by the MOS switch clk1, and transfer amplification is controlled by the MOS switch clk 2. The capacitor C1 is a sampling capacitor. Compared with the MOS transistor switch clk, the edge of the MOS transistor switch clk1e arrives earlier, so that the influence of charge injection effect on linearity can be reduced. The sampling capacitor C and the integrating capacitors C2n and C2p form a capacitor feedback network, and a virtual short effect can be formed at the input end of the capacitor by means of the increase of the high small signal voltage of the dynamic amplifier, so that the signal charge collected by the sampling capacitor C during sampling can be transferred to the integrating capacitor, and the integrating function is completed.
Similarly, the first second-order modulation circuit 212, the second first-order modulation circuit 221 and the third first-order modulation circuit 231 operate in substantially the same manner as the first-order modulation circuit 211. The only difference is that the second first-order modulation circuit 221 and the third first-order modulation circuit 231 introduce the feedback signal from the comparator output of the preceding-stage modulation circuit, and the description thereof will not be repeated here.
Referring to fig. 5, in one embodiment, the first comparator 213, the second comparator 222 and the third comparator 232 all include the same circuit structure. The circuit structure comprises a differential amplifying circuit, a voltage amplifying circuit and a positive feedback circuit. The two input ends of the differential amplifying circuit are respectively and electrically connected with the two output ends of the first second-order modulation circuit 212, the second first-order modulation circuit 221 or the third first-order modulation circuit 231 in a one-to-one correspondence manner. And two output ends of the differential amplifying circuit are respectively and electrically connected with two input ends of the voltage amplifying circuit in a one-to-one correspondence manner. The two output ends of the differential amplifying circuit are also respectively and electrically connected with the two input ends of the positive feedback circuit in a one-to-one correspondence manner. The two output ends of the positive feedback circuit are respectively and correspondingly electrically connected with the two output ends of the voltage amplifying circuit, and the two output ends of the voltage amplifying circuit output feedback signals.
The differential amplifying circuit compares the magnitudes of the two differential signals and outputs a differential output signal. And outputting the differential output signal to the voltage amplifying circuit and the positive feedback circuit. The voltage amplifying circuit amplifies the differential output signals, and when the difference value of the differential output signals reaches or exceeds a threshold value, the positive feedback circuit generates positive feedback effect, so that the voltage amplifying circuit outputs two paths of signals, one path of the signals is equal to the power-on power level of the comparator, and the other path of signals is equal to the grounding level of the comparator. The output signal of the voltage amplifying circuit is used as a feedback input signal of the front-stage modulating circuit, so that the modulating precision is greatly improved.
Referring to fig. 5, in one embodiment, the mutually non-overlapping clock signals include a first clock signal and a second clock signal. The non-overlapping clock signals further include a first sub-clock signal and a second sub-clock signal. The first sub-clock signal is in opposite phase to the first clock signal. The second sub-clock signal is in opposite phase to the second clock signal. The differential amplifying circuit is connected with the first clock signal or the second clock signal. The positive feedback circuit is connected with the first clock signal or the second clock signal.
The differential amplifying circuit comprises an MOS tube M8, an MOS tube M9 and an MOS tube M10, the voltage amplifying circuit comprises an MOS tube M0, an MOS tube M1, an MOS tube M2 and an MOS tube M3, the positive feedback circuit comprises an MOS tube M4 and an MOS tube M5, the grid electrode of the MOS tube M8 and the grid electrode of the MOS tube M9 are respectively connected with signals output by two output ends of the first second-order modulating circuit, the second-order modulating circuit or the third first-order modulating circuit, the source electrode of the MOS tube M8 and the source electrode of the MOS tube M9 are respectively and electrically connected with the drain electrode of the MOS tube M10, the source electrode of the MOS tube M10 is grounded, the grid electrodes of the MOS tube M10 are connected with the first clock signal or the second clock signal, the drain electrodes of the MOS tube M8, the MOS tube M9 and the substrate of the MOS tube M10 are grounded, the drain electrode of the MOS tube M8 and the drain electrode of the MOS tube M9 are respectively connected with the drain electrode of the MOS tube M4 and the drain electrode of the MOS tube M5, the grid electrode of the MOS tube M4 is connected with the grid electrode of the MOS tube M5, the grid electrode of the MOS tube M4 is connected with the first clock signal or the second clock signal, the source electrode of the MOS tube M4 and the source electrode of the MOS tube M5 are electrically connected, the source electrode of the MOS tube M0 and the source electrode of the MOS tube M2 are respectively electrically connected, the drain electrode of the MOS tube M0 and the drain electrode of the MOS tube M2 are respectively and correspondingly electrically connected with the source electrode of the MOS tube M1 and the source electrode of the MOS tube M3, the grid electrode of the MOS tube M1 and the grid electrode of the MOS tube M3 are respectively and correspondingly electrically connected with the drain electrode of the MOS tube M8 and the drain electrode of the MOS tube M9, the drain electrode of the MOS tube M1 is respectively and correspondingly electrically connected with the drain electrode of the MOS tube M6 and the drain electrode of the MOS tube M7, the drain electrode of the MOS tube M3 is respectively and electrically connected with the drain electrode of the MOS tube M11 and the drain electrode of the MOS tube M12, and the drain electrode of the MOS tube M6 are respectively and electrically connected, the source of the MOS tube M7, the source of the MOS tube M11 and the source of the MOS tube M12 are respectively grounded, the grid of the MOS tube M6 and the grid of the MOS tube M0 are respectively electrically connected with the drain of the MOS tube M3, the grid of the MOS tube M11 and the grid of the MOS tube M2 are respectively electrically connected with the drain of the MOS tube M1, the grid of the MOS tube M7 and the grid of the MOS tube M12 are connected, and the grid of the MOS tube M7 is connected with the first sub-clock signal or the second sub-clock signal.
mos transistors are metal-oxide-semiconductor field effect transistors. The differential amplifying circuit is formed by the MOS tube M8, the MOS tube M9 and the MOS tube M10, and the two input differential signals are compared. The voltage amplifying circuit is formed by the MOS tube M0, the MOS tube M1, the MOS tube M2 and the MOS tube M3 to amplify the differential output signal output by the differential amplifying circuit. Meanwhile, the positive feedback circuit formed by the MOS tube M4 and the MOS tube M5 generates positive feedback when the difference value of the differential output signals reaches or exceeds a threshold value. And the voltage amplifying circuit outputs a comparison result according to the feedback signal output by the positive feedback circuit. The voltage amplification circuit outputs a signal as the feedback input signal of the preceding stage modulation circuit.
Referring to fig. 6, in one embodiment, the clock generating circuit 300 includes a first not gate, a first nand gate, a second not gate, a third not gate, a first delay, a second delay, a fourth not gate, a third delay, a fifth not gate, a sixth not gate, a fourth delay, and a seventh not gate. The external circuit outputs a clock signal. The external clock signal is coupled to an input of the first NAND gate and to an input of the second NAND gate. The output of the first NAND gate is electrically connected to one input of the first NAND gate. The output end of the first NAND gate is electrically connected with the input end of the second NAND gate. The output end of the second NOT gate is electrically connected with the input end of the first delayer, the input end of the fourth NOT gate and the input end of the third delayer respectively. The output end of the first delayer is electrically connected with the input end of the fifth NOT gate. The output end of the fifth NOT gate is electrically connected with the other input end of the second NOT gate. The output end of the second NAND gate is electrically connected with the input end of the third NAND gate. The output end of the third NOT gate is electrically connected with the input end of the second delayer, the input end of the fourth delayer and the input end of the seventh NOT gate respectively. The output end of the second delayer is electrically connected with the input end of the sixth NOT gate. The output end of the sixth NAND gate is electrically connected with the other input end of the first NAND gate. The fourth NOT outputs the first clock signal. The seventh NOT outputs the second clock signal. The third delay outputs the first sub-clock signal. The fourth delay outputs the second sub-clock signal.
Referring to fig. 6, the clock generating circuit 300 includes a first not gate N1, a first nand gate NA1, a second nand gate NA2, a second not gate N2, a third not gate N3, a first delay D1, a second delay D2, a fourth not gate N4, a third delay D3, a fifth not gate N5, a sixth not gate N6, a fourth delay D4, and a seventh not gate N7. An external circuit output clock signal clk_in is connected to the input end of the first nand gate N1 and one input end of the second nand gate NA2, and the output end of the first nand gate N1 is electrically connected to one input end of the first nand gate NA 1. The output end of the first nand gate NA1 is electrically connected to the input end of the second not gate N2. The output end of the second NOT gate N2 is electrically connected with the input end of the first delayer D1, the input end of the fourth NOT gate N4 and the input end of the third delayer D3 respectively. The output end of the first delayer D1 is electrically connected to the input end of the fifth not gate N5. The output end of the fifth NOT gate N5 is electrically connected with the other input end of the second NOT gate NA 2. The output end of the second nand gate NA2 is electrically connected to the input end of the third nor gate N3. The output end of the third NOT gate N3 is electrically connected with the input end of the second delayer D2, the input end of the fourth delayer D4 and the input end of the seventh NOT gate N7 respectively. The output end of the second delayer D2 is electrically connected to the input end of the sixth not gate N6. The output end of the sixth not gate N6 is electrically connected to the other input end of the first nand gate NA 1. The fourth not gate N4 outputs the first clock signal CLK1. The seventh not gate N7 outputs the second clock signal CLK2. The third delay D3 outputs the first sub-clock signal clk1_b. And the fourth delay D4 outputs the second sub-clock signal clk2_b.
And performing a series of inverse, NAND operation and delay processing on the input external clock signal through a logic device, and finally outputting the complementary overlapped clock signal to meet the requirement of an integrator in a front-order modulation circuit.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the patent. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A modulation circuit, comprising:
the data selector comprises a data selector output end and a plurality of data selector input ends, wherein the data selector input ends are used for being connected with external sensing signals;
The input end of the multistage modulation circuit is electrically connected with the output end of the data selector; the multi-stage modulation circuit comprises a first-stage modulation circuit, a second-stage modulation circuit and a third-stage modulation circuit; the first-stage modulation circuit comprises a first-order modulation circuit, a first second-order modulation circuit and a first comparator, the second-stage modulation circuit comprises a second first-order modulation circuit and a second comparator, and the third-stage modulation circuit comprises a third first-order modulation circuit and a third comparator;
the output end of the clock generation circuit is electrically connected with the clock signal input end of the multi-stage modulation circuit, and the clock generation circuit is used for outputting clock signals which are not overlapped with each other to the multi-stage modulation circuit so as to enable the output end of the multi-stage modulation circuit to output modulation signals;
the power supply circuit is electrically connected with the power supply input end of the multistage modulation circuit;
the first comparator, the second comparator and the third comparator all comprise the same circuit structure, the circuit structure comprises a differential amplifying circuit, a voltage amplifying circuit and a positive feedback circuit, two input ends of the differential amplifying circuit are respectively and correspondingly and electrically connected with two output ends of the first second-order modulating circuit, the second first-order modulating circuit or the third first-order modulating circuit, two output ends of the differential amplifying circuit are respectively and electrically connected with two input ends of the voltage amplifying circuit in a one-to-one correspondence manner, two output ends of the differential amplifying circuit are also respectively and electrically connected with two input ends of the positive feedback circuit in a one-to-one correspondence manner, two output ends of the positive feedback circuit are respectively and correspondingly and electrically connected with two output ends of the voltage amplifying circuit, and the two output ends of the voltage amplifying circuit output feedback signals.
2. The modulation circuit of claim 1 wherein the signal at the output of the data selector comprises a differential signal.
3. The modulation circuit of claim 2, wherein,
the output end of the data selector is electrically connected with the input end of the first-stage modulation circuit, the feedback output end of the first-stage modulation circuit is electrically connected with the feedback input end of the first-stage modulation circuit, and the first-stage modulation circuit is used for carrying out analog-to-digital conversion and noise shaping on the signal output by the data selector;
the output end of the first-stage modulation circuit is electrically connected with the input end of the second-stage modulation circuit, the feedback output end of the second-stage modulation circuit is electrically connected with the feedback input end of the second-stage modulation circuit, the feedback output end of the first-stage modulation circuit is electrically connected with the feedback input end of the second-stage modulation circuit, and the second-stage modulation circuit is used for shaping noise of the output signal of the first-stage modulation circuit;
the output end of the second-stage modulation circuit is electrically connected with the input end of the third-stage modulation circuit, the feedback output end of the third-stage modulation circuit is electrically connected with the feedback input end of the third-stage modulation circuit, the feedback output end of the first-stage modulation circuit is electrically connected with the feedback input end of the third-stage modulation circuit, the feedback output end of the second-stage modulation circuit is electrically connected with the feedback input end of the third-stage modulation circuit, and the third-stage modulation circuit is used for shaping noise of the output signal of the first-stage modulation circuit and outputting the modulation signal.
4. The modulation circuit of claim 3, wherein the input of the first stage modulation circuit comprises an input of the first one-stage modulation circuit, the feedback output of the first stage modulation circuit comprises an output of the first comparator, the feedback input of the first stage modulation circuit comprises a feedback input of the first one-stage modulation circuit and a feedback input of the first two-stage modulation circuit, the output of the first stage modulation circuit comprises an output of the first two-stage modulation circuit, the output of the data selector is electrically connected to the input of the first one-stage modulation circuit, the output of the first one-stage modulation circuit is electrically connected to the input of the first two-stage modulation circuit, the output of the first two-stage modulation circuit is electrically connected to the input of the first comparator, the output of the first comparator is electrically connected to the feedback input of the first one-stage modulation circuit, and the output of the first comparator is also electrically connected to the feedback input of the first two-stage modulation circuit.
5. The modulation circuit of claim 4, wherein the input of the second stage modulation circuit comprises an input of the second first stage modulation circuit, the output of the second stage modulation circuit comprises an output of the second first stage modulation circuit, the feedback output of the second stage modulation circuit comprises an output of the second comparator, the feedback input of the second stage modulation circuit comprises a feedback input of the second first stage modulation circuit, the input of the second first stage modulation circuit is electrically connected to the output of the first second stage modulation circuit, the output of the second first stage modulation circuit is electrically connected to the input of the third stage modulation circuit, the output of the second first stage modulation circuit is electrically connected to the input of the second comparator, the output of the second comparator is electrically connected to the feedback input of the second first stage modulation circuit, and the feedback input of the second first stage modulation circuit is electrically connected to the output of the first stage modulation circuit.
6. The modulation circuit of claim 5, wherein the input of the third stage modulation circuit comprises an input of the third first stage modulation circuit, the feedback input of the third stage modulation circuit comprises a feedback input of the third first stage modulation circuit, the feedback output of the third stage modulation circuit comprises an output of the third comparator, the output of the third first stage modulation circuit is electrically connected to the input of the third comparator, the output of the third comparator is electrically connected to the feedback input of the third first stage modulation circuit, the feedback input of the third first stage modulation circuit is electrically connected to the output of the second comparator, the feedback input of the third first stage modulation circuit is electrically connected to the output of the second first stage modulation circuit, and the output of the third first stage modulation circuit outputs the modulation signal.
7. The modulation circuit of claim 6, wherein the first-order modulation circuit, the first second-order modulation circuit, the second first-order modulation circuit, and the third first-order modulation circuit each comprise a switched-capacitor integration circuit.
8. The modulation circuit according to claim 7, wherein the mutually non-overlapping clock signals include a first clock signal and a second clock signal, the mutually non-overlapping clock signals further include a first sub-clock signal and a second sub-clock signal, the first sub-clock signal is opposite in phase to the first clock signal, the second sub-clock signal is opposite in phase to the second clock signal, the differential amplification circuit is connected to the first clock signal or the second clock signal, and the positive feedback circuit is connected to the first clock signal or the second clock signal.
9. The modulation circuit of claim 8, wherein the clock generation circuit comprises a first NOT gate, a second NOT gate, a third NOT gate, a first delay, a second delay, a fourth NOT gate, a third delay, a fifth NOT gate, a sixth NOT gate, a fourth delay and a seventh NOT gate, an external circuit outputs a clock signal, the clock signal output by the external circuit is connected to the input end of the first NOT gate and one input end of the second NOT gate, the output end of the first NOT gate is electrically connected with one input end of the first NOT gate, the output end of the first NOT gate is electrically connected with the input end of the second NOT gate, the output end of the second NOT gate is respectively electrically connected with the input end of the first delay, the input end of the fourth NOT gate and the input end of the third delay, the output end of the first delay device is electrically connected with the input end of the fifth NOT gate, the output end of the fifth NOT gate is electrically connected with the other input end of the second NOT gate, the output end of the second NOT gate is electrically connected with the input end of the third NOT gate, the output end of the third NOT gate is respectively electrically connected with the input end of the second delay device, the input end of the fourth delay device and the input end of the seventh NOT gate, the output end of the second delay device is electrically connected with the input end of the sixth NOT gate, the output end of the sixth NOT gate is electrically connected with the other input end of the first NOT gate, the fourth NOT gate outputs the first clock signal, the seventh NOT gate outputs the second clock signal, the third delay device outputs the first sub clock signal, the fourth delay outputs the second sub-clock signal.
10. The modulation circuit of claim 2, wherein the differential signal is two signals of equal amplitude and opposite phase.
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