CN112255464B - Capacitance measuring circuit and measuring method based on charge compensation analog front end - Google Patents
Capacitance measuring circuit and measuring method based on charge compensation analog front end Download PDFInfo
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Abstract
The application provides a capacitance measuring circuit and a measuring method based on a charge compensation analog front end, which automatically set a compensation capacitance value according to an actual parasitic capacitance value, can ensure the effectiveness of capacitance compensation, ensure the normal work of the capacitance measuring circuit and improve the precision of capacitance measurement, and comprises a charge compensation analog front end module, an analog/digital converter, a digital control module, an extraction filter module and a reference voltage module; the input of charge compensation analog front end module links to each other with the capacitor under test, charge compensation analog front end module output with analog/digital converter input links to each other its characterized in that: the input end of the charge compensation analog front end module is provided with a compensation charge array module, the compensation charge array module is provided with a compensation capacitance value according to a parasitic capacitance value, and the charge compensation analog front end module obtains a compensation capacitance array code and residual voltage and outputs the residual voltage to the analog/digital converter.
Description
Technical Field
The invention relates to the technical field of capacitance measurement, in particular to a capacitance measurement circuit and a measurement method based on a charge compensation analog front end.
Background
Touch screen capacitors of many smart devices are self-capacitance type, that is, one end of a capacitor to be measured is grounded. The capacitance values of these capacitors need to be measured. These self capacitances are typically measured in the prior art using capacitive-to-digital converters. An important component of the capacitance measurement circuit of a capacitance-to-digital converter is the charge-compensated analog front-end.
In the prior art, a charge compensation analog front end of a capacitance measuring circuit mostly adopts a charge amplifying circuit, and the basic charge amplifying circuit has the following problems: it cannot work normally when the parasitic capacitance is above 100 pF. Since large parasitic capacitances generate large amounts of charge that enters the charge amplifying structure, which results in a large voltage step. This voltage step will waste voltage margin and if this voltage value is reduced by increasing the feedback capacitance, the accuracy of the capacitance measurement will be lost and the measurement will not be as accurate.
In the prior art, a charge compensation structure is adopted to solve the above problems, but since the compensation capacitance in the charge compensation structure is a fixed value, the following two problems are caused: 1. the size of the compensation capacitor can be determined only by knowing the size of the parasitic capacitor in advance; 2. if the parasitic capacitance is a capacitance that changes with temperature and humidity, the compensation may fail and may eventually cause the capacitance measuring circuit to fail to function properly.
Disclosure of Invention
The capacitance measurement circuit based on the charge compensation analog front end can solve the problems that compensation capacitance values of a charge compensation structure in the existing capacitance measurement circuit are fixed values and can be determined only by predetermining parasitic capacitance values, so that the compensation capacitance values are difficult to take, the parasitic capacitance changes once possibly to cause compensation failure, and the capacitance measurement circuit can not work normally.
The technical scheme is as follows: a capacitance measuring circuit based on a charge compensation analog front end comprises a charge compensation analog front end module AFE, an analog/digital converter ADC, a digital control module, a decimation filter module and a reference voltage module; the input end of the charge compensation analog front end module AFE is connected with the tested capacitor Cx, the output end of the charge compensation analog front end module AFE is connected with the input end of an analog/digital converter (ADC), and the output end of the ADC is connected with the input end of a decimation filter module;
the method is characterized in that: the input end of the charge compensation analog front end module AFE is provided with a compensation charge array module, the compensation charge array module sets a compensation capacitance value according to a parasitic capacitance value and generates a compensation capacitance array code, and the charge compensation analog front end module AFE measures residual voltage and outputs the residual voltage to the analog/digital converter ADC; the analog/digital converter performs oversampling on the residual voltage and analog-to-digital conversion to generate an oversampled digital code stream, and then outputs the generated oversampled digital code stream to the extraction filter module; the decimation filter module is used for carrying out frequency reduction and low-pass filtering on the digital code to obtain a final analog/digital converter output digital code; the final capacitance measurement output value is the addition of the compensated capacitor array code and the analog/digital converter output digital code.
Further, the charge compensation analog front end module AFE includes a first operational amplifier CA, a comparator COMP, a compensation charge array module, and a single-to-double output module;
the inverting input end of the first operational amplifier CA is connected with the measured capacitor Cx, the parasitic capacitor and the compensation charge array module, and the non-inverting input end of the first operational amplifier CA is connected with the excitation signal VEX; the output end of the first operational amplifier CA is connected with the non-inverting input end of the comparator COMP and the input end of the single-end-to-double-end output module, a feedback capacitor Cfb and a reset switch RST _ CA are connected between the output end and the inverting input end of the first operational amplifier CA, and the feedback capacitor Cfb and the reset switch RST _ CA are connected in parallel;
and the inverting input end of the comparator COMP is connected with the common-mode voltage VCM, and the VOUTN end and the VOUTP end of the comparator are connected with the compensation charge array module.
The compensation charge array module comprises a compensation capacitor, a capacitance SWITCH and a logic control unit DYNAMIC;
the compensation capacitors adopt 9 capacitors, the upper pole plate of each compensation capacitor is connected to the inverting input end of the first operational amplifier CA, a capacitor SWITCH is connected between the lower pole plate of each compensation capacitor and the excitation signal NVCR, and each SWITCH is connected with a logic control unit DYNAMIC;
the lower pole plate of each compensation capacitor is connected with the OUT end of a capacitor SWITCH, the D end of the capacitor SWITCH is connected with the D end of the corresponding logic control unit DYNAMIC, the N end of the capacitor SWITCH is connected with the N end of the corresponding logic control unit DYNAMIC, and the IN end of the capacitor SWITCH is connected with an excitation signal NVCR;
the D end of the logic control unit DYNAMIC corresponding to the first compensation capacitor C8 is connected with a reset signal RST _ COMPENSATE, the D ends of the logic control units DYNAMIC corresponding to the other compensation capacitors are respectively connected with the Q end of the logic control unit DYNAMIC corresponding to the last compensation capacitor, and the CMPP end and the CMPN end of each logic control unit DYNAMIC are respectively connected with the VOUTN end and the VOUTP end of the comparator COMP after phase inversion by an inverter; the VALID end of each logic control unit DYNAMIC is connected with the VOUTN end and VOUTP end of the comparator COMP through nor gates.
The capacitance values of the 9 compensation capacitors are binary weight distribution, and C8-2C 7-4C 6-8C 5-16C 4-32C 3-64C 2-128C 1-256C 0.
The single-end-to-double-end output module comprises a second operational amplifier and a third operational amplifier; the non-inverting input ends of the second operational amplifier and the third operational amplifier are connected with the common-mode voltage VCM, the inverting input ends of the second operational amplifier and the third operational amplifier are connected with the output end of the first operational amplifier CA through a sampling capacitor Cs1, and a single-turn double-switch PUSAI2 and a single-turn double-switch PUSAI1 are respectively connected between the inverting input ends and a sampling capacitor Cs 1; a reset switch RST _ P and a sampling capacitor Cs2 are connected between the inverting input end of the second operational amplifier and the output end VP of the second operational amplifier, and the reset switch RST _ P and the sampling capacitor Cs2 are connected in parallel; a reset switch RST _ N and a sampling capacitor Cs3 are connected between the inverting input end of the third operational amplifier and the output end VN of the third operational amplifier, and the reset switch RST _ N and the sampling capacitor Cs3 are connected in parallel; the comparator COMP of the charge compensation analog front end module AFE employs a pre-amplification and latching structure.
The first operational amplifier CA in the charge compensation analog front end module AFE adopts a PMOS differential pair input, single-ended output and gain enhancement operational amplifier structure, and is composed of a main operational amplifier and two auxiliary operational amplifiers, wherein the two auxiliary operational amplifiers are both source-level input.
The second and third operational amplifiers of the single-end-to-double-end output module in the charge compensation analog front-end module AFE both adopt a p-input and two-stage amplification structure, the first stage adopts a low-voltage self-bias cascode structure, the second stage adopts a push-pull structure, and a Miller compensation capacitor is added between the two stages.
A capacitance measuring method adopting the circuit comprises the following steps:
step 1, a charge compensation analog front end module AFE measures a measured capacitor Cx to obtain a compensation capacitor array code and a residual voltage, and outputs the residual voltage to an analog/digital converter ADC;
step 2, the analog/digital converter ADC is used for oversampling the residual voltage and performing analog-to-digital conversion to obtain an oversampled digital code stream, and outputting the generated oversampled digital code stream to the extraction filter module;
step 3, the extraction filter module reduces the frequency of the digital code and performs low-pass filtering to obtain the final output digital code of the analog/digital converter; the final output value of the capacitance measurement is the addition of the compensation capacitor array code and the digital code output by the analog/digital converter;
the method is characterized in that: the step 1 also comprises the following steps:
step 1-1, in a first period of setting the compensation capacitor, firstly closing a capacitance switch of a first compensation capacitor C8 of the compensation charge array, and disconnecting capacitance switches of the other compensation capacitors in the array;
step 1-2, excitation signals VEX and NVCR are respectively at low levels VL and VGND, a reset switch RST _ CA is closed, a feedback capacitor Cfb is reset, a measured capacitor Cx and a parasitic capacitor Cpara are charged, after stabilization, the voltage across the feedback capacitor Cfb is VL, and VL is a fixed constant voltage value (for example, 1.3125V) smaller than VCM;
step 1-3, the reset switch RST _ CA is turned off, the excitation signals VEX and NVCR rise together, the voltage changes are Δ VEX-VCM-VL and Δ NVCR-VDD-VGND, respectively, the measured capacitance Cx and the parasitic capacitance Cpara will increase the charge amount to (Cx + Cpara) × Δ VEX, wherein the compensation charge array will provide the charge amount of C8 × (Δ NVCR- Δ VEX); the feedback capacitor Cfb needs to provide a charge amount of (Cx + Cpara) x Δ VEX-C8 × (Δ NVCR- Δ VEX); the output of the first operational amplifier CA is therefore VCM + Δ Vout, where
Steps 1-4. if the output of the first operational amplifier (VCM + Δ Vout) > VCM, representing an under-compensation, then the switch of C8 is kept closed; if (VCM + Δ Vout) < VCM, indicating overcompensation, the switch of C8 is opened;
step 1-5, sequentially accessing C7-C0 in the compensation charge array, sequentially closing a capacitance switch of the compensation charge array, and sequentially executing steps 1-2-1-4 to finish the second to nine periods;
step 1-6, after 9 cycles, a compensation capacitor array code of 9 bits will be generated, and finally the output voltage VCA of the first operational amplifier CA after the capacitance compensation is VCM + Δ Vout, where
CCAP_ARRAYThe compensation capacitance value of the charge array is compensated after 9 cycles.
The step 1 further comprises:
step 1-7, the reset switches RST _ CA and RST _ N and the single-turn double-switch PUSAI1 are closed, the excitation signals VEX and NVCR are set to VL and GND respectively, and at the moment, VCA is VL and VN is VCM;
step 1-8, disconnecting the reset switches RST _ CA and RST _ N, respectively raising the excitation signals VEX and NVCR to VCM and VDD, wherein the voltage of VCA is changed into delta VEX + delta Vout, and the output end VN of the single-end to double-end output module outputs voltage VCM- (delta VEX + delta Vout);
step 1-9. now, PUSAI1 is turned off, and this voltage will be stored across capacitor Cs;
step 1-10, closing the PUSAI2 and RST _ P, and keeping VP equal to VCM;
step 1-11, the RST _ P is turned off, the RST _ CA is turned on, the VEX is decreased to VL, the voltage of the VCA is changed to- (Δ VEX + Δ Vout), the output terminal VP of the single-to-double output module outputs the voltage VCM + (Δ VEX + Δ Vout), so that the single-to-double output module outputs the double-ended voltage centered around the VCM voltage, and the voltage difference VP-VN is equal to 2(Δ VEX + Δ Vout), which is the remaining voltage.
The invention provides a capacitance measuring circuit and a capacitance measuring method based on a charge compensation analog front end, which have the following beneficial effects: the compensation capacitance value is automatically set according to the actual parasitic capacitance value by setting the charge compensation array, the fixed compensation capacitance value is not required to be set by determining the parasitic capacitance value in advance, the problems that the compensation fails and the measurement circuit cannot work due to the fact that the parasitic capacitance changes along with the changes of temperature and humidity are avoided, the effectiveness of capacitance compensation and the normal work of the capacitance measurement circuit can be guaranteed, and the precision of capacitance measurement is improved.
Drawings
FIG. 1 is an overall schematic diagram of a capacitance measurement circuit;
FIG. 2 is a circuit diagram of a charge compensated analog front end module;
FIG. 3 is a schematic diagram of a charge compensation array circuit;
FIG. 4 is a circuit diagram of the comparator COMP;
FIG. 5 is a circuit diagram of a first operational amplifier;
FIG. 6 is a circuit diagram of a second/third operational amplifier;
FIG. 7 is a circuit diagram of a capacitor SWITCH;
fig. 8 is a circuit diagram of a logic control unit.
Detailed Description
As shown in fig. 1, a capacitance measuring circuit based on a charge compensation analog front end includes a charge compensation analog front end module AFE, an analog/digital converter ADC, a digital control module, a decimation filter module, and a reference voltage module.
The reference voltage module is respectively connected with the charge compensation analog front end module AFE, the analog/digital converter ADC, the digital control module and the decimation filter module and is used for providing reference voltage required by the modules.
The digital control module is connected with the charge compensation analog front end module, the analog/digital converter and the decimation filter module and is used for providing logic operation and time sequence control.
The input end of the charge compensation analog front end module AFE is connected with the measured capacitor Cx, and the output end of the charge compensation analog front end module AFE is connected with the sampling input end of the analog/digital converter ADC.
The input end of the charge compensation analog front end module AFE is provided with a compensation charge array module, the compensation charge array module is provided with a compensation capacitance value according to a parasitic capacitance value, and the charge compensation analog front end module AFE is used for converting the value of the measured capacitance Cx into an addition form of a compensation capacitance array code and a residual voltage and outputting the residual voltage to the analog/digital converter ADC.
The output end of the analog/digital converter ADC is connected with the input end of the extraction filter module, the analog/digital converter ADC is used for oversampling the residual voltage and performing analog-to-digital conversion to generate an oversampled digital code stream, and then the generated oversampled digital code stream is output to the extraction filter module.
The decimation filter module is used for carrying out frequency reduction and low-pass filtering on the digital code to obtain a final analog/digital converter output digital code; the final output value of the measured capacitance Cx is the addition of the compensation capacitance array code and the analog/digital converter output digital code.
As shown in fig. 2, the charge compensation analog front end module AFE includes: the circuit comprises a first operational amplifier CA, a comparator COMP, a compensation charge array module and a single-end to double-end output module. Cx and Cpara are respectively a tested capacitor and a parasitic capacitor, Cfb is a feedback capacitor, Cs1, Cs2 and Cs3 are sampling capacitors, RST _ CA and RST _ P, RST _ N are reset switches, and PUSAI2 and PUSAI1 are single-switch double-switch switches; VCM is half the common mode voltage, i.e., VDD; VEX and NVCR are excitation signals; NVCR has a range of variation from GND to VDD, VEX has a range of variation from VL to VCM, where VL < VCM, followed by Δ NVCR-VDD, Δ VEX-VCM-VL for convenience, where Δ NVCR is much larger than Δ VEX, and VL is a fixed constant voltage value less than VCM, such as 1.3125V.
The inverting input end of the first operational amplifier CA is connected with the measured capacitor Cx, the parasitic capacitor and the compensation charge array module, and the non-inverting input end of the first operational amplifier CA is connected with the excitation signal VEX.
The output end of the first operational amplifier is connected with the non-inverting input end of a comparator COMP and the input end of a single-end-to-double-end output module, a feedback capacitor Cfb and a reset switch RST _ CA are connected between the output end and the inverting input end, and the feedback capacitor Cfb and the reset switch RST _ CA are connected in parallel; and the inverting input end of the comparator COMP is connected with the common-mode voltage VCM, and the VOUTN end and the VOUTP end of the comparator are connected with the compensation charge array module.
As shown in fig. 3, the compensation charge array module includes a compensation capacitor, a capacitor SWITCH, and a logic control unit DYNAMIC.
The compensation capacitors adopt a mode of connecting 9 capacitors in parallel, the upper electrode plate of each compensation capacitor is connected to the inverting input end of the first operational amplifier CA, a capacitor SWITCH is connected between the lower electrode plate of each compensation capacitor and the excitation signal NVCR, and each SWITCH is connected with a logic control unit DYNAMIC.
The lower pole plate of each compensation capacitor is connected with the OUT end of a capacitor SWITCH, the D end of the capacitor SWITCH is connected with the D end of the corresponding logic control unit DYNAMIC, the N end of the capacitor SWITCH is connected with the N end of the corresponding logic control unit DYNAMIC, and the IN end of the capacitor SWITCH is connected with the excitation signal NVCR.
The D end of the logic control unit DYNAMIC corresponding to the first compensation capacitor C8 is connected with a reset signal RST _ COMPENSATE, the D ends of the logic control units DYNAMIC corresponding to the other compensation capacitors are respectively connected with the Q end of the logic control unit DYNAMIC corresponding to the last compensation capacitor, and the CMPP end and the CMPN end of each logic control unit DYNAMIC are respectively connected with the VOUTN end and the VOUTP end of the comparator COMP after phase inversion by an inverter; the VALID end of each logic control unit DYNAMIC is connected with the VOUTN end and the VOUTP end of a comparator COMP through a NOR gate; the capacitance values of the 9 compensation capacitors are binary weight distribution, that is, C8-2C 7-4C 6-8C 5-16C 4-32C 3-64C 2-128C 1-256C 0.
The single-end-to-double-end output module comprises a second operational amplifier and a third operational amplifier; the non-inverting input ends of the second operational amplifier and the third operational amplifier are connected with the common-mode voltage VCM, the inverting input ends of the second operational amplifier and the third operational amplifier are connected with the output end of the first operational amplifier CA through a sampling capacitor Cs1, and a single-turn double-switch PUSAI2 and a single-turn double-switch PUSAI1 are respectively connected between the inverting input ends and a sampling capacitor Cs 1; a reset switch RST _ P and a sampling capacitor Cs2 are connected between the directional input end of the second operational amplifier and the output end VP of the second operational amplifier, and the reset switch RST _ P and the sampling capacitor Cs2 are connected in parallel; a reset switch RST _ N and a sampling capacitor Cs3 are connected between the inverting input terminal of the third operational amplifier and the output terminal VN thereof, and the reset switch RST _ N and the sampling capacitor Cs3 are connected in parallel.
As shown in fig. 4, the comparator COMP of the charge compensation analog front end module adopts a pre-amplification and latching structure, and the comparator needs only one clock to operate.
As shown in fig. 5, the first operational amplifier CA in the charge compensation analog front-end module adopts a PMOS differential pair input single-ended output gain enhancement operational amplifier structure, which is composed of a main operational amplifier, UP and DN auxiliary operational amplifiers, both of which are source inputs, and adopts the above structure, so as to achieve large low-frequency gain and low noise, and at the same time, the amplifier has only one low-frequency pole at the output end of the main operational amplifier, so as to satisfy the stability of the feedback loop of the amplifier in the case of large capacitive load range variation, because in the charge amplification portion, when the switch RST _ CA is closed, the load capacitance of the operational amplifier CA includes a large parasitic capacitance, and when RST _ CA is opened, the load capacitance of CA is only Cs 1.
As shown in fig. 6, the second and third operational amplifiers of the single-to-double output module in the charge compensation analog front-end module adopt PMOS pair input and two-stage amplification structures, and the first stage adopts a low-voltage self-biased cascode structure; the second stage adopts a push-pull structure to increase the output swing amplitude; and a Miller compensation capacitor is added between the two stages to ensure the stability in the closed loop.
As shown in fig. 7, the circuit diagram of the capacitor SWITCH is shown, and the on logic of the capacitor SWITCH is:
d is the input of the logic control unit DYNAMIC corresponding to the current capacitor SWITCH, i.e. the output Q of the previous logic control unit DYNAMIC, and N is the N end of the current logic control unit DYNAMIC output; after the comparison of the previous compensation capacitor is completed, the current capacitor SWITCH is turned on, and then the comparison is performed according to the access of the current compensation capacitor, and the result is latched at P, N, where P is the P terminal output by the current logic control unit DYNAMIC, and the N terminal thereof is used to determine whether to remain to access the current compensation capacitor.
As shown in fig. 8, the circuit structure of the logic control unit DYNAMIC is the prior art and is not described herein.
A capacitance measurement method adopting the capacitance measurement circuit based on the charge compensation analog front end comprises the following steps:
step 1, a charge compensation analog front end measures a measured capacitor, converts the measured capacitor value into a form of a compensation capacitor array code and a residual voltage, and outputs the residual voltage to an analog/digital converter;
step 2, the analog/digital converter is used for oversampling the residual voltage and performing analog-to-digital conversion, and outputting the generated oversampled digital code stream to the extraction filter module;
step 3, the decimation filter module reduces the frequency of the digital code and performs low-pass filtering to obtain the digital code of the analog/digital converter; the final capacitance measurement output values are the compensated capacitor array code and the analog/digital converter digital code.
The method is characterized in that: the step 1 further comprises the following steps:
step 1-1, in a first period, firstly, a switch of a first compensation capacitor C8 of a compensation charge array is closed, and the rest capacitors in the array are opened;
step 1-2, excitation signals VEX and NVCR are respectively at a low level VL and VGND, a capacitor switch RST _ CA is closed to reset a capacitor Cfb, a capacitor to be detected and a parasitic capacitor are charged, and after stabilization, the voltage at two ends of the capacitor Cfb is VL;
step 1-3, disconnecting the RST _ CA, enabling excitation signals VEX and NVCR to rise together, and enabling voltage variation amounts to be delta VEX and delta NVCR respectively; at this time, due to the action of the operational amplifier CA, the measured capacitance and the parasitic capacitance (Cx + Cpara) will increase the charge amount (Cx + Cpara) × Δ VEX, and the charge will be mostly provided by the compensation capacitor array and the small charge will be provided by the feedback capacitor; since only the switch of C8 is closed, the compensation capacitor array will provide a charge of C8 × (Δ NVCR- Δ VEX) in the first cycle; the feedback capacitance therefore needs to provide a charge of (Cx + Cpara) x Δ VEX-C8 x (Δ NVCR- Δ VEX); the output of CA is therefore VCM + Δ Vout, where
Steps 1-4. if the output of the first operational amplifier (VCM + Δ Vout) > VCM, representing an under-compensation, then the switch of C8 is kept closed; if (VCM + Δ Vout) < VCM, indicating overcompensation, the switch of C8 is opened;
step 1-5, when the first period is finished, sequentially accessing C7-C0 in the capacitor array, sequentially closing the capacitor switches, and sequentially executing steps 1-2-1-4 to finish second to nine compensation periods;
step 1-6, after 9 periods of compensation, a 9-bit compensation capacitor array code is generated, and finally the output voltage VCA of the compensated CA is VCM + Δ Vout, wherein
The step 1 further comprises:
step 1-7. closing RST _ CA, RST _ N, and PUSAI1, with VEX and NVCR VL and GND, respectively, where VCA is VL and VN is VCM;
step 1-8, firstly disconnecting RST _ N and RST _ CA, respectively raising excitation signals VEX and NVCR to VCM and VDD, then changing the voltage of VCA to delta VEX + delta Vout, under the action of operational amplifier AMP, due to charge conservation, outputting voltage VCM- (delta VEX + delta Vout) by an output end VN;
step 1-9. now, PUSAI1 is turned off, and this voltage will be stored across capacitor Cs;
step 1-10. closing PUSAI2 with RST _ P, VP ═ VCM;
steps 1-11 then turn RST _ P off, RST _ CA on, and VEX down to VL. At this time, the voltage of the VCA changes to- (Δ VEX + Δ Vout), and under the action of the operational amplifier AMP, the output terminal VP will output the voltage VCM + (Δ VEX + Δ Vout) due to the conservation of charge, so that this single-ended voltage is converted into a double-ended voltage centered on the VCM voltage, and the voltage difference VP-VN is equal to 2(Δ VEX + Δ Vout), and the voltage difference VP-VN is the residual voltage; where Δ VEX is a fixed, small value that can be eliminated by subtracting a fixed code value from the output code of the subsequent ADC, but can be directly retained for applications that only require a relatively variable value of capacitance.
The final resulting capacitance measurements were as follows:
Cpara+Cx＝{[(VP-VN)/2-ΔVEX]Cfb+(ΔNVCR-ΔVEX)CCAP_ARRAY}/ΔVEX
since the VP-VN will get binary code after ADC conversion, the VP-VN can be expressed as:
Meanwhile, the capacitance of the capacitor array can also be represented by a capacitor array binary code, and the minimum capacitance of the capacitor array is assumed to be Cmim. It can be expressed as:
CCAP_ARRAY＝Cmim×[CAP_ARRAY_CODE]
after replacing the expression with binary code:
the parameters can be selected to simplify the digital logic operation of combining the final capacitor array code and the code values of the subsequent ADC, for example, when VDD is 3V, VCM is 1.5V, Cfb is 6Cmim, VL is 1.3125V, Δ VEX is 0.1875V, Δ NVCR is 3V)
Cx+Cpara＝6Cmim(8[ADC_CODE]+15[CAP_ARRAY_CODE]-1)。
There are two main modes of operation of the charge compensated analog front end module AFE, depending on the application scenario of the overall CDC:
1: for the application scenario that the parasitic capacitance is large and the variation range of the measured capacitance is small: the parameter values are selected, so that after compensation is performed for one time in a certain environment, the range of the measured capacitor does not overflow the output double-end voltage, compensation is not performed again, after the AFE module generates a 9-bit compensation capacitor array code through one-time operation, the corresponding module can stop working, and the change of the measured capacitor is reflected only by sampling and converting the residual voltage through the analog/digital converter ADC.
The application mode has a small detection range but low power consumption.
2: the application scenario of the measured capacitance with wide variation range is as follows: in each measurement, the AFE module and the analog/digital converter module work all the time, and the output compensation capacitor array code of the AFE module is added with the output digital code of the analog/digital converter to reflect the measured capacitance value.
This measurement range consumes more power but increases the dynamic range of the capacitance measurement circuit.
Claims (10)
1. A capacitance measuring circuit based on a charge compensation analog front end comprises a charge compensation analog front end module AFE, an analog/digital converter ADC, a digital control module, a decimation filter module and a reference voltage module; the input end of the charge compensation analog front end module AFE is connected with the tested capacitor Cx, the output end of the charge compensation analog front end module AFE is connected with the input end of an analog/digital converter (ADC), and the output end of the ADC is connected with the input end of a decimation filter module;
the method is characterized in that: the input end of the charge compensation analog front end module AFE is provided with a compensation charge array module, the compensation charge array module is used for setting a compensation capacitance value according to a parasitic capacitance value and generating a compensation capacitance array code, and the charge compensation analog front end module AFE measures residual voltage and outputs the residual voltage to the analog/digital converter ADC; the analog/digital converter performs analog-to-digital conversion on the residual voltage and generates an oversampled digital code stream, and then outputs the generated oversampled digital code stream to the extraction filter module; the decimation filter module is used for carrying out frequency reduction and low-pass filtering on the digital code to obtain the final output digital code of the analog/digital converter; the final capacitance measurement output value is the addition of the compensated capacitor array code and the output digital code of the analog/digital converter.
2. The charge-compensated analog front-end based capacitance measurement circuit of claim 1, wherein: the charge compensation analog front end module AFE comprises a first operational amplifier CA, a comparator COMP, a compensation charge array module and a single-end-to-double-end module;
the inverting input end of the first operational amplifier CA is connected with the measured capacitor Cx, the parasitic capacitor and the compensation charge array module, and the non-inverting input end of the first operational amplifier CA is connected with the excitation signal VEX; the output end of the first operational amplifier CA is connected with the non-inverting input end of the comparator COMP and the input end of the single-end-to-double-end output module, a feedback capacitor Cfb and a reset switch RST _ CA are connected between the output end and the inverting input end of the first operational amplifier CA, and the feedback capacitor Cfb and the reset switch RST _ CA are connected in parallel;
and the inverting input end of the comparator COMP is connected with the common-mode voltage VCM, and the VOUTN end and the VOUTP end of the comparator are connected with the compensation charge array module.
3. The charge-compensated analog front-end based capacitance measurement circuit of claim 2, wherein: the compensation charge array module comprises a compensation capacitor, a capacitance SWITCH and a logic control unit DYNAMIC;
the compensation capacitors adopt 9 capacitors, the upper pole plate of each compensation capacitor is connected to the inverting input end of the first operational amplifier CA, a capacitor SWITCH is connected between the lower pole plate of each compensation capacitor and the excitation signal NVCR, and each SWITCH is connected with a logic control unit DYNAMIC;
the lower pole plate of each compensation capacitor is connected with the OUT end of a capacitor SWITCH, the D end of the capacitor SWITCH is connected with the D end of the corresponding logic control unit DYNAMIC, the N end of the capacitor SWITCH is connected with the N end of the corresponding logic control unit DYNAMIC, and the IN end of the capacitor SWITCH is connected with an excitation signal NVCR;
the D end of the logic control unit DYNAMIC corresponding to the first compensation capacitor C8 is connected with a reset signal RST _ COMPENSATE, the D ends of the logic control units DYNAMIC corresponding to the other compensation capacitors are respectively connected with the Q end of the logic control unit DYNAMIC corresponding to the last compensation capacitor, and the CMPP end and the CMPN end of each logic control unit DYNAMIC are respectively connected with the VOUTN end and the VOUTP end of the comparator COMP after being inverted by an inverter; the VALID end of each logic control unit DYNAMIC is connected with the VOUTN end and VOUTP end of the comparator COMP through nor gates.
4. A charge-compensated analog front-end based capacitance measurement circuit according to claim 3, wherein: the capacitance values of the 9 compensation capacitors are binary weight distribution, that is, C8-2C 7-4C 6-8C 5-16C 4-32C 3-64C 2-128C 1-256C 0.
5. The charge-compensated analog front-end based capacitance measurement circuit of claim 4, wherein: the single-end-to-double-end output module comprises a second operational amplifier and a third operational amplifier; the non-inverting input ends of the second operational amplifier and the third operational amplifier are connected with the common-mode voltage VCM, the inverting input ends of the second operational amplifier and the third operational amplifier are connected with the output end of the first operational amplifier CA through a sampling capacitor Cs1, and a single-turn double-switch PUSAI2 and a single-turn double-switch PUSAI1 are respectively connected between the inverting input ends and a sampling capacitor Cs 1; a reset switch RST _ P and a sampling capacitor Cs2 are connected between the inverting input end of the second operational amplifier and the output end VP of the second operational amplifier, and the reset switch RST _ P and the sampling capacitor Cs2 are connected in parallel; a reset switch RST _ N and a sampling capacitor Cs3 are connected between the inverting input terminal of the third operational amplifier and the output terminal VN thereof, and the reset switch RST _ N and the sampling capacitor Cs3 are connected in parallel.
6. The charge-compensated analog front end based capacitance measurement circuit of claim 5, wherein: the comparator COMP of the charge compensation analog front end module AFE employs a pre-amplification and latching structure.
7. The charge-compensated analog front end based capacitance measurement circuit of claim 6, wherein: the first operational amplifier CA in the charge compensation analog front end module AFE adopts a PMOS differential pair input, single-ended output and gain enhancement operational amplifier structure, and is composed of a main operational amplifier and two auxiliary operational amplifiers, wherein the two auxiliary operational amplifiers are both source-level input.
8. The charge-compensated analog front end based capacitance measurement circuit of claim 7, wherein: the second and third operational amplifiers of the single-end-to-double-end output module in the charge compensation analog front-end module AFE adopt PMOS differential pair input and two-stage amplification, the first stage adopts a low-voltage self-bias cascode amplification structure, the second stage adopts a push-pull structure, and a Miller compensation capacitor is added between the two stages.
9. A capacitance measuring method using the circuit of claim 8, comprising the steps of:
step 1, a charge compensation analog front end module AFE measures a measured capacitor Cx to obtain a compensation capacitor array code and a residual voltage, and outputs the residual voltage to an analog/digital converter ADC;
step 2, the analog/digital converter ADC is used for oversampling the residual voltage and performing analog-to-digital conversion to obtain an oversampled digital code stream, and outputting the generated oversampled digital code to the extraction filter module;
step 3, the extraction filter module reduces the frequency of the digital code and performs low-pass filtering to obtain the final output digital code of the analog/digital converter; the final output value of the capacitance measurement is in a form of adding the compensation capacitor array code and the output digital code of the analog/digital converter;
the method is characterized in that: the step 1 also comprises the following steps:
step 1-1, in a first period of setting the compensation capacitor, firstly closing a capacitance switch of a first compensation capacitor C8 of the compensation charge array, and disconnecting capacitance switches of the other compensation capacitors in the array;
step 1-2, excitation signals VEX and NVCR are respectively at low levels VL and GND, a reset switch RST _ CA is closed, a feedback capacitor Cfb is reset, a capacitor Cx to be detected and a parasitic capacitor Cpara are charged, after stabilization, the voltage at two ends of the feedback capacitor Cfb is VL, and VL is a fixed constant voltage value smaller than VCM;
step 1-3, the reset switch RST _ CA is turned off, the excitation signals VEX and NVCR rise together, the voltage changes are Δ VEX-VCM-VL and Δ NVCR-VDD-VGND, respectively, the measured capacitance Cx and the parasitic capacitance Cpara will increase the charge amount to (Cx + Cpara) × Δ VEX, wherein the compensation charge array will provide the charge amount of C8 × (Δ NVCR- Δ VEX); the feedback capacitor Cfb needs to provide a charge amount of (Cx + Cpara) x Δ VEX-C8 × (Δ NVCR- Δ VEX); the output of the first operational amplifier CA is therefore VCM + Δ Vout, where
Steps 1-4. if the output of the first operational amplifier (VCM + Δ Vout) > VCM, representing an under-compensation, then the switch of C8 is kept closed; if (VCM + Δ Vout) < VCM, indicating overcompensation, the switch of C8 is opened;
step 1-5, sequentially accessing C7-C0 in the compensation charge array, sequentially closing a capacitance switch of the compensation charge array, and sequentially executing steps 1-2-1-4 to finish the second to nine periods;
step 1-6, after 9 cycles, a compensation capacitor array code of 9 bits will be generated, and finally the output voltage VCA of the first operational amplifier CA after the capacitance compensation is VCM + Δ Vout, where
CCAP_ARRAYThe compensation capacitance value of the charge array is compensated after 9 cycles.
10. The method of claim 9, wherein the measuring method comprises: the step 1 further comprises:
step 1-7, the reset switches RST _ CA and RST _ N and the single-turn double-switch PUSAI1 are closed, the excitation signals VEX and NVCR are set to VL and GND respectively, and at the moment, VCA is VL and VN is VCM;
step 1-8, disconnecting the reset switches RST _ CA and RST _ N, respectively raising the excitation signals VEX and NVCR to VCM and VDD, wherein the voltage of VCA is changed into delta VEX + delta Vout, and the output end VN of the single-end to double-end output module outputs voltage VCM- (delta VEX + delta Vout);
step 1-9. now, PUSAI1 is turned off, and this voltage will be stored across capacitor Cs;
step 1-10, closing the PUSAI2 and RST _ P, and keeping VP equal to VCM;
step 1-11, the RST _ P is turned off, the RST _ CA is turned on, the VEX is decreased to VL, the voltage of the VCA is changed to- (Δ VEX + Δ Vout), the output terminal VP of the single-to-double output module outputs the voltage VCM + (Δ VEX + Δ Vout), so that the single-to-double output module outputs the double-ended voltage centered around the VCM voltage, and the voltage difference VP-VN is equal to 2(Δ VEX + Δ Vout), which is the remaining voltage.
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