CN112255464B - A capacitance measurement circuit and measurement method based on charge compensation analog front end - Google Patents

A capacitance measurement circuit and measurement method based on charge compensation analog front end Download PDF

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CN112255464B
CN112255464B CN202011046679.XA CN202011046679A CN112255464B CN 112255464 B CN112255464 B CN 112255464B CN 202011046679 A CN202011046679 A CN 202011046679A CN 112255464 B CN112255464 B CN 112255464B
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compensation
charge
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capacitor
capacitance
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CN112255464A (en
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陈晓飞
钱旭东
石俊杰
邹雪城
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Huazhong University of Science and Technology
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/30—Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers

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Abstract

本申请提供了一种基于电荷补偿模拟前端的电容测量电路及测量方法，其根据实际的寄生电容值来自动设置补偿电容值，能够保证电容补偿的有效性，保证电容测量电路正常工作，提高电容测量的精度，其包括电荷补偿模拟前端模块、模拟/数字转换器、数字控制模块、抽取滤波器模块和基准电压模块；所述电荷补偿模拟前端模块的输入端与被测电容相连，所述电荷补偿模拟前端模块输出端与所述模拟/数字转换器输入端相连，其特征在于：所述电荷补偿模拟前端模块的输入端设置了补偿电荷阵列模块，所述补偿电荷阵列模块根据寄生电容值设置补偿电容值，所述电荷补偿模拟前端模块得到补偿电容阵列码和剩余电压，并将剩余电压输出到所述模拟/数字转换器。

Figure 202011046679

The present application provides a capacitance measurement circuit and measurement method based on a charge compensation analog front end, which automatically set the compensation capacitance value according to the actual parasitic capacitance value, which can ensure the effectiveness of capacitance compensation, ensure the normal operation of the capacitance measurement circuit, and improve the capacitance The measurement accuracy includes a charge compensation analog front-end module, an analog/digital converter, a digital control module, a decimation filter module and a reference voltage module; the input end of the charge-compensation analog front-end module is connected to the measured capacitor, and the charge The output end of the compensation analog front end module is connected to the input end of the analog/digital converter, and it is characterized in that: the input end of the charge compensation analog front end module is provided with a compensation charge array module, and the compensation charge array module is set according to the parasitic capacitance value To compensate the capacitance value, the charge compensation analog front-end module obtains the compensation capacitance array code and the residual voltage, and outputs the residual voltage to the analog/digital converter.

Figure 202011046679

Description

Capacitance measuring circuit and measuring method based on charge compensation analog front end
Technical Field
The invention relates to the technical field of capacitance measurement, in particular to a capacitance measurement circuit and a measurement method based on a charge compensation analog front end.
Background
Touch screen capacitors of many smart devices are self-capacitance type, that is, one end of a capacitor to be measured is grounded. The capacitance values of these capacitors need to be measured. These self capacitances are typically measured in the prior art using capacitive-to-digital converters. An important component of the capacitance measurement circuit of a capacitance-to-digital converter is the charge-compensated analog front-end.
In the prior art, a charge compensation analog front end of a capacitance measuring circuit mostly adopts a charge amplifying circuit, and the basic charge amplifying circuit has the following problems: it cannot work normally when the parasitic capacitance is above 100 pF. Since large parasitic capacitances generate large amounts of charge that enters the charge amplifying structure, which results in a large voltage step. This voltage step will waste voltage margin and if this voltage value is reduced by increasing the feedback capacitance, the accuracy of the capacitance measurement will be lost and the measurement will not be as accurate.
In the prior art, a charge compensation structure is adopted to solve the above problems, but since the compensation capacitance in the charge compensation structure is a fixed value, the following two problems are caused: 1. the size of the compensation capacitor can be determined only by knowing the size of the parasitic capacitor in advance; 2. if the parasitic capacitance is a capacitance that changes with temperature and humidity, the compensation may fail and may eventually cause the capacitance measuring circuit to fail to function properly.
Disclosure of Invention
The capacitance measurement circuit based on the charge compensation analog front end can solve the problems that compensation capacitance values of a charge compensation structure in the existing capacitance measurement circuit are fixed values and can be determined only by predetermining parasitic capacitance values, so that the compensation capacitance values are difficult to take, the parasitic capacitance changes once possibly to cause compensation failure, and the capacitance measurement circuit can not work normally.
The technical scheme is as follows: a capacitance measuring circuit based on a charge compensation analog front end comprises a charge compensation analog front end module AFE, an analog/digital converter ADC, a digital control module, a decimation filter module and a reference voltage module; the input end of the charge compensation analog front end module AFE is connected with the tested capacitor Cx, the output end of the charge compensation analog front end module AFE is connected with the input end of an analog/digital converter (ADC), and the output end of the ADC is connected with the input end of a decimation filter module;
the method is characterized in that: the input end of the charge compensation analog front end module AFE is provided with a compensation charge array module, the compensation charge array module sets a compensation capacitance value according to a parasitic capacitance value and generates a compensation capacitance array code, and the charge compensation analog front end module AFE measures residual voltage and outputs the residual voltage to the analog/digital converter ADC; the analog/digital converter performs oversampling on the residual voltage and analog-to-digital conversion to generate an oversampled digital code stream, and then outputs the generated oversampled digital code stream to the extraction filter module; the decimation filter module is used for carrying out frequency reduction and low-pass filtering on the digital code to obtain a final analog/digital converter output digital code; the final capacitance measurement output value is the addition of the compensated capacitor array code and the analog/digital converter output digital code.
Further, the charge compensation analog front end module AFE includes a first operational amplifier CA, a comparator COMP, a compensation charge array module, and a single-to-double output module;
the inverting input end of the first operational amplifier CA is connected with the measured capacitor Cx, the parasitic capacitor and the compensation charge array module, and the non-inverting input end of the first operational amplifier CA is connected with the excitation signal VEX; the output end of the first operational amplifier CA is connected with the non-inverting input end of the comparator COMP and the input end of the single-end-to-double-end output module, a feedback capacitor Cfb and a reset switch RST _ CA are connected between the output end and the inverting input end of the first operational amplifier CA, and the feedback capacitor Cfb and the reset switch RST _ CA are connected in parallel;
and the inverting input end of the comparator COMP is connected with the common-mode voltage VCM, and the VOUTN end and the VOUTP end of the comparator are connected with the compensation charge array module.
The compensation charge array module comprises a compensation capacitor, a capacitance SWITCH and a logic control unit DYNAMIC;
the compensation capacitors adopt 9 capacitors, the upper pole plate of each compensation capacitor is connected to the inverting input end of the first operational amplifier CA, a capacitor SWITCH is connected between the lower pole plate of each compensation capacitor and the excitation signal NVCR, and each SWITCH is connected with a logic control unit DYNAMIC;
the lower pole plate of each compensation capacitor is connected with the OUT end of a capacitor SWITCH, the D end of the capacitor SWITCH is connected with the D end of the corresponding logic control unit DYNAMIC, the N end of the capacitor SWITCH is connected with the N end of the corresponding logic control unit DYNAMIC, and the IN end of the capacitor SWITCH is connected with an excitation signal NVCR;
the D end of the logic control unit DYNAMIC corresponding to the first compensation capacitor C8 is connected with a reset signal RST _ COMPENSATE, the D ends of the logic control units DYNAMIC corresponding to the other compensation capacitors are respectively connected with the Q end of the logic control unit DYNAMIC corresponding to the last compensation capacitor, and the CMPP end and the CMPN end of each logic control unit DYNAMIC are respectively connected with the VOUTN end and the VOUTP end of the comparator COMP after phase inversion by an inverter; the VALID end of each logic control unit DYNAMIC is connected with the VOUTN end and VOUTP end of the comparator COMP through nor gates.
The capacitance values of the 9 compensation capacitors are binary weight distribution, and C8-2C 7-4C 6-8C 5-16C 4-32C 3-64C 2-128C 1-256C 0.
The single-end-to-double-end output module comprises a second operational amplifier and a third operational amplifier; the non-inverting input ends of the second operational amplifier and the third operational amplifier are connected with the common-mode voltage VCM, the inverting input ends of the second operational amplifier and the third operational amplifier are connected with the output end of the first operational amplifier CA through a sampling capacitor Cs1, and a single-turn double-switch PUSAI2 and a single-turn double-switch PUSAI1 are respectively connected between the inverting input ends and a sampling capacitor Cs 1; a reset switch RST _ P and a sampling capacitor Cs2 are connected between the inverting input end of the second operational amplifier and the output end VP of the second operational amplifier, and the reset switch RST _ P and the sampling capacitor Cs2 are connected in parallel; a reset switch RST _ N and a sampling capacitor Cs3 are connected between the inverting input end of the third operational amplifier and the output end VN of the third operational amplifier, and the reset switch RST _ N and the sampling capacitor Cs3 are connected in parallel; the comparator COMP of the charge compensation analog front end module AFE employs a pre-amplification and latching structure.
The first operational amplifier CA in the charge compensation analog front end module AFE adopts a PMOS differential pair input, single-ended output and gain enhancement operational amplifier structure, and is composed of a main operational amplifier and two auxiliary operational amplifiers, wherein the two auxiliary operational amplifiers are both source-level input.
The second and third operational amplifiers of the single-end-to-double-end output module in the charge compensation analog front-end module AFE both adopt a p-input and two-stage amplification structure, the first stage adopts a low-voltage self-bias cascode structure, the second stage adopts a push-pull structure, and a Miller compensation capacitor is added between the two stages.
A capacitance measuring method adopting the circuit comprises the following steps:
step 1, a charge compensation analog front end module AFE measures a measured capacitor Cx to obtain a compensation capacitor array code and a residual voltage, and outputs the residual voltage to an analog/digital converter ADC;
step 2, the analog/digital converter ADC is used for oversampling the residual voltage and performing analog-to-digital conversion to obtain an oversampled digital code stream, and outputting the generated oversampled digital code stream to the extraction filter module;
step 3, the extraction filter module reduces the frequency of the digital code and performs low-pass filtering to obtain the final output digital code of the analog/digital converter; the final output value of the capacitance measurement is the addition of the compensation capacitor array code and the digital code output by the analog/digital converter;
the method is characterized in that: the step 1 also comprises the following steps:
step 1-1, in a first period of setting the compensation capacitor, firstly closing a capacitance switch of a first compensation capacitor C8 of the compensation charge array, and disconnecting capacitance switches of the other compensation capacitors in the array;
step 1-2, excitation signals VEX and NVCR are respectively at low levels VL and VGND, a reset switch RST _ CA is closed, a feedback capacitor Cfb is reset, a measured capacitor Cx and a parasitic capacitor Cpara are charged, after stabilization, the voltage across the feedback capacitor Cfb is VL, and VL is a fixed constant voltage value (for example, 1.3125V) smaller than VCM;
step 1-3, the reset switch RST _ CA is turned off, the excitation signals VEX and NVCR rise together, the voltage changes are Δ VEX-VCM-VL and Δ NVCR-VDD-VGND, respectively, the measured capacitance Cx and the parasitic capacitance Cpara will increase the charge amount to (Cx + Cpara) × Δ VEX, wherein the compensation charge array will provide the charge amount of C8 × (Δ NVCR- Δ VEX); the feedback capacitor Cfb needs to provide a charge amount of (Cx + Cpara) x Δ VEX-C8 × (Δ NVCR- Δ VEX); the output of the first operational amplifier CA is therefore VCM + Δ Vout, where
Figure BDA0002708218920000021
Steps 1-4. if the output of the first operational amplifier (VCM + Δ Vout) > VCM, representing an under-compensation, then the switch of C8 is kept closed; if (VCM + Δ Vout) < VCM, indicating overcompensation, the switch of C8 is opened;
step 1-5, sequentially accessing C7-C0 in the compensation charge array, sequentially closing a capacitance switch of the compensation charge array, and sequentially executing steps 1-2-1-4 to finish the second to nine periods;
step 1-6, after 9 cycles, a compensation capacitor array code of 9 bits will be generated, and finally the output voltage VCA of the first operational amplifier CA after the capacitance compensation is VCM + Δ Vout, where
Figure BDA0002708218920000022
CCAP_ARRAYThe compensation capacitance value of the charge array is compensated after 9 cycles.
The step 1 further comprises:
step 1-7, the reset switches RST _ CA and RST _ N and the single-turn double-switch PUSAI1 are closed, the excitation signals VEX and NVCR are set to VL and GND respectively, and at the moment, VCA is VL and VN is VCM;
step 1-8, disconnecting the reset switches RST _ CA and RST _ N, respectively raising the excitation signals VEX and NVCR to VCM and VDD, wherein the voltage of VCA is changed into delta VEX + delta Vout, and the output end VN of the single-end to double-end output module outputs voltage VCM- (delta VEX + delta Vout);
step 1-9. now, PUSAI1 is turned off, and this voltage will be stored across capacitor Cs;
step 1-10, closing the PUSAI2 and RST _ P, and keeping VP equal to VCM;
step 1-11, the RST _ P is turned off, the RST _ CA is turned on, the VEX is decreased to VL, the voltage of the VCA is changed to- (Δ VEX + Δ Vout), the output terminal VP of the single-to-double output module outputs the voltage VCM + (Δ VEX + Δ Vout), so that the single-to-double output module outputs the double-ended voltage centered around the VCM voltage, and the voltage difference VP-VN is equal to 2(Δ VEX + Δ Vout), which is the remaining voltage.
The invention provides a capacitance measuring circuit and a capacitance measuring method based on a charge compensation analog front end, which have the following beneficial effects: the compensation capacitance value is automatically set according to the actual parasitic capacitance value by setting the charge compensation array, the fixed compensation capacitance value is not required to be set by determining the parasitic capacitance value in advance, the problems that the compensation fails and the measurement circuit cannot work due to the fact that the parasitic capacitance changes along with the changes of temperature and humidity are avoided, the effectiveness of capacitance compensation and the normal work of the capacitance measurement circuit can be guaranteed, and the precision of capacitance measurement is improved.
Drawings
FIG. 1 is an overall schematic diagram of a capacitance measurement circuit;
FIG. 2 is a circuit diagram of a charge compensated analog front end module;
FIG. 3 is a schematic diagram of a charge compensation array circuit;
FIG. 4 is a circuit diagram of the comparator COMP;
FIG. 5 is a circuit diagram of a first operational amplifier;
FIG. 6 is a circuit diagram of a second/third operational amplifier;
FIG. 7 is a circuit diagram of a capacitor SWITCH;
fig. 8 is a circuit diagram of a logic control unit.
Detailed Description
As shown in fig. 1, a capacitance measuring circuit based on a charge compensation analog front end includes a charge compensation analog front end module AFE, an analog/digital converter ADC, a digital control module, a decimation filter module, and a reference voltage module.
The reference voltage module is respectively connected with the charge compensation analog front end module AFE, the analog/digital converter ADC, the digital control module and the decimation filter module and is used for providing reference voltage required by the modules.
The digital control module is connected with the charge compensation analog front end module, the analog/digital converter and the decimation filter module and is used for providing logic operation and time sequence control.
The input end of the charge compensation analog front end module AFE is connected with the measured capacitor Cx, and the output end of the charge compensation analog front end module AFE is connected with the sampling input end of the analog/digital converter ADC.
The input end of the charge compensation analog front end module AFE is provided with a compensation charge array module, the compensation charge array module is provided with a compensation capacitance value according to a parasitic capacitance value, and the charge compensation analog front end module AFE is used for converting the value of the measured capacitance Cx into an addition form of a compensation capacitance array code and a residual voltage and outputting the residual voltage to the analog/digital converter ADC.
The output end of the analog/digital converter ADC is connected with the input end of the extraction filter module, the analog/digital converter ADC is used for oversampling the residual voltage and performing analog-to-digital conversion to generate an oversampled digital code stream, and then the generated oversampled digital code stream is output to the extraction filter module.
The decimation filter module is used for carrying out frequency reduction and low-pass filtering on the digital code to obtain a final analog/digital converter output digital code; the final output value of the measured capacitance Cx is the addition of the compensation capacitance array code and the analog/digital converter output digital code.
As shown in fig. 2, the charge compensation analog front end module AFE includes: the circuit comprises a first operational amplifier CA, a comparator COMP, a compensation charge array module and a single-end to double-end output module. Cx and Cpara are respectively a tested capacitor and a parasitic capacitor, Cfb is a feedback capacitor, Cs1, Cs2 and Cs3 are sampling capacitors, RST _ CA and RST _ P, RST _ N are reset switches, and PUSAI2 and PUSAI1 are single-switch double-switch switches; VCM is half the common mode voltage, i.e., VDD; VEX and NVCR are excitation signals; NVCR has a range of variation from GND to VDD, VEX has a range of variation from VL to VCM, where VL < VCM, followed by Δ NVCR-VDD, Δ VEX-VCM-VL for convenience, where Δ NVCR is much larger than Δ VEX, and VL is a fixed constant voltage value less than VCM, such as 1.3125V.
The inverting input end of the first operational amplifier CA is connected with the measured capacitor Cx, the parasitic capacitor and the compensation charge array module, and the non-inverting input end of the first operational amplifier CA is connected with the excitation signal VEX.
The output end of the first operational amplifier is connected with the non-inverting input end of a comparator COMP and the input end of a single-end-to-double-end output module, a feedback capacitor Cfb and a reset switch RST _ CA are connected between the output end and the inverting input end, and the feedback capacitor Cfb and the reset switch RST _ CA are connected in parallel; and the inverting input end of the comparator COMP is connected with the common-mode voltage VCM, and the VOUTN end and the VOUTP end of the comparator are connected with the compensation charge array module.
As shown in fig. 3, the compensation charge array module includes a compensation capacitor, a capacitor SWITCH, and a logic control unit DYNAMIC.
The compensation capacitors adopt a mode of connecting 9 capacitors in parallel, the upper electrode plate of each compensation capacitor is connected to the inverting input end of the first operational amplifier CA, a capacitor SWITCH is connected between the lower electrode plate of each compensation capacitor and the excitation signal NVCR, and each SWITCH is connected with a logic control unit DYNAMIC.
The lower pole plate of each compensation capacitor is connected with the OUT end of a capacitor SWITCH, the D end of the capacitor SWITCH is connected with the D end of the corresponding logic control unit DYNAMIC, the N end of the capacitor SWITCH is connected with the N end of the corresponding logic control unit DYNAMIC, and the IN end of the capacitor SWITCH is connected with the excitation signal NVCR.
The D end of the logic control unit DYNAMIC corresponding to the first compensation capacitor C8 is connected with a reset signal RST _ COMPENSATE, the D ends of the logic control units DYNAMIC corresponding to the other compensation capacitors are respectively connected with the Q end of the logic control unit DYNAMIC corresponding to the last compensation capacitor, and the CMPP end and the CMPN end of each logic control unit DYNAMIC are respectively connected with the VOUTN end and the VOUTP end of the comparator COMP after phase inversion by an inverter; the VALID end of each logic control unit DYNAMIC is connected with the VOUTN end and the VOUTP end of a comparator COMP through a NOR gate; the capacitance values of the 9 compensation capacitors are binary weight distribution, that is, C8-2C 7-4C 6-8C 5-16C 4-32C 3-64C 2-128C 1-256C 0.
The single-end-to-double-end output module comprises a second operational amplifier and a third operational amplifier; the non-inverting input ends of the second operational amplifier and the third operational amplifier are connected with the common-mode voltage VCM, the inverting input ends of the second operational amplifier and the third operational amplifier are connected with the output end of the first operational amplifier CA through a sampling capacitor Cs1, and a single-turn double-switch PUSAI2 and a single-turn double-switch PUSAI1 are respectively connected between the inverting input ends and a sampling capacitor Cs 1; a reset switch RST _ P and a sampling capacitor Cs2 are connected between the directional input end of the second operational amplifier and the output end VP of the second operational amplifier, and the reset switch RST _ P and the sampling capacitor Cs2 are connected in parallel; a reset switch RST _ N and a sampling capacitor Cs3 are connected between the inverting input terminal of the third operational amplifier and the output terminal VN thereof, and the reset switch RST _ N and the sampling capacitor Cs3 are connected in parallel.
As shown in fig. 4, the comparator COMP of the charge compensation analog front end module adopts a pre-amplification and latching structure, and the comparator needs only one clock to operate.
As shown in fig. 5, the first operational amplifier CA in the charge compensation analog front-end module adopts a PMOS differential pair input single-ended output gain enhancement operational amplifier structure, which is composed of a main operational amplifier, UP and DN auxiliary operational amplifiers, both of which are source inputs, and adopts the above structure, so as to achieve large low-frequency gain and low noise, and at the same time, the amplifier has only one low-frequency pole at the output end of the main operational amplifier, so as to satisfy the stability of the feedback loop of the amplifier in the case of large capacitive load range variation, because in the charge amplification portion, when the switch RST _ CA is closed, the load capacitance of the operational amplifier CA includes a large parasitic capacitance, and when RST _ CA is opened, the load capacitance of CA is only Cs 1.
As shown in fig. 6, the second and third operational amplifiers of the single-to-double output module in the charge compensation analog front-end module adopt PMOS pair input and two-stage amplification structures, and the first stage adopts a low-voltage self-biased cascode structure; the second stage adopts a push-pull structure to increase the output swing amplitude; and a Miller compensation capacitor is added between the two stages to ensure the stability in the closed loop.
As shown in fig. 7, the circuit diagram of the capacitor SWITCH is shown, and the on logic of the capacitor SWITCH is:
Figure BDA0002708218920000041
d is the input of the logic control unit DYNAMIC corresponding to the current capacitor SWITCH, i.e. the output Q of the previous logic control unit DYNAMIC, and N is the N end of the current logic control unit DYNAMIC output; after the comparison of the previous compensation capacitor is completed, the current capacitor SWITCH is turned on, and then the comparison is performed according to the access of the current compensation capacitor, and the result is latched at P, N, where P is the P terminal output by the current logic control unit DYNAMIC, and the N terminal thereof is used to determine whether to remain to access the current compensation capacitor.
As shown in fig. 8, the circuit structure of the logic control unit DYNAMIC is the prior art and is not described herein.
A capacitance measurement method adopting the capacitance measurement circuit based on the charge compensation analog front end comprises the following steps:
step 1, a charge compensation analog front end measures a measured capacitor, converts the measured capacitor value into a form of a compensation capacitor array code and a residual voltage, and outputs the residual voltage to an analog/digital converter;
step 2, the analog/digital converter is used for oversampling the residual voltage and performing analog-to-digital conversion, and outputting the generated oversampled digital code stream to the extraction filter module;
step 3, the decimation filter module reduces the frequency of the digital code and performs low-pass filtering to obtain the digital code of the analog/digital converter; the final capacitance measurement output values are the compensated capacitor array code and the analog/digital converter digital code.
The method is characterized in that: the step 1 further comprises the following steps:
step 1-1, in a first period, firstly, a switch of a first compensation capacitor C8 of a compensation charge array is closed, and the rest capacitors in the array are opened;
step 1-2, excitation signals VEX and NVCR are respectively at a low level VL and VGND, a capacitor switch RST _ CA is closed to reset a capacitor Cfb, a capacitor to be detected and a parasitic capacitor are charged, and after stabilization, the voltage at two ends of the capacitor Cfb is VL;
step 1-3, disconnecting the RST _ CA, enabling excitation signals VEX and NVCR to rise together, and enabling voltage variation amounts to be delta VEX and delta NVCR respectively; at this time, due to the action of the operational amplifier CA, the measured capacitance and the parasitic capacitance (Cx + Cpara) will increase the charge amount (Cx + Cpara) × Δ VEX, and the charge will be mostly provided by the compensation capacitor array and the small charge will be provided by the feedback capacitor; since only the switch of C8 is closed, the compensation capacitor array will provide a charge of C8 × (Δ NVCR- Δ VEX) in the first cycle; the feedback capacitance therefore needs to provide a charge of (Cx + Cpara) x Δ VEX-C8 x (Δ NVCR- Δ VEX); the output of CA is therefore VCM + Δ Vout, where
Figure BDA0002708218920000051
Steps 1-4. if the output of the first operational amplifier (VCM + Δ Vout) > VCM, representing an under-compensation, then the switch of C8 is kept closed; if (VCM + Δ Vout) < VCM, indicating overcompensation, the switch of C8 is opened;
step 1-5, when the first period is finished, sequentially accessing C7-C0 in the capacitor array, sequentially closing the capacitor switches, and sequentially executing steps 1-2-1-4 to finish second to nine compensation periods;
step 1-6, after 9 periods of compensation, a 9-bit compensation capacitor array code is generated, and finally the output voltage VCA of the compensated CA is VCM + Δ Vout, wherein
Figure BDA0002708218920000052
The step 1 further comprises:
step 1-7. closing RST _ CA, RST _ N, and PUSAI1, with VEX and NVCR VL and GND, respectively, where VCA is VL and VN is VCM;
step 1-8, firstly disconnecting RST _ N and RST _ CA, respectively raising excitation signals VEX and NVCR to VCM and VDD, then changing the voltage of VCA to delta VEX + delta Vout, under the action of operational amplifier AMP, due to charge conservation, outputting voltage VCM- (delta VEX + delta Vout) by an output end VN;
step 1-9. now, PUSAI1 is turned off, and this voltage will be stored across capacitor Cs;
step 1-10. closing PUSAI2 with RST _ P, VP ═ VCM;
steps 1-11 then turn RST _ P off, RST _ CA on, and VEX down to VL. At this time, the voltage of the VCA changes to- (Δ VEX + Δ Vout), and under the action of the operational amplifier AMP, the output terminal VP will output the voltage VCM + (Δ VEX + Δ Vout) due to the conservation of charge, so that this single-ended voltage is converted into a double-ended voltage centered on the VCM voltage, and the voltage difference VP-VN is equal to 2(Δ VEX + Δ Vout), and the voltage difference VP-VN is the residual voltage; where Δ VEX is a fixed, small value that can be eliminated by subtracting a fixed code value from the output code of the subsequent ADC, but can be directly retained for applications that only require a relatively variable value of capacitance.
The final resulting capacitance measurements were as follows:
Cpara+Cx＝{[(VP-VN)/2-ΔVEX]Cfb+(ΔNVCR-ΔVEX)CCAP_ARRAY}/ΔVEX
since the VP-VN will get binary code after ADC conversion, the VP-VN can be expressed as:
Figure BDA0002708218920000053
(assuming that the number of bits of the ADC is 14 bits)
Meanwhile, the capacitance of the capacitor array can also be represented by a capacitor array binary code, and the minimum capacitance of the capacitor array is assumed to be Cmim. It can be expressed as:
CCAP_ARRAY＝Cmim×[CAP_ARRAY_CODE]
after replacing the expression with binary code:
Figure BDA0002708218920000054
the parameters can be selected to simplify the digital logic operation of combining the final capacitor array code and the code values of the subsequent ADC, for example, when VDD is 3V, VCM is 1.5V, Cfb is 6Cmim, VL is 1.3125V, Δ VEX is 0.1875V, Δ NVCR is 3V)
Cx+Cpara＝6Cmim(8[ADC_CODE]+15[CAP_ARRAY_CODE]-1)。
There are two main modes of operation of the charge compensated analog front end module AFE, depending on the application scenario of the overall CDC:
1: for the application scenario that the parasitic capacitance is large and the variation range of the measured capacitance is small: the parameter values are selected, so that after compensation is performed for one time in a certain environment, the range of the measured capacitor does not overflow the output double-end voltage, compensation is not performed again, after the AFE module generates a 9-bit compensation capacitor array code through one-time operation, the corresponding module can stop working, and the change of the measured capacitor is reflected only by sampling and converting the residual voltage through the analog/digital converter ADC.
The application mode has a small detection range but low power consumption.
2: the application scenario of the measured capacitance with wide variation range is as follows: in each measurement, the AFE module and the analog/digital converter module work all the time, and the output compensation capacitor array code of the AFE module is added with the output digital code of the analog/digital converter to reflect the measured capacitance value.
This measurement range consumes more power but increases the dynamic range of the capacitance measurement circuit.

Claims (10)

1.一种基于电荷补偿模拟前端的电容测量电路，其包括电荷补偿模拟前端模块AFE、模拟/数字转换器ADC、数字控制模块、抽取滤波器模块和基准电压模块；所述电荷补偿模拟前端模块AFE的输入端与被测电容Cx相连，所述电荷补偿模拟前端模块AFE输出端与模拟/数字转换器ADC输入端相连，所述模拟/数字转换器ADC的输出端与抽取滤波器模块输入端相连；1. A capacitance measurement circuit based on a charge compensation analog front end, comprising a charge compensation analog front end module AFE, an analog/digital converter ADC, a digital control module, an extraction filter module and a reference voltage module; the charge compensation analog front end module The input end of the AFE is connected to the measured capacitor Cx, the output end of the charge compensation analog front-end module AFE is connected to the input end of the analog/digital converter ADC, and the output end of the analog/digital converter ADC is connected to the input end of the decimation filter module connected; 其特征在于：所述电荷补偿模拟前端模块AFE的输入端设置了补偿电荷阵列模块，所述补偿电荷阵列模块用于根据寄生电容值设置补偿电容值并生成补偿电容阵列码，所述电荷补偿模拟前端模块AFE测得剩余电压并将其输出到模拟/数字转换器ADC；所述模拟/数字转换器对剩余电压进行模数转换并产生过采样数字码流，然后将产生的过采样数字码流输出给抽取滤波器模块；所述抽取滤波器模块将数字码降频和低通滤波后得到最终的模拟/数字转换器的输出数字码；最终电容测量的输出值为所述补偿电容阵列码和所述模拟/数字转换器的输出数字码相加。It is characterized in that: a compensation charge array module is set at the input end of the charge compensation analog front-end module AFE, and the compensation charge array module is used to set the compensation capacitance value according to the parasitic capacitance value and generate the compensation capacitance array code, and the charge compensation simulation The front-end module AFE measures the residual voltage and outputs it to the analog/digital converter ADC; the analog/digital converter performs analog-to-digital conversion on the residual voltage and generates an oversampled digital code stream, and then converts the generated oversampled digital code stream Output to the decimation filter module; the decimation filter module obtains the output digital code of the final analog/digital converter after frequency reduction and low-pass filtering of the digital code; the output value of the final capacitance measurement is the compensation capacitor array code and The output digital codes of the analog/digital converters are added. 2.根据权利要求1所述一种基于电荷补偿模拟前端的电容测量电路，其特征在于：所述电荷补偿模拟前端模块AFE包括第一运算放大器CA、比较器COMP、补偿电荷阵列模块、单端转双端模块；2. A capacitance measurement circuit based on a charge compensation analog front end according to claim 1, wherein the charge compensation analog front end module AFE comprises a first operational amplifier CA, a comparator COMP, a compensation charge array module, a single-ended To double-ended module; 所述第一运算放大器CA的反相输入端连接被测电容Cx、寄生电容和补偿电荷阵列模块，同相输入端连接激励信号VEX；第一运算放大器CA的输出端连接比较器COMP的同相输入端和单端转双端输出模块的输入端，在第一运算放大器CA的输出端和反相输入端之间连接反馈电容Cfb和复位开关RST_CA，反馈电容Cfb和复位开关RST_CA并联；The inverting input terminal of the first operational amplifier CA is connected to the measured capacitor Cx, the parasitic capacitance and the compensation charge array module, the non-inverting input terminal is connected to the excitation signal VEX; the output terminal of the first operational amplifier CA is connected to the non-inverting input terminal of the comparator COMP and the input terminal of the single-ended to double-ended output module, the feedback capacitor Cfb and the reset switch RST_CA are connected between the output terminal of the first operational amplifier CA and the inverting input terminal, and the feedback capacitor Cfb and the reset switch RST_CA are connected in parallel; 比较器COMP的反相输入端连接共模电压VCM，比较器的VOUTN端和VOUTP端连接补偿电荷阵列模块。The inverting input terminal of the comparator COMP is connected to the common mode voltage VCM, and the VOUTN terminal and the VOUTP terminal of the comparator are connected to the compensation charge array module. 3.根据权利要求2所述一种基于电荷补偿模拟前端的电容测量电路，其特征在于：补偿电荷阵列模块包含补偿电容、电容开关SWITCH、逻辑控制单元DYNAMIC；3. a kind of capacitance measurement circuit based on charge compensation analog front end according to claim 2, is characterized in that: compensation charge array module comprises compensation capacitance, capacitance switch SWITCH, logic control unit DYNAMIC; 补偿电容采用9个电容，各补偿电容的上极板连接到第一运算放大器CA的反相输入端，各补偿电容的下极板和激励信号NVCR之间均连接有一个电容开关SWITCH，每个SWITCH又与一个逻辑控制单元DYNAMIC相连；The compensation capacitor adopts 9 capacitors, the upper plate of each compensation capacitor is connected to the inverting input terminal of the first operational amplifier CA, and a capacitor switch SWITCH is connected between the lower plate of each compensation capacitor and the excitation signal NVCR, each SWITCH is connected with a logic control unit DYNAMIC; 各补偿电容的下极板连接电容开关SWITCH的OUT端，电容开关SWITCH的D端与对应的逻辑控制单元DYNAMIC的D端相连，电容开关SWITCH的N端与对应的逻辑控制单元DYNAMIC的N端相连，电容开关SWITCH的IN端与激励信号NVCR相连；The lower plate of each compensation capacitor is connected to the OUT terminal of the capacitive switch SWITCH, the D terminal of the capacitive switch SWITCH is connected to the D terminal of the corresponding logic control unit DYNAMIC, and the N terminal of the capacitive switch SWITCH is connected to the corresponding logic control unit DYNAMIC. , the IN terminal of the capacitive switch SWITCH is connected to the excitation signal NVCR; 第一补偿电容C8对应的逻辑控制单元DYNAMIC的D端接复位信号RST_COMPENSATE，其余各补偿电容对应的逻辑控制单元DYNAMIC的D端分别接上一个补偿电容对应的逻辑控制单元DYNAMIC的Q端，各逻辑控制单元DYNAMIC的CMPP端和CMPN端分别与比较器COMP的VOUTN端和VOUTP端经反相器取反后相连；各逻辑控制单元DYNAMIC的VALID端与比较器COMP的VOUTN端、VOUTP端经或非门后相连。The D terminal of the logic control unit DYNAMIC corresponding to the first compensation capacitor C8 is connected to the reset signal RST_COMPENSATE, and the D terminals of the logic control unit DYNAMIC corresponding to the other compensation capacitors are respectively connected to the Q terminal of the logic control unit DYNAMIC corresponding to a compensation capacitor. The CMPP end and the CMPN end of the control unit DYNAMIC are respectively connected with the VOUTN end and the VOUTP end of the comparator COMP through the inversion of the inverter; Connected behind the door. 4.根据权利要求3所述一种基于电荷补偿模拟前端的电容测量电路，其特征在于：9个补偿电容的电容值为二进制权值分布，即C8＝2C7＝4C6＝8C5＝16C4＝32C3＝64C2＝128C1＝256C0。4. A capacitance measurement circuit based on a charge compensation analog front end according to claim 3, wherein the capacitance values of the 9 compensation capacitors are binary weight distribution, that is, C8=2C7=4C6=8C5=16C4=32C3= 64C2=128C1=256C0. 5.根据权利要求4所述一种基于电荷补偿模拟前端的电容测量电路，其特征在于：所述单端转双端输出模块包括第二运算放大器、第三运算放大器；第二、三运算放大器的同相输入端均与共模电压VCM相连，第二、三运算放大器的反相输入端均通过采样电容Cs1与第一运算放大器CA的输出端相连，上述反相输入端与采样电容Cs1之间还分别连接单转双开关PUSAI2、PUSAI1；第二运算放大器的反相输入端与其输出端VP之间连接有复位开关RST_P和采样电容Cs2，复位开关RST_P和采样电容Cs2并联；第三运算放大器的反相输入端与其输出端VN之间连接有复位开关RST_N和采样电容Cs3，复位开关RST_N和采样电容Cs3并联。5. The capacitance measurement circuit based on a charge compensation analog front end according to claim 4, wherein the single-ended to double-ended output module comprises a second operational amplifier and a third operational amplifier; the second and third operational amplifiers The non-inverting input terminals of the second and third operational amplifiers are connected to the common mode voltage VCM, the inverting input terminals of the second and third operational amplifiers are connected to the output terminal of the first operational amplifier CA through the sampling capacitor Cs1, and the inverting input terminal and the sampling capacitor Cs1 are also connected. The single-turn double switches PUSAI2 and PUSAI1 are respectively connected; between the inverting input terminal of the second operational amplifier and its output terminal VP, a reset switch RST_P and a sampling capacitor Cs2 are connected, and the reset switch RST_P and the sampling capacitor Cs2 are connected in parallel; A reset switch RST_N and a sampling capacitor Cs3 are connected between the phase input terminal and its output terminal VN, and the reset switch RST_N and the sampling capacitor Cs3 are connected in parallel. 6.根据权利要求5所述一种基于电荷补偿模拟前端的电容测量电路，其特征在于：电荷补偿模拟前端模块AFE的比较器COMP采用预放大和锁存结构。6 . The capacitance measurement circuit based on the charge compensation analog front end according to claim 5 , wherein the comparator COMP of the charge compensation analog front end module AFE adopts a pre-amplification and latch structure. 7 . 7.根据权利要求6所述一种基于电荷补偿模拟前端的电容测量电路，其特征在于：电荷补偿模拟前端模块AFE中第一运算放大器CA采用PMOS差动对输入、单端输出、增益增强运算放大器结构，由主运算放大器、两个辅助运算放大器构成，两个辅助运算放大器均为源级输入。7. a kind of capacitance measurement circuit based on charge compensation analog front end according to claim 6, it is characterized in that: first operational amplifier CA in charge compensation analog front end module AFE adopts PMOS differential to input, single-ended output, gain enhancement operation The amplifier structure consists of a main operational amplifier and two auxiliary operational amplifiers, both of which are source-level inputs. 8.根据权利要求7所述一种基于电荷补偿模拟前端的电容测量电路，其特征在于：电荷补偿模拟前端模块AFE中单端转双端输出模块的第二、三运算放大器均采用PMOS差动对输入、两级放大，第一级使用了低压自偏置共源共栅放大结构，第二级使用了推挽式结构，两级之间加入米勒补偿电容。8. a kind of capacitance measuring circuit based on charge compensation analog front end according to claim 7, is characterized in that: the second and third operational amplifiers of single-end to double-end output module in charge compensation analog front-end module AFE all adopt PMOS differential For input and two-stage amplification, the first stage uses a low-voltage self-biased cascode amplification structure, the second stage uses a push-pull structure, and a Miller compensation capacitor is added between the two stages. 9.一种采用上述权利要求8所述的电路的电容测量方法，步骤包括：9. A method for measuring capacitance using the circuit of claim 8, the step comprising: 步骤1.电荷补偿模拟前端模块AFE测量被测电容Cx，得到补偿电容阵列码和剩余电压，并将剩余电压输出到模拟/数字转换器ADC；Step 1. The charge compensation analog front-end module AFE measures the measured capacitance Cx, obtains the compensation capacitance array code and residual voltage, and outputs the residual voltage to the analog/digital converter ADC; 步骤2.模拟/数字转换器ADC用于对剩余电压进行过采样并进行模数转化得到过采样数字码流，将产生的过采样数字码输出给抽取滤波器模块；Step 2. The analog/digital converter ADC is used to oversample the residual voltage and perform analog-to-digital conversion to obtain an oversampled digital code stream, and output the generated oversampled digital code to the decimation filter module; 步骤3.抽取滤波器模块将数字码降频并低通滤波后得到最终的模拟/数字转换器输出数字码；最终的电容测量的输出值为补偿电容阵列码和模拟/数字转换器输出数字码相加的形式；Step 3. The decimation filter module down-converts and low-pass filters the digital code to obtain the final analog/digital converter output digital code; the output value of the final capacitance measurement is the compensation capacitor array code and the analog/digital converter output digital code the form of addition; 其特征在于：其步骤1中还包括以下步骤：It is characterized in that: its step 1 also includes the following steps: 步骤1-1.在设置补偿电容的第一个周期中，首先将补偿电荷阵列的第一补偿电容C8的电容开关闭合，阵列中其余补偿电容的电容开关断开；Step 1-1. In the first cycle of setting the compensation capacitor, firstly, the capacitance switch of the first compensation capacitor C8 of the compensation charge array is closed, and the capacitance switches of the remaining compensation capacitors in the array are turned off; 步骤1-2.激励信号VEX和NVCR分别处在低电平VL和GND，复位开关RST_CA闭合，对反馈电容Cfb进行复位，被测电容Cx以及寄生电容Cpara将被充电，稳定后反馈电容Cfb两端的电压均为VL，VL是小于VCM的固定常数电压值；Step 1-2. The excitation signals VEX and NVCR are at low levels VL and GND respectively, the reset switch RST_CA is closed, and the feedback capacitor Cfb is reset. The measured capacitor Cx and the parasitic capacitor Cpara will be charged. After stabilization, the feedback capacitor Cfb is two The voltages of the terminals are all VL, and VL is a fixed constant voltage value less than VCM; 步骤1-3.将复位开关RST_CA断开，激励信号VEX和NVCR一同上升，电压变化量分别为ΔVEX＝VCM-VL和ΔNVCR＝VDD-VGND，被测电容Cx和寄生电容Cpara将会增加电荷量为(Cx+Cpara)×ΔVEX，其中补偿电荷阵列将提供C8×(ΔNVCR-ΔVEX)的电荷量；反馈电容Cfb需要提供的电荷量为(Cx+Cpara)×ΔVEX-C8×(ΔNVCR-ΔVEX)；因此第一运算放大器CA的输出为VCM+ΔVout，其中Step 1-3. Turn off the reset switch RST_CA, the excitation signals VEX and NVCR rise together, the voltage changes are ΔVEX=VCM-VL and ΔNVCR=VDD-VGND respectively, the measured capacitance Cx and parasitic capacitance Cpara will increase the amount of charge It is (Cx+Cpara)×ΔVEX, where the compensation charge array will provide the charge of C8×(ΔNVCR-ΔVEX); the charge that the feedback capacitor Cfb needs to provide is (Cx+Cpara)×ΔVEX-C8×(ΔNVCR-ΔVEX) ; so the output of the first operational amplifier CA is VCM+ΔVout, where
Figure FDA0003094509000000021
Figure FDA0003094509000000021
 步骤1-4.如果第一运算放大器的输出(VCM+ΔVout)>VCM，表示欠补偿，则保持C8的开关闭合；如果(VCM+ΔVout)<VCM，表示过补偿，则把C8的开关断开；Step 1-4. If the output of the first operational amplifier (VCM+ΔVout)>VCM, indicating undercompensation, keep the switch of C8 closed; if (VCM+ΔVout)<VCM, indicating overcompensation, then turn off the switch of C8. open; 步骤1-5.将补偿电荷阵列中的C7至C0依次接入，依次将其电容开关闭合，依次执行步骤1-2至1-4，完成第二个至九个周期；Step 1-5. Connect C7 to C0 in the compensation charge array in turn, close their capacitor switches in turn, and execute steps 1-2 to 1-4 in turn to complete the second to nine cycles; 步骤1-6.在9个周期之后，将会产生9位的补偿电容阵列码，最终经过电容补偿后第一运算放大器CA的输出电压VCA为VCM+ΔVout，其中Step 1-6. After 9 cycles, a 9-bit compensation capacitor array code will be generated, and finally the output voltage VCA of the first operational amplifier CA after capacitance compensation is VCM+ΔVout, where
Figure FDA0003094509000000022
Figure FDA0003094509000000022
 CCAP_ARRAY为9个周期后补偿电荷阵列的补偿电容值。C CAP_ARRAY is the compensation capacitance value of the compensation charge array after 9 cycles. 10.根据权利要求9所述一种基于电荷补偿模拟前端的电容测量电路的测量方法，其特征在于：步骤1还包括：10. The method for measuring a capacitance measuring circuit based on a charge compensation analog front end according to claim 9, wherein step 1 further comprises: 步骤1-7.将复位开关RST_CA、RST_N以及单转双开关PUSAI1闭合,激励信号VEX和NVCR分别设置为VL和GND，此时VCA＝VL，VN＝VCM；Step 1-7. Close the reset switches RST_CA, RST_N and the single-turn double switch PUSAI1, and set the excitation signals VEX and NVCR to VL and GND respectively, at this time VCA=VL, VN=VCM; 步骤1-8.再将复位开关RST_CA、RST_N断开，激励信号VEX和NVCR分别上升至VCM和VDD，这时VCA的电压变化为ΔVEX+ΔVout，此时单端转双端输出模块的输出端VN将会输出电压为VCM-(ΔVEX+ΔVout)；Step 1-8. Then turn off the reset switches RST_CA and RST_N, and the excitation signals VEX and NVCR rise to VCM and VDD, respectively. At this time, the voltage of VCA changes to ΔVEX+ΔVout. At this time, the output terminal of the single-ended to double-ended output module VN will output the voltage as VCM-(ΔVEX+ΔVout); 步骤1-9.此时将PUSAI1断开，这个电压将被保存在电容Cs两端；Step 1-9. Disconnect PUSAI1 at this time, and this voltage will be stored across the capacitor Cs; 步骤1-10.再将PUSAI2、RST_P闭合,VP＝VCM；Step 1-10. Close PUSAI2 and RST_P again, VP=VCM; 步骤1-11.接着将RST_P断开，RST_CA闭合，VEX下降至VL，这时VCA的电压变化为-(ΔVEX+ΔVout)，此时单端转双端输出模块的输出端VP将会输出电压VCM+(ΔVEX+ΔVout)，因此单端转双端输出模块输出以VCM电压为中心的双端电压，并且电压差值为VP-VN＝2(ΔVEX+ΔVout)，上述的电压差值VP-VN为剩余电压。Step 1-11. Then disconnect RST_P, close RST_CA, and VEX drops to VL. At this time, the voltage of VCA changes to -(ΔVEX+ΔVout). At this time, the output terminal VP of the single-ended to double-ended output module will output voltage VCM+(ΔVEX+ΔVout), so the single-ended to double-ended output module outputs the double-ended voltage centered on the VCM voltage, and the voltage difference is VP-VN=2(ΔVEX+ΔVout), the above-mentioned voltage difference VP-VN is the residual voltage.
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电流型PWM DC-DC升压转换器的稳定性分析与实现;郑朝霞 等;《微电子学与计算机》;20061231;第229-232页 *

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