CN112881775A - Low-power-consumption high-resolution capacitance measuring circuit - Google Patents

Low-power-consumption high-resolution capacitance measuring circuit Download PDF

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CN112881775A
CN112881775A CN202110042598.0A CN202110042598A CN112881775A CN 112881775 A CN112881775 A CN 112881775A CN 202110042598 A CN202110042598 A CN 202110042598A CN 112881775 A CN112881775 A CN 112881775A
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mos transistor
output
capacitor
voltage
mos
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CN112881775B (en
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简明朝
郭春炳
孔祥键
陆维立
杨德旺
高钧达
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Guangdong University of Technology
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Guangdong University of Technology
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices

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Abstract

The invention discloses a low-power-consumption high-resolution capacitance measuring circuit, which comprises an analog front end module and a digital-to-analog converter, wherein: one end of the capacitor to be tested is grounded, and the other end of the capacitor to be tested is connected to the analog front-end module through a switch; the analog front-end module comprises an input stage, an amplification stage and an output stage, when the switch is closed, the input stage converts a capacitor to be detected into corresponding linear output voltage through capacitor voltage division, and the linear output voltage passes through the amplification stage to improve the voltage output swing and is transmitted to the output stage through a current mirror technology; and storing the voltage value output by the output stage on an output capacitor, and converting the voltage value into a digital signal through the digital-to-analog converter and outputting the digital signal. The invention adopts the capacitance voltage division-current mirror adjustment technology to detect the size change of the measured capacitance, has the characteristic of high resolution, and has the advantages of low power consumption, simple structure, easy realization and full integration.

Description

Low-power-consumption high-resolution capacitance measuring circuit
Technical Field
The invention relates to the technical field of analog front-end integrated circuits, in particular to a low-power-consumption high-resolution capacitance measuring circuit (CDC) which is used for converting the size of a Capacitor to be measured into a Digital signal and outputting the Digital signal.
Background
Capacitance is one of the important physical parameters in electricity, and capacitance measurement circuits are widely used in scientific and industrial applications, such as capacitive-inductive touch screens; when a finger touches the screen, the touch screen controller determines the position of the touch object by sensing the size change of the self capacitance or the mutual capacitance on the touch screen.
The capacitance measuring circuit at the present stage comprises an alternating current bridge method and alternating current phase-locked amplification, wherein alternating current excitation is adopted in the alternating current bridge-based method, and then the ADC is used for demodulating and digitizing the output of the bridge so as to obtain digital output corresponding to capacitance change, so that the stability is good, the influence of parasitic capacitance is small, but the method needs an operational amplifier with high impedance and low temperature drift, so that the requirements on process conditions are high, the integration is difficult, and the measurement error is large. The alternating current phase-locked amplifying capacitor measuring circuit has low temperature drift and high signal-to-noise ratio, but has complex circuit, large power consumption, higher cost, still needs to improve the anti-impurity property and can only reach nF level in resolution.
Disclosure of Invention
The invention aims to provide a low-power-consumption high-resolution capacitance measuring circuit which is used for solving the problems of high circuit power consumption, low resolution and complex circuit of the existing capacitance measuring circuit.
In order to realize the task, the invention adopts the following technical scheme:
a low power consumption high resolution capacitance measurement circuit comprising an analog front end module and a digital to analog converter, wherein:
one end of the capacitor Cx to be tested is grounded, and the other end of the capacitor Cx to be tested is connected to the analog front-end module through a switch S1;
the analog front-end module comprises an input stage, an amplification stage and an output stage, when the switch S1 is closed, the input stage converts a capacitor Cx to be detected into a corresponding linear output voltage through capacitance voltage division, and the linear output voltage passes through the amplification stage to increase the voltage output swing and is then transmitted to the output stage through a current mirror technology; and storing the voltage value output by the output stage on an output capacitor, and converting the voltage value into a digital signal through the digital-to-analog converter and outputting the digital signal.
Further, the capacitance measuring circuit further comprises a low dropout linear regulator;
the low dropout regulator is respectively connected with the analog front end module and the digital-to-analog converter and is used for providing stable working voltage for the analog front end module and the digital-to-analog converter so as to enable the analog front end module and the digital-to-analog converter to be suitable for working under different external power supply voltages.
Further, the input stage comprises a capacitance CinitialThe MOS transistor comprises a capacitor C1, a transmission gate TG1, a transmission gate TG2, a transmission gate TG3, a MOS transistor M1 and a MOS transistor M2; wherein:
the upper polar plate of the capacitor Cx to be measured is grounded, and the lower polar plate is connected to a voltage node X in the input stage through a switch S1; capacitor CinitialAnd the upper plate of the capacitor C1 is connected with the voltage nodes X and CinitialThe lower polar plate of the C1 is connected with the drain electrode of the MOS tube M1 and the source electrode of the MOS tube M2; the source electrode of the MOS transistor M1 is connected with the ground, and the drain electrode of the MOS transistor M2 is connected with a voltage source VR; the gates of the MOS transistor M1 and the MOS transistor M2 are connected with a control signal CLK 1; the transmission gate TG1 is connected with the voltage node X and the ground, the transmission gate TG2 is connected with the output V1 and the reference voltage Vref, and the transmission gate TG3 is connected with the voltage node X and the output V1; the control signals of the transmission gate TG1 and the transmission gate TG2 are CLK1, and the control signal of the transmission gate TG3 is CLK 2.
Further, the working process of the input stage is as follows:
when CLK1 is high, CLK2 is low, MOS transistor M2 and transmission gate TG3 are turned off, MOS transistor M1, transmission gate TG1 and transmission gate TG2 are turned on, and capacitor C1 and capacitor C are connectedInitialThe upper and lower stages of the circuit are pulled down to GND, the voltage node X is pulled to ground through a transmission gate TG1, and the output V1 is pulled to a reference voltage Vref through a transmission gate TG 2;
when the CLK2 is low, the CLK1 is high, the MOS transistor M1, the transmission gate TG1 and the transmission gate TG2 are cut off, the MOS transistor M2 and the transmission gate TG3 are turned on, and the lower plate of the capacitor C1 is switched from the GND to the VR; when different capacitances Cx to be measured are connected, linear output voltages which change linearly based on different capacitance values can be obtained at the output end through capacitance voltage division.
Further, the amplifier stage comprises a current source I1, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, a MOS transistor M7, a MOS transistor M8, a MOS transistor M9, a MOS transistor M10, a MOS transistor M11, a MOS transistor M12, a transmission gate TG4, and a capacitor Cp, wherein:
the current source I1 is connected with the drain electrode of the MOS tube M11; the grid and the drain of the MOS transistor M11 are connected with the grid of the MOS transistor M12, and the source of the MOS transistor M11 is connected with the source of the MOS transistor M12; the sources of the MOS transistors M3 and M4 are connected with the drain of the MOS transistor M12; the drains of the MOS tubes M3 and M4 are respectively connected with the drains and gates of the MOS tubes M5 and M6; the drain electrode of the MOS transistor M5 is connected with the gate electrode of the MOS transistor M9; the drain electrode of the MOS transistor M6 is connected with the gate electrode of the M110; the source electrode of the MOS transistor M5 is connected with the source electrode of the MOS transistor M6, the grid electrode of the MOS transistor M4, namely a voltage node INP, is connected with the drain electrode of the MOS transistor M6 through a transmission gate TG4 and is connected with the upper plate of a capacitor Cp, and the lower plate of the capacitor Cp is connected with a reference voltage Vref; the drain electrode of the MOS tube M9 is connected with the drain electrode and the grid electrode of the MOS tube M7; the grid electrode of the MOS tube M7 is connected with the grid electrode of the MOS tube M8; the drain electrode of the MOS transistor M110 and the drain electrode of the MOS transistor M8 are connected with the output V2; the gate of the MOS transistor M3, i.e., the input port INN, is connected to the output V1 of the input stage.
Further, the working process of the amplification stage is as follows:
when CLK1 is high, transmission gate TG4 is turned on, the amplifier stage acts as a unity gain amplifier, and output V2 follows input INN;
when the CLK1 is at low level, the transmission gate TG4 is turned off, the gate of the MOS transistor M4, i.e., the positive input terminal of the amplifier stage, is connected to the upper stage of the capacitor Cp, and the holding voltage is Vref; when the negative input end INN of the amplification stage changes, a basic amplifier composed of MOS tubes M12, M3, M4, M5 and M6 amplifies the tiny voltage change of the negative input end, and the voltage of the drain electrode of the MOS tube M6 is copied to an output V2 through a current mirror composed of MOS tubes M7, M8, M9 and M10, and the output of the output V2 can reach the output range of 0-VDD.
Further, the output stage includes a capacitor C2, a capacitor C3, a capacitor C4, a MOS transistor M13, a MOS transistor M14, a MOS transistor M15, a MOS transistor M16, a MOS transistor M17, a MOS transistor M18, a MOS transistor M19, a MOS transistor M20, and a transmission gate TG5, where:
the upper plate of the capacitor C2 and the lower plate of the capacitor C3 are connected with the input port IN; the upper plate of the capacitor C2 is connected with the gates of the MOS tube M13 and the MOS tube M14, the sources of the MOS tube M13 and the MOS tube M14 are connected, and the drain of the MOS tube M14 is connected with the source of the MOS tube M16; the lower polar plate of the capacitor C3 is connected with the grids of the MOS tube M19 and the MOS tube M20; the grid of the MOS transistor M15 is connected with the grid of the MOS transistor M16 and connected with a control signal CLK 3-; the source electrode of the MOS transistor M15 is connected with the drain electrode of the MOS transistor M13, and the drain electrode of the MOS transistor M15 is connected with the drain electrode of the MOS transistor M17; the grid electrode of the MOS transistor M17 is connected with the grid electrode of the MOS transistor M18 and connected with a control signal CLK 3; the source electrode of the MOS tube M17 is connected with the drain electrode of the MOS tube M19, the source electrode of the MOS tube M19 is connected with the source electrode of the MOS tube M20, the drain electrodes of the MOS tube M16 and the MOS tube M18 are connected with the upper plate of the capacitor C4 and the output port OUT, and the lower plate of the capacitor C4 is grounded; the source of the MOS transistor M6 is connected to the drain of the MOS transistor M8, and the output port OUT is connected to the reference voltage Vref through the transmission gate TG 5.
Further, the working process of the output stage is as follows:
when CLK1 is high and CLK3 is low, transmission gate TG5 is turned on to reset output port OUT to Vref, and MOS transistor M15, MOS transistor M16, MOS transistor M17, and MOS transistor M18 are turned on. Capacitors C2 and C3 provide bias to M13, M17, M19, M20;
CLK1 is low, transmission gate TG5 is turned off, at this time, input port IN receives V2 transmitted from the amplifier stage, and is coupled from the amplifier stage to the output stage, and the width-to-length ratio of MOS transistor M14 and MOS transistor M13 is 8 through a current mirror formed by MOS transistor M13, MOS transistor M14, MOS transistor M19, and MOS transistor M20: 1, the width-to-length ratio of the MOS transistor M20 to the MOS transistor M19 is also 8: 1, current is proportionally amplified to an output port through a current mirror to charge a capacitor C4, when the capacitor C4 is stably charged, CKL3 is changed from low level to high level, and an MOS tube M15, an MOS tube M16, an MOS tube M17 and an MOS tube M18 are turned off. The voltage value at the output port at this time is the voltage value stored in the capacitor C4.
Further, the digital-to-analog converter includes a bootstrap switch, a segmented capacitor array, a comparator, and SAR control logic, wherein:
the input of the bootstrap switch is connected with the output port of the analog front-end module, the output port of the bootstrap switch is connected with the input of the DAC of the segmented capacitor array, the output port of the segmented capacitor array is connected with the input of the comparator, the output port of the comparator is connected with the input of the SAR control logic, the SAR control logic is connected with the control switch of the segmented capacitor array, the charging and discharging of the capacitor array are controlled, and meanwhile, a digital code is output;
the input signal is firstly sampled through the bootstrap switch, the voltage value of the input signal is stored in the segmented capacitor array, when the segmented capacitor array keeps the sampling voltage stable, the comparator starts to compare the output of the segmented capacitor array under the control of the control signal Clkc, the SAR control logic adjusts the reference voltage output next time by the segmented capacitor array according to the output of the comparator, at the same time, the digital code of the comparison result is output, and the process is repeated until all conversion is completed.
Further, the low dropout regulator comprises a reference voltage source V provided by an external power supplyBATError amplifier, power stage device MPT, resistance R1, resistance R2, resistance RL and off-chip capacitor CL, wherein:
the negative input end of the error amplifier is connected with a reference voltage Vref, and the positive input end of the error amplifier is connected with a voltage node Y; the output of the error amplifier is connected with the grid of the power stage device MPT and a reference voltage source VBATThe source electrode of the error amplifier and the power level device MPT are connected, the drain electrode of the power level device MPT is connected with the resistor R1, the resistor RL and the off-chip capacitor CL, one end of the resistor R2 is connected with a voltage node, and the other end of the resistor R2 is grounded;
the feedback voltage Y is added at the positive phase input end of the error amplifier and compared with the reference voltage Vref added at the negative input end, the difference value of the two is amplified by the error amplifier, the grid voltage of the power level device MPT is controlled, and the voltage drop on the resistors R1 and R2 is further adjusted, so that the output voltage Vout is stabilized; when the output voltage Vout is lowered, the difference between the voltage node Y and the reference voltage Vref increases, the voltage output by the error amplifier increases, and the MTP driving current of the power stage device increases, so that the output voltage Vout is raised, and the output voltage Vout is stabilized.
Compared with the prior art, the invention has the following technical characteristics:
1. the front-end analog circuit of the invention adopts a charge-current mirror adjustment technology to detect the size of the measured capacitor, the bias of the current mirror is dynamically biased by using clock signals of different time sequences, static high power consumption does not exist, and the ADC module adopts dynamic SAR logic, a dynamic comparator and an asynchronous time sequence technology and has the advantage of low power consumption, so that the capacitor measuring circuit has the advantage of low power consumption.
2. The minimum capacitance value measurable by the invention is 1fF, the measurement range is 0-1 pF, and the device has the advantages of high resolution and wide dynamic range.
3. The circuit of the invention has simple structure, is easy to realize, integrates the low dropout regulator and has the advantage of full integration.
Drawings
FIG. 1 is a block diagram of capacitance measurement circuitry of the present invention;
FIG. 2 is a schematic block diagram of an AFE;
FIG. 3 is a schematic diagram of an AFE input stage circuit;
FIG. 4 is a schematic diagram of an AFE amplifier stage circuit;
FIG. 5 is a schematic diagram of an AFE output stage circuit;
FIG. 6 is a schematic diagram of the overall architecture of the ADC;
FIG. 7 is a diagram of a basic topology of LDO;
FIG. 8 is a schematic diagram of a capacitance measurement circuit;
FIG. 9 is a circuit for testing the performance of a capacitance measuring circuit;
FIG. 10 is a capacitance measurement circuit resolution simulation (front end analog output voltage waveform);
FIG. 11 is a capacitance measurement circuit resolution simulation (ideal DAC output voltage waveform);
FIG. 12 is a capacitance measurement circuit range simulation (front end analog output voltage waveform);
FIG. 13 is a capacitance measurement circuit range simulation (ideal DAC output voltage waveform);
fig. 14 shows the transient current of the power supply.
Detailed Description
The invention provides a simple front-end analog circuit, which adopts a capacitance voltage division-current mirror adjustment technology to detect the size change of a measured capacitor and has the characteristic of high resolution; then, an SAR (SAR) ADC (synthetic aperture radar) is adopted to output a digital signal corresponding to the capacitance change, and the SAR ADC adopts dynamic SAR logic, a dynamic comparator and an asynchronous time sequence technology, so that the power consumption is lower; the circuit of the invention has the advantages of simple structure, easy realization and full integration. Finally, the invention realizes that the power consumption is only 1.1798mW, and the measurement resolution can reach fF level.
Referring to fig. 1, the low power consumption and high resolution capacitance measuring circuit of the present invention includes three sub-modules, which are an Analog Front End (AFE) module, an Analog to Digital Converter (ADC) and a low dropout regulator (LDO), respectively. The LDO provides stable operating voltages for the ADE and ADC modules to enable them to adapt to operate at different external supply voltages. When the switch S1 is closed, the input stage of the AFE converts the capacitance Cx to be measured into a corresponding linear output voltage through capacitance voltage division, the linear output voltage passes through the amplification stage of the AFE, i.e., a simple rail-to-rail single-stage amplifier, to increase its voltage output swing, the voltage is transmitted to the output stage of the AFE through the current mirror technology, the obtained voltage value is stored on the output capacitor, and the voltage value is quantized into a 12-bit digital signal by the ADC module and then output, thereby realizing the conversion of the capacitance to be measured into a digital signal for output. The three submodules of the present invention are described in further detail below.
1. Analog front end module AFE
As shown in fig. 2, the AFE is divided into three parts: input stage, amplifier stage, output stage. The input stage is connected with a capacitor C1 to be charged and an internal fixed capacitor CInitialAnd initializing, and discharging the upper and lower electrode plates to GND. In the testing stage, the capacitor to be tested is connected, meanwhile, the lower polar plate of the C1 is switched from the ground to the VDD, the capacitor Cx to be tested is converted into corresponding linear output voltage through capacitor voltage division, and the voltage which is in a linear function relation with the capacitor to be tested can be obtained at the output end. Different voltages at the output end are amplified through a rail-to-rail single-stage amplifier to obtain a larger dynamic range, and then the voltages are transmitted to the output stage in a current mode to charge a capacitor and discharge electricityThe voltage value is stored on the capacitor.
The schematic diagram of the input stage circuit of the AFE designed according to the principle of AFE is shown in FIG. 3: the input stage circuit comprises a capacitor CinitialThe MOS transistor comprises a capacitor C1, a transmission gate TG1, a transmission gate TG2, a transmission gate TG3, a MOS transistor M1 and a MOS transistor M2. The lower polar plate of the capacitor Cx to be measured is connected to a voltage node X through a switch S1, and the upper polar plate is connected to the ground; capacitor CinitialAnd C1 upper plate connected to voltage nodes X, CinitialThe lower polar plate of the C1 is connected with the drain electrode of the MOS tube M1 and the source electrode of the MOS tube M2; the source electrode of the MOS transistor M1 is connected with the ground, and the drain electrode of the MOS transistor M2 is connected with a voltage source VR; the gates of the MOS transistor M1 and the MOS transistor M2 are connected with a control signal CLK 1; TG1 connects voltage node X to ground, TG2 connects output V1 to reference voltage Vref, TG3 connects voltage node X to output V1; the control signals of the transmission gate TG1 and the transmission gate TG2 are CLK1, and the control signal of the transmission gate TG3 is CLK 2.
The working process of the input stage circuit is as follows: when the CLK1 is high, the CLK2 is low, the MOS transistor M2 is turned off, the transmission gate TG3 is turned off, the MOS transistor M1, the transmission gate TG1 and the transmission gate TG2 are turned on, and the capacitor C1 to be charged and the internal fixed capacitor C3583 are connectedInitialThe upper and lower plates of (2) are pulled down to GND, the voltage node X is pulled to ground through transmission gate TG1, and the output V1 is pulled to Vref through transmission gate TG 2. When CLK2 is low, CLK1 is high, MOS transistor M1, transmission gate TG1 and transmission gate TG2 are turned off, MOS transistor M2 and transmission gate TG3 are turned on, and the lower plate of capacitor C1 is switched from GND to VR. When different capacitances Cx to be measured are connected, linear output voltages which change linearly based on different capacitance values can be obtained at the output end through capacitance voltage division.
Considering the amplification factor and the output dynamic range comprehensively, the amplifier stage is designed as a rail-to-rail double-end input single-end output amplifier, as shown in fig. 4, the amplifier stage circuit comprises a current source I1, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, a MOS transistor M7, a MOS transistor M8, a MOS transistor M9, a MOS transistor M10, a MOS transistor M11, a MOS transistor M12, a transmission gate TG4 and a capacitor Cp; the current source I1 is connected with the drain electrode of the MOS tube M11; the grid and the drain of the MOS transistor M11 are connected with the grid of the MOS transistor M12, and the source of the MOS transistor M11 is connected with the source of the MOS transistor M12; the sources of the MOS transistors M3 and M4 are connected with the drain of the MOS transistor M12; the drains of the MOS tubes M3 and M4 are respectively connected with the drains and gates of the MOS tubes M5 and M6; the drain electrode of the MOS transistor M5 is connected with the gate electrode of the MOS transistor M9; the drain electrode of the MOS transistor M6 is connected with the gate electrode of the MOS transistor M10; the source electrode of the MOS transistor M5 is connected with the source electrode of the MOS transistor M6, the grid electrode of the MOS transistor M4, namely a voltage node INP, is connected with the drain electrode of the MOS transistor M6 through a transmission gate TG4 and is connected with the upper plate of a capacitor Cp, and the lower plate of the capacitor Cp is connected with a reference voltage Vref; the drain electrode of the MOS tube M9 is connected with the drain electrode and the grid electrode of the MOS tube M7; the grid electrode of the MOS tube M7 is connected with the grid electrode of the MOS tube M8; the drain electrode of the MOS tube M10 and the drain electrode of the MOS tube M8 are connected with the output V2; the gate of the MOS transistor M3, i.e., the input port INN, is connected to the output V1 of the input stage.
The working process of the amplifier stage circuit is as follows: when CLK1 is high, transmission gate TG4 is turned on, the amplifier stage acts as a unity gain amplifier, and the output V2 follows the input INN. When CLK1 is low, transmission gate TG4 is turned off, and the gate of MOS transistor M4, i.e., the positive input terminal of the amplifier stage, is connected to the upper stage of capacitor Cp, and the holding voltage is Vref. When the negative input end INN of the amplification stage changes, the basic amplifier composed of the MOS tubes M12, M3, M4, M5 and M6 amplifies the tiny voltage change of the negative input end, and the voltage of the drain electrode of the MOS tube M6 is copied to the output V2 through the current mirror composed of the MOS tubes M7, M8, M9 and M10, so that the output can reach the output range of 0-VDD, and the better amplification performance can be achieved.
In order to realize the voltage-to-current conversion, the output stage amplifier needs to be in the form of a current mirror, and in order to adapt to the wide dynamic requirements of the output stage, the circuit principle is designed as shown in fig. 5. The output stage circuit comprises a capacitor C2, a capacitor C3, a capacitor C4, a MOS tube M13, a MOS tube M14, a MOS tube M15, a MOS tube M16, a MOS tube M17, a MOS tube M18, a MOS tube M19, a MOS tube M20 and a transmission gate TG 5. Wherein: the upper plate of the capacitor C2 and the lower plate of the capacitor C3 are connected with the input port IN; the upper plate of the capacitor C2 is connected with the gates of the MOS tube M13 and the MOS tube M14, the sources of the MOS tube M13 and the MOS tube M14 are connected, and the drain of the MOS tube M14 is connected with the source of the MOS tube M16; the lower polar plate of the capacitor C3 is connected with the grids of the MOS tube M19 and the MOS tube M20; the grid of the MOS transistor M15 is connected with the grid of the MOS transistor M16 and connected with a control signal CLK 3-; the source electrode of the MOS transistor M15 is connected with the drain electrode of the MOS transistor M13, and the drain electrode of the MOS transistor M15 is connected with the drain electrode of the MOS transistor M17; the grid electrode of the MOS transistor M17 is connected with the grid electrode of the MOS transistor M18 and connected with a control signal CLK 3; the source electrode of the MOS tube M17 is connected with the drain electrode of the MOS tube M19, the source electrode of the MOS tube M19 is connected with the source electrode of the MOS tube M20, the drain electrodes of the MOS tube M16 and the MOS tube M18 are connected with the upper plate of the capacitor C4 and the output port OUT, and the lower plate of the capacitor C4 is grounded; the source of the MOS transistor M6 is connected to the drain of the MOS transistor M8, and the output port OUT is connected to the reference voltage Vref through the transmission gate TG 5.
The working process of the output stage circuit is as follows: when CLK1 is high and CLK3 is low, transmission gate TG5 is turned on to reset output port OUT to Vref, and MOS transistor M15, MOS transistor M16, MOS transistor M17, and MOS transistor M18 are turned on. Capacitors C2 and C3 provide bias to M13, M17, M19, M20. CLK1 is low, transmission gate TG5 is turned off, at this time, input port IN receives V2 transmitted from the amplifier stage, and is coupled from the amplifier stage to the output stage, and the width-to-length ratio of MOS transistor M14 and MOS transistor M13 is 8 through a current mirror formed by MOS transistor M13, MOS transistor M14, MOS transistor M19, and MOS transistor M20: 1, the width-to-length ratio of the MOS transistor M20 to the MOS transistor M19 is also 8: 1, current is proportionally amplified to an output port through a current mirror to charge a capacitor C4, when the capacitor C4 is stably charged, CKL3 is changed from low level to high level, and an MOS tube M15, an MOS tube M16, an MOS tube M17 and an MOS tube M18 are turned off. The voltage value at the output port at this time is the voltage value stored in the capacitor C4.
The overall working process of the analog front end module AFE is as follows: the AFE operation process can be divided into a reset phase and a test phase, and the input stage of the test phase is provided with a capacitor C1 to be charged and an internal fixed capacitor CInitialAnd initializing, namely discharging the upper and lower plates of the amplifier to GND, resetting the output port of the input stage to Vref, transferring the Vref to the input port INN of the amplifier stage, and enabling the output V2 of the amplifier stage to follow the voltage value of the input INN. At this time, the output stage output port OUT is reset to Vref. In the testing stage, a capacitor Cx to be tested is connected, the lower polar plate of the C1 is switched from the ground to the VR, the capacitor Cx to be tested is converted into corresponding linear output voltage through capacitor voltage division, and the voltage which is in a linear function relation with the capacitor to be tested can be obtained at the output end V1 of the input stage. After different voltages at the output end pass through the amplifying stage, the voltage difference is amplified to obtain a larger dynamic range, then the voltage is transmitted to the output stage in a current mode to charge the capacitor and store the voltage value in the output stageOn the capacitor.
ADC module
The ADC module adopted in the present invention is an SAR ADC architecture having a low power consumption advantage, and as shown in fig. 7, the main circuit is composed of a bootstrap switch, a segmented capacitor array, a comparator, and an SAR control logic. The input of the bootstrap switch is connected with the output port of the AFE, the output port of the bootstrap switch is connected with the input of the DAC of the segmented capacitor array, the output port of the segmented capacitor array is connected with the input of the comparator, the output port of the comparator is connected with the input of the SAR control logic, the SAR control logic is connected with the control switch of the segmented capacitor array, the charging and discharging of the capacitor array are controlled, and meanwhile, a digital code is output.
The overall working process of the ADC module is as follows:
the input signal is firstly sampled through the bootstrap switch, the voltage value of the input signal is stored in the segmented capacitor array, when the segmented capacitor array keeps the sampling voltage stable, the comparator starts to compare the output of the segmented capacitor array under the control of the control signal Clkc, the SAR control logic adjusts the reference voltage output next time by the segmented capacitor array according to the output of the comparator, at the same time, the digital code of the comparison result is output, and the process is repeated until all conversion is completed.
3. Low dropout linear regulator (LDO)
FIG. 7 shows a basic topology of LDO, including a reference voltage source V provided by an external power supplyBATError amplifier, power stage MPT, resistance R1, resistance R2, resistance RL and off-chip capacitor CL.
The negative input end of the error amplifier is connected with a reference voltage Vref, and the positive input end of the error amplifier is connected with a voltage node Y; the output of the error amplifier is connected with the grid of the power stage device MPT and a reference voltage source VBATConnecting the error amplifier and the MPT source electrode; the drain electrode of the power level device MPT is connected with the resistor R1, the resistor RL and the off-chip capacitor CL; resistor R2 has one end connected to the voltage node and one end connected to ground.
The basic working principle of the LDO is that a feedback voltage Y is applied to the positive input terminal of an error amplifier, and compared with a reference voltage Vref applied to the negative input terminal, the difference between the positive input terminal and the negative input terminal is amplified by the error amplifier, and then the gate voltage of a power stage device is controlled, and further, voltage drops across resistors R1 and R2 are adjusted, thereby stabilizing an output voltage Vout. When the output voltage Vout is lowered, the difference between the voltage node Y and the reference voltage Vref increases, the voltage output by the error amplifier increases, and the MTP driving current of the power stage device increases, so that the output voltage Vout is raised, and the output voltage Vout is stabilized. The LDC can suppress the noise of the external power supply and provide stable working voltage to ensure that the LDC can adapt to work under different external power supply voltages.
The capacitance measuring circuit provided by the invention can convert the size of the capacitor to be measured into a digital signal to be output. When the switch S1 is closed, the AFE converts the capacitor Cx to be measured into corresponding linear output voltage through capacitance voltage division, the linearly changing voltage is increased in voltage output swing amplitude through a simple rail-to-rail single-stage amplifier, the voltage is transmitted to an output stage through a current mirror technology, the obtained voltage value is stored on the output capacitor, the voltage value is quantized into 12bit digital signals by the ADC and then output, and therefore the purpose that the size of the capacitor to be measured is converted into the digital signals to be output is achieved.
Based on the above circuit structure provided by the present invention, the measurement method of the capacitance measurement circuit of the present invention is:
after the capacitance detection circuit is powered on, a low dropout regulator (LDO) converts an external power supply voltage into a stable reference voltage source required by an AFE and an ADC, at the moment, a front-end analog circuit AFE begins to reset, CLK1 is high level CLK2 is low level for an input stage of the AFE, a MOS tube M2 is cut off, a transmission gate TG3 is cut off, a MOS tube M1, a transmission gate TG1 and a transmission gate TG2 are conducted, and a capacitor C1 to be charged and an internal fixed capacitor C2 are conductedInitialThe upper and lower plates of (2) are pulled down to GND, the voltage node X is pulled to ground through transmission gate TG1, and the output V1 is pulled to Vref through transmission gate TG 2. For the AFE amplifier stage CLK1 is high, transmission gate TG4 is on, the amplifier is connected as a unity gain amplifier, and the output V2 follows the input INN. For the AFE output stage, when CLK1 is high and CLK3 is low, transfer gate TG5 is turned on to reset the output port to Vref, and MOS transistor M15, MOS transistor M16, MOS transistor M17, and MOS transistor M18 are turned on. Capacitors C2 and C3 provide bias for M13, M14, M19, M20And (4) placing. At the same time, the ADC is also in the reset phase, and the digital code output is 0.
When the switch S1 is closed, the AFE is in a test phase, and for the AFE input stage, CLK2 is low, CLK1 is high, MOS transistor M1, transmission gate TG1 and transmission gate TG2 are turned off, MOS transistor M2 is turned off and transmission gate TG3 is turned off, and the bottom plate of the capacitor C1 is switched from GND to VR. And the voltage value of the capacitor Cx to be measured can be obtained at the output end through the voltage division of the capacitor. For the AFE amplifier stage, CLK1 is low, transmission gate TG4 is off, the gate of MOS transistor M4, i.e., the positive input of the amplifier, is connected to the capacitor Cp upper stage, and the holding voltage is Vref. The basic amplifier composed of the MOS tubes M12, M3, M4, M5 and M6 amplifies the voltage difference between the negative input end and the positive input end and outputs the amplified voltage, and the voltage of the drain of the MOS tube M6 is copied to the output V2 through the current mirror composed of the MOS tubes M7, M8, M9 and M10. For the AFE output stage, CLK1 is low, transmission gate TG5 is turned off, and at this time, the input port receives V2 transmitted from the amplifier stage, and the input port is coupled from the amplifier stage to the output stage, and through a current mirror formed by MOS transistor M13, MOS transistor M14, MOS transistor M19, and MOS transistor M20, the width-to-length ratio of MOS transistor M14 and MOS transistor M13 is 8: 1, the width-to-length ratio of the MOS transistor M20 to the MOS transistor M19 is also 8: 1, current is proportionally amplified to an output port through a current mirror to charge a capacitor C4, when the capacitor C4 is stably charged, CKL3 is changed from low level to high level, and an MOS tube M15, an MOS tube M16, an MOS tube M17 and an MOS tube M18 are turned off. The voltage value at the output port at this time is the voltage value stored in the capacitor C4. At this time, the ADC samples the voltage value stored in the capacitor C4 through the bootstrap switch, quantizes the voltage value into a 12-bit digital signal, and outputs the digital signal, thereby converting the size of the capacitor to be measured into a digital signal and outputting the digital signal.
Example (b):
the invention uses Cadence software to carry out circuit design and simulation, adopts a TSMC 180nm CMOS process, designs a capacitance measuring circuit schematic diagram as shown in figure 7, and comprises a control logic circuit, a low-dropout linear regulator, a front-end analog circuit, an analog-to-digital converter and a buffer, wherein the buffer is connected between the front-end analog circuit and the analog-to-digital converter, and the load driving capability of the front-end analog circuit is improved.
The performance test circuit of the capacitance measurement circuit is shown in fig. 8, the power supply voltage is 3.3V, the test capacitor outputs a digital signal corresponding to the capacitance after passing through the capacitance measurement circuit, and then an ideal digital-to-analog converter restores the analog signal, so that the change of the digital code output by the capacitance measurement circuit when different capacitance values are measured can be visually seen.
The resolution simulation test is performed on the capacitance measuring circuit, the parameter scanning is performed on the capacitance to be measured, the capacitance to be measured is set to change from 1fF to 10fF in steps with the precision of 1fF, and the output voltages corresponding to the analog front end when different capacitance values are measured are as shown in FIG. 9.
It can be seen that the output of the analog front end presents very good linearity, and the output voltage of the analog front end changes by 0.9mV when the capacitance to be detected changes by 1 fF. The minimum resolution of the subsequent SAR ADC can be met, and the digital signal is output after the SAR ADC is quantized. The test module returns an analog signal through the ideal digital-to-analog converter, the output of the ideal digital-to-analog converter is shown in fig. 10, the capacitance measuring circuit can detect the variable quantity of each 1fF of the tested capacitance and output different values, and therefore the resolution of the capacitance measuring circuit designed by the invention can reach 1 fF.
The method comprises the steps of testing a measurement range of a capacitance measurement circuit, scanning parameters of a capacitor to be measured, setting linear change of the capacitor to be measured from 1fF to 1pF, and setting the total simulation step number to be 11. The measured output voltages of the different capacitance values corresponding to the analog front end are shown in fig. 11. For the capacitor to be measured with the capacitance value variation range within 1pF, the output of the analog front end still has good linearity. The output of the ideal digital-to-analog converter is shown in fig. 12, and it can be seen that the capacitance measuring circuit can measure the change of the capacitance to be measured from the minimum value 1fF to the maximum value 1pF, and output the value corresponding to the capacitance size, therefore, the capacitance measuring circuit of the present invention has the capacitance measuring range of 1 pF.
And (3) carrying out power consumption test on the capacitance measuring circuit, and carrying out transient simulation on the capacitance measuring circuit at the power supply voltage of 3.3V and the clock period of 4us, wherein the simulation time is 40us and 10 measuring periods are carried out. As shown in fig. 13, the transient current obtained from the power supply voltage is calculated to be 357.5uA, so that the average power consumption of the capacitance measuring circuit of the present invention is only 1.1798mW, which has the advantage of low power consumption.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. A low power consumption high resolution capacitance measuring circuit comprising an analog front end module and a digital to analog converter, wherein:
one end of the capacitor Cx to be tested is grounded, and the other end of the capacitor Cx to be tested is connected to the analog front-end module through a switch S1;
the analog front-end module comprises an input stage, an amplification stage and an output stage, when the switch S1 is closed, the input stage converts a capacitor Cx to be detected into a corresponding linear output voltage through capacitance voltage division, and the linear output voltage passes through the amplification stage to increase the voltage output swing and is then transmitted to the output stage through a current mirror technology; and storing the voltage value output by the output stage on an output capacitor, and converting the voltage value into a digital signal through the digital-to-analog converter and outputting the digital signal.
2. The low power consumption high resolution capacitance measuring circuit of claim 1, further comprising a low dropout linear regulator;
the low dropout regulator is respectively connected with the analog front end module and the digital-to-analog converter and is used for providing stable working voltage for the analog front end module and the digital-to-analog converter so as to enable the analog front end module and the digital-to-analog converter to be suitable for working under different external power supply voltages.
3. The low power consumption high resolution capacitance measurement circuit of claim 1, wherein the input stage comprises a capacitance CinitialCapacitor C1 and transmission gateTG1, transmission gate TG2, transmission gate TG3, MOS tube M1 and MOS tube M2; wherein:
the upper polar plate of the capacitor Cx to be measured is grounded, and the lower polar plate is connected to a voltage node X in the input stage through a switch S1; capacitor CinitialAnd the upper plate of the capacitor C1 is connected with the voltage nodes X and CinitialThe lower polar plate of the C1 is connected with the drain electrode of the MOS tube M1 and the source electrode of the MOS tube M2; the source electrode of the MOS transistor M1 is connected with the ground, and the drain electrode of the MOS transistor M2 is connected with a voltage source VR; the gates of the MOS transistor M1 and the MOS transistor M2 are connected with a control signal CLK 1; the transmission gate TG1 is connected with the voltage node X and the ground, the transmission gate TG2 is connected with the output V1 and the reference voltage Vref, and the transmission gate TG3 is connected with the voltage node X and the output V1; the control signals of the transmission gate TG1 and the transmission gate TG2 are CLK1, and the control signal of the transmission gate TG3 is CLK 2.
4. The low-power consumption high-resolution capacitance measuring circuit according to claim 3, wherein the input stage operates by:
when CLK1 is high, CLK2 is low, MOS transistor M2 and transmission gate TG3 are turned off, MOS transistor M1, transmission gate TG1 and transmission gate TG2 are turned on, and capacitor C1 and capacitor C are connectedInitialThe upper and lower stages of the circuit are pulled down to GND, the voltage node X is pulled to ground through a transmission gate TG1, and the output V1 is pulled to a reference voltage Vref through a transmission gate TG 2;
when the CLK2 is low, the CLK1 is high, the MOS transistor M1, the transmission gate TG1 and the transmission gate TG2 are cut off, the MOS transistor M2 and the transmission gate TG3 are turned on, and the lower plate of the capacitor C1 is switched from the GND to the VR; when different capacitances Cx to be measured are connected, linear output voltages which change linearly based on different capacitance values can be obtained at the output end through capacitance voltage division.
5. The low-power consumption high-resolution capacitance measuring circuit according to claim 1, wherein the amplifier stage comprises a current source I1, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, a MOS transistor M7, a MOS transistor M8, a MOS transistor M9, a MOS transistor M10, a MOS transistor M11, a MOS transistor M12, a transmission gate TG4 and a capacitor Cp, wherein:
the current source I1 is connected with the drain electrode of the MOS tube M11; the grid and the drain of the MOS transistor M11 are connected with the grid of the MOS transistor M12, and the source of the MOS transistor M11 is connected with the source of the MOS transistor M12; the sources of the MOS transistors M3 and M4 are connected with the drain of the MOS transistor M12; the drains of the MOS tubes M3 and M4 are respectively connected with the drains and gates of the MOS tubes M5 and M6; the drain electrode of the MOS transistor M5 is connected with the gate electrode of the MOS transistor M9; the drain electrode of the MOS transistor M6 is connected with the gate electrode of the M110; the source electrode of the MOS transistor M5 is connected with the source electrode of the MOS transistor M6, the grid electrode of the MOS transistor M4, namely a voltage node INP, is connected with the drain electrode of the MOS transistor M6 through a transmission gate TG4 and is connected with the upper plate of a capacitor Cp, and the lower plate of the capacitor Cp is connected with a reference voltage Vref; the drain electrode of the MOS tube M9 is connected with the drain electrode and the grid electrode of the MOS tube M7; the grid electrode of the MOS tube M7 is connected with the grid electrode of the MOS tube M8; the drain electrode of the MOS transistor M110 and the drain electrode of the MOS transistor M8 are connected with the output V2; the gate of the MOS transistor M3, i.e., the input port INN, is connected to the output V1 of the input stage.
6. The low power consumption high resolution capacitance measuring circuit according to claim 5, wherein the amplifier stage operates by:
when CLK1 is high, transmission gate TG4 is turned on, the amplifier stage acts as a unity gain amplifier, and output V2 follows input INN;
when the CLK1 is at low level, the transmission gate TG4 is turned off, the gate of the MOS transistor M4, i.e., the positive input terminal of the amplifier stage, is connected to the upper stage of the capacitor Cp, and the holding voltage is Vref; when the negative input end INN of the amplification stage changes, a basic amplifier composed of MOS tubes M12, M3, M4, M5 and M6 amplifies the tiny voltage change of the negative input end, and the voltage of the drain electrode of the MOS tube M6 is copied to an output V2 through a current mirror composed of MOS tubes M7, M8, M9 and M10, and the output of the output V2 can reach the output range of 0-VDD.
7. The low-power consumption high-resolution capacitance measuring circuit according to claim 1, wherein the output stage comprises a capacitor C2, a capacitor C3, a capacitor C4, a MOS transistor M13, a MOS transistor M14, a MOS transistor M15, a MOS transistor M16, a MOS transistor M17, a MOS transistor M18, a MOS transistor M19, a MOS transistor M20 and a transmission gate TG5, wherein:
the upper plate of the capacitor C2 and the lower plate of the capacitor C3 are connected with the input port IN; the upper plate of the capacitor C2 is connected with the gates of the MOS tube M13 and the MOS tube M14, the sources of the MOS tube M13 and the MOS tube M14 are connected, and the drain of the MOS tube M14 is connected with the source of the MOS tube M16; the lower polar plate of the capacitor C3 is connected with the grids of the MOS tube M19 and the MOS tube M20; the grid of the MOS transistor M15 is connected with the grid of the MOS transistor M16 and connected with a control signal CLK 3-; the source electrode of the MOS transistor M15 is connected with the drain electrode of the MOS transistor M13, and the drain electrode of the MOS transistor M15 is connected with the drain electrode of the MOS transistor M17; the grid electrode of the MOS transistor M17 is connected with the grid electrode of the MOS transistor M18 and connected with a control signal CLK 3; the source electrode of the MOS tube M17 is connected with the drain electrode of the MOS tube M19, the source electrode of the MOS tube M19 is connected with the source electrode of the MOS tube M20, the drain electrodes of the MOS tube M16 and the MOS tube M18 are connected with the upper plate of the capacitor C4 and the output port OUT, and the lower plate of the capacitor C4 is grounded; the source of the MOS transistor M6 is connected to the drain of the MOS transistor M8, and the output port OUT is connected to the reference voltage Vref through the transmission gate TG 5.
8. The low-power consumption high-resolution capacitance measuring circuit according to claim 7, wherein the output stage operates by:
when CLK1 is high and CLK3 is low, transmission gate TG5 is turned on to reset output port OUT to Vref, and MOS transistor M15, MOS transistor M16, MOS transistor M17, and MOS transistor M18 are turned on. Capacitors C2 and C3 provide bias to M13, M17, M19, M20;
CLK1 is low, transmission gate TG5 is turned off, at this time, input port IN receives V2 transmitted from the amplifier stage, and is coupled from the amplifier stage to the output stage, and the width-to-length ratio of MOS transistor M14 and MOS transistor M13 is 8 through a current mirror formed by MOS transistor M13, MOS transistor M14, MOS transistor M19, and MOS transistor M20: 1, the width-to-length ratio of the MOS transistor M20 to the MOS transistor M19 is also 8: 1, current is proportionally amplified to an output port through a current mirror to charge a capacitor C4, when the capacitor C4 is stably charged, CKL3 is changed from low level to high level, and an MOS tube M15, an MOS tube M16, an MOS tube M17 and an MOS tube M18 are turned off. The voltage value at the output port at this time is the voltage value stored in the capacitor C4.
9. The low power consumption high resolution capacitance measurement circuit of claim 1, wherein the digital-to-analog converter comprises a bootstrap switch, a segmented capacitance array, a comparator, and SAR control logic, wherein:
the input of the bootstrap switch is connected with the output port of the analog front-end module, the output port of the bootstrap switch is connected with the input of the DAC of the segmented capacitor array, the output port of the segmented capacitor array is connected with the input of the comparator, the output port of the comparator is connected with the input of the SAR control logic, the SAR control logic is connected with the control switch of the segmented capacitor array, the charging and discharging of the capacitor array are controlled, and meanwhile, a digital code is output;
the input signal is firstly sampled through the bootstrap switch, the voltage value of the input signal is stored in the segmented capacitor array, when the segmented capacitor array keeps the sampling voltage stable, the comparator starts to compare the output of the segmented capacitor array under the control of the control signal Clkc, the SAR control logic adjusts the reference voltage output next time by the segmented capacitor array according to the output of the comparator, at the same time, the digital code of the comparison result is output, and the process is repeated until all conversion is completed.
10. The low power consumption high resolution capacitance measuring circuit according to claim 2, wherein the LDO comprises a reference voltage source V provided by an external power supplyBATError amplifier, power stage device MPT, resistance R1, resistance R2, resistance RL and off-chip capacitor CL, wherein:
the negative input end of the error amplifier is connected with a reference voltage Vref, and the positive input end of the error amplifier is connected with a voltage node Y; the output of the error amplifier is connected with the grid of the power stage device MPT and a reference voltage source VBATThe source electrode of the error amplifier and the power level device MPT are connected, the drain electrode of the power level device MPT is connected with the resistor R1, the resistor RL and the off-chip capacitor CL, one end of the resistor R2 is connected with a voltage node, and the other end of the resistor R2 is grounded;
the feedback voltage Y is added at the positive phase input end of the error amplifier and compared with the reference voltage Vref added at the negative input end, the difference value of the two is amplified by the error amplifier, the grid voltage of the power level device MPT is controlled, and the voltage drop on the resistors R1 and R2 is further adjusted, so that the output voltage Vout is stabilized; when the output voltage Vout is lowered, the difference between the voltage node Y and the reference voltage Vref increases, the voltage output by the error amplifier increases, and the MTP driving current of the power stage device increases, so that the output voltage Vout is raised, and the output voltage Vout is stabilized.
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