CN102297688A - Full-differential capacitance reading circuit for crosswise sampling secondary charge summation - Google Patents

Full-differential capacitance reading circuit for crosswise sampling secondary charge summation Download PDF

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CN102297688A
CN102297688A CN2010102184675A CN201010218467A CN102297688A CN 102297688 A CN102297688 A CN 102297688A CN 2010102184675 A CN2010102184675 A CN 2010102184675A CN 201010218467 A CN201010218467 A CN 201010218467A CN 102297688 A CN102297688 A CN 102297688A
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switch
capacitor
electric charge
switches
integrating capacitor
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吴其松
杨海钢
张翀
尹韬
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Institute of Electronics of CAS
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Institute of Electronics of CAS
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Abstract

The invention relates to a capacitance reading circuit for crosswise sampling secondary charge summation. The circuit has a symmetrical circuit structure and comprises switches 1,2,5 and 6, reference capacitance arrays CR1 and CR2, switches 3,4,7 and 8, switches 9,10,11,12,13,14,15 and 18, capacitors CD1 and CD2, switches 16 and 17, a full-differential trans-conductor operational amplifier, integral capacitors CI1 and CI2, integral capacitors CI3 and CI4 and switches 22 and 23, switches 19,20,21 and 24 and a four-phase non-overlapping clock circuit, wherein the switches 1,2,5 and 6 are used for charging sensor capacitors; the switches 3,4,7 and 8 are used for charging the reference capacitance arrays; the switches 9,10,11,12,13,14,15 and 18 are used for transferring charges; the capacitors CD1 and CD2 are used for eliminating imbalance and restraining low-frequency noises; the switches 16 and 17 are used for supplying direct current working points to the capacitance reading circuit; the integral capacitors CI1 and CI2 are used for storing transferred charges; the integral capacitors CI3 and CI4 and switches 22 and 23 are used for adjusting circuit gains; the switches 19,20,21 and 24 are used for supplying direct current bias to an input end of a full-differential trans-conductor; and the four-phase non-overlapping clock circuit is used for controlling the whole capacitance reading circuit.

Description

A kind of fully differential electric capacity sensing circuit of ALTERNATE SAMPLING electric charge secondary summation
Technical field
The present invention relates to the electric capacity sensing circuit, and relate to the sensing circuit of high-precision condenser type micro-electro-mechanical sensors in more detail, as gyroscope and micro-acceleration gauge etc.
Background technology
Capacitance type sensor is a kind of sensor that is widely used, as capacitance pressure transducer,, accelerometer and gyroscope etc.Capacitance type sensor is differential configuration mostly, so it can equivalence be a pair of difference variable capacitance usually, and its changes in capacitance amount has directly reflected the size of extraneous measured physical quantity.Gyroscope and accelerometer are a kind of inertial sensors that is widely used, and are used to detect the angular velocity and the acceleration of moving object, and they have a wide range of applications in fields such as defense technology, Aero-Space, automotive electronics, Industry Control.Progress along with infotech and micro-fabrication technology, the microminiaturization of sensing system, integrated, the intelligent and networked main trend that has become technical development, volume is little, in light weight because of having for MEMS (micro electro mechanical system) (MEMS) sensor, low price and advantage such as low in energy consumption enjoy favor, it not only is widely used in traditional sensory field, but also be applied in some emerging fields, as intelligent mouse, senior toy, smart mobile phone, medical monitorings etc. have boundless application prospect and market.
MEMS capacitive transducer volume is small, and the signal of its output is very faint, as the scope of body silicon MEMS gyroscopes capacitance variations 10 -18-10 -12The farad magnitude will detect so little capacitance change, and sensing circuit has been proposed very harsh requirement.Because the minimum signal amplitude that sensing system can be surveyed is by the noise decision of sensor and sensing circuit thereof, wherein sensing circuit noise (comprising 1/f noise and thermonoise etc.) accounts for major part, it is the primary factor of restriction sensor precision, therefore explore theory and the method for eliminating and suppressing circuit noise, become the necessary ways and the method that improve capacitive transducer accuracy of detection and resolution; Secondly, because the deviation of manufacturing process, there is mismatch in the difference sensing capacitance, and there is mismatch too in sensing circuit device size parameter, and therefore, its sensing circuit need compensate or suppresses because the error that device mismatch is brought by certain method; In addition, because temperature and Effect of Environmental, parameters such as device parameters, supply voltage and common mode voltage all can produce drift thereupon, and the traditional capacitance sensing circuit is very responsive to temperature drift, and its corresponding temperature-compensation circuit and method are also very complicated, have increased the area and the power consumption of system.
Summary of the invention
The object of the present invention is to provide a kind of fully differential electric capacity sensing circuit of ALTERNATE SAMPLING electric charge secondary summation, to improve the defective that exists in the known technology.
For achieving the above object, the electric capacity sensing circuit of ALTERNATE SAMPLING electric charge secondary summation provided by the invention, the circuit structure for symmetry mainly comprises:
The capacitive transducer of a pair of differential variation has sensor capacitance C S1And C S2
The reference capacitance array C of two adjustable size R1And C R2, and C R1=C R2
The capacitor C that is used to eliminate the sensing circuit imbalance and suppresses low-frequency noise D1And C D2, and C D1=C D2
The integrating capacitor array of the adjustable size of two symmetries is respectively by the integrating capacitor C that is used for the memory transfer electric charge I1And C I2, and the integrating capacitor C that is used for the regulating circuit gain I3With integrating capacitor C I4Form;
A fully differential operational transconductance amplifier;
Wherein:
Sensor capacitance C S1A termination common mode voltage, the other end links to each other with switch 1, switch 2, switch 9 and switch 11, another termination power of switch 1, another termination common port of switch 2; Switch 1 and switch 2 are used to sensor capacitance C S1Charging;
Reference capacitance array C R1A termination common mode voltage, the other end connects an end of switch 3, switch 4 and switch 10, another termination common port of switch 3, another termination power of switch 4, switch 3 and switch 4 are used to reference capacitance array C R1Charging;
The same capacitor C of the other end of switch 9, switch 10 and switch 12 D1An end link to each other;
The same capacitor C of one end of switch 15 and switch 16 D1An end that is connected with the switch 9, switch 10 and the switch 12 that are used for the electric charge transfer is connected, and the other end of switch 16 connects common mode voltage;
Eliminate the capacitor C of imbalance and inhibition low-frequency noise D1The normal phase input end that is connected the fully differential mutual conductance with an end of switch 19;
The other end of switch 15 and switch 19 is connected integrating capacitor C I1With integrating capacitor C I3An end, integrating capacitor C I3The other end connect an end of switch 22, integrating capacitor C I1The other end be connected the reversed-phase output of fully differential operational transconductance amplifier with the other end of switch 22;
Switch 21 is connected across integrating capacitor C I1Two ends;
C S2A termination common mode voltage, the other end links to each other with switch 5, switch 6, switch 12 and switch 14, another termination common port of switch 5, another termination power of switch 6; Switch 5 and switch 6 are used to sensor capacitance C S2Charging;
Reference capacitance array C R2A termination common mode voltage, the other end connects an end of switch 7, switch 8 and switch 13, another termination power of switch 7, another termination common port of switch 8, switch 7 and switch 8 are used to reference capacitance array C R2Charging;
The same capacitor C of the other end of switch 11, switch 13 and switch 14 D2An end link to each other;
The same capacitor C of one end of switch 17 and switch 18 D2An end that is connected with the switch 11, switch 13 and the switch 14 that are used for the electric charge transfer is connected, and the other end of switch 17 connects common mode voltage;
Eliminate the capacitor C of imbalance and inhibition low-frequency noise D2The inverting input that is connected the fully differential mutual conductance with an end of switch 20;
The other end of switch 18 and switch 20 is connected integrating capacitor C I2With integrating capacitor C I4An end, integrating capacitor C I4The other end connect integrating capacitor C with an end of switch 23 I2The positive output end that is connected the fully differential operational transconductance amplifier with the other end of switch 23;
Switch 24 is connected across capacitor C I2Two ends.
The integrating capacitor C of memory transfer electric charge I1And C I2,
The electric capacity sensing circuit of described ALTERNATE SAMPLING electric charge secondary summation wherein, is used for to the switch 1 of sensor electrical capacity charge and switch 6 by clock Φ 1Control; Switch 2 and switch 5 are by clock Φ mutually 3Control.
The electric capacity sensing circuit of described ALTERNATE SAMPLING electric charge secondary summation wherein, is used to the switch 3 of reference capacitance array charging and switch 8 by clock Φ 1Control; Switch 4 and switch 7 are by clock Φ mutually 3Control.
The electric capacity sensing circuit of described ALTERNATE SAMPLING electric charge secondary summation wherein, is used for switch 9 that electric charge shifts and switch 14 by clock Φ mutually 2Control; Switch 11 and switch 14 are by clock Φ mutually 4Control; Switch 10, switch 13, switch 15 and switch 18 are by clock Φ mutually 2And Φ 4Φ is worked as in common control 2Or Φ 4Switch closure when being high level mutually.
The electric capacity sensing circuit of described ALTERNATE SAMPLING electric charge secondary summation, wherein, switch 16 and switch 17 are by Φ 1Control.
The electric capacity sensing circuit of described ALTERNATE SAMPLING electric charge secondary summation, wherein, switch 19, switch 20, switch 21 and switch 24 are used to fully differential operational transconductance amplifier input end that direct current biasing is provided.
The present invention adopts switched-capacitor circuit, and is insensitive to the stray capacitance of circuit, uses the correlated-double-sampling technology, can suppress the imbalance and the circuit noise of sensing circuit, thereby improves system accuracy.The present invention reaches the purpose that reduces the sensor mismatch and increase the system dynamics scope by adjusting the reference capacitance array, if fixed common mode voltage, electric charge secondary summing mode can be eliminated the mismatch that the reference capacitance array is introduced owing to the microelectronic technique manufacture deviation in the sensing circuit, if ignore the mismatch of reference capacitance, circuit can be eliminated the influence that the common mode voltage drift brings.
Description of drawings
Fig. 1 is the fully differential electric capacity sensing circuit theory diagram of ALTERNATE SAMPLING electric charge secondary summation of the present invention.
Fig. 1 a is reference capacitance array C among Fig. 1 R1Connection layout.
Fig. 1 b is reference capacitance array C among Fig. 1 R2Connection layout.
Fig. 2 is Φ among Fig. 1 1The circuitry phase working condition.
Fig. 3 is Φ among Fig. 1 2The circuitry phase working condition.
Fig. 4 is Φ among Fig. 1 3The circuitry phase working condition.
Fig. 5 is Φ among Fig. 1 4The circuitry phase working condition.
Embodiment
The present invention is towards the capacitive transducer of differential configurations such as gyroscope and micro-acceleration gauge, characteristics at the microsensor weak output signals, a kind of fully differential weak capacitive sensing circuit of ALTERNATE SAMPLING electric charge secondary summation has been proposed, this circuit adopts switched-capacitor circuit to realize, insensitive to stray capacitance, by the imbalance and the low frequency 1/f noise of correlated-double-sampling electric capacity inhibition circuit, to improve electric capacity resolution; Adopt reference capacitance to reduce the mismatch of sensor capacitance, and can improve the dynamic range of system; Fixed common mode voltage is eliminated the influence that the mismatch of reference capacitance is brought in the sensing circuit, fixed reference capacitor array (C by the mode of electric charge secondary summation R1=C R2), this mode can be eliminated the influence that the common mode voltage drift brings.
ALTERNATE SAMPLING electric charge secondary summation electric capacity sensing circuit of the present invention comprises the capacitor C of a pair of differential variation S1And C S2(also being capacitive transducer), the reference capacitance array C of the adjustable size of two complete symmetries R1And C R2(C ideally R1And C R2Symmetrical fully, C R1=C R2), a pair of capacitor C that is used to eliminate the sensing circuit imbalance and suppresses the low frequency 1/f noise D1And C D2(C D1=C D2), the integrating capacitor array (C of the adjustable size of two complete symmetries I1, C I2, C I3And C I4), a fully differential operational transconductance amplifier (OTA) and some switches are formed, switch 22 and 23 sizes by control signal G1 adjusting sensing circuit gain (V/C), and P1u, P2u, P3u, P1d, P2d and P3d are used for regulating reference capacitance C R1And C R2Size, rest switch is by 4 non-overlapping clock controls, they have determined how circuit works.
Illustrate in greater detail, as shown in Figure 1, C S1A termination common mode voltage (VCM), the other end links to each other with switch 1,2,9,11, another termination Vdd (power supply) of switch 1, another termination Gnd (common port) of switch 2, reference capacitance array C R1A termination VCM, an end of another termination switch 3,4,10, another termination Gnd of switch 3, another termination Vdd of switch 4, the same capacitor C of the other end of switch 9,10,12 D1An end link to each other the same capacitor C of an end of switch 15,16 D1The end that is connected with switch 9,10,12 is connected, and the other end of switch 16 connects with common mode voltage VCM, capacitor C D1The other end with the link of the positive input terminal of fully differential mutual conductance, an end of switch 19 also is connected to the positive input terminal of fully differential, the switch 15 and 19 the other end meet C with electric capacity I1And C I3An end link to each other C I1The other end link to each other C with the reversed-phase output of fully differential mutual conductance I3The other end connect with an end of switch 22, the other end of switch 22 connects with the reversed-phase output of fully differential operational transconductance amplifier, switch 21 is connected across capacitor C I1Two ends; C S2A termination common mode voltage VCM, the other end links to each other with switch 5,6,12,14, another termination Gnd of switch 5, another termination Vdd of switch 6, reference capacitance array C R2A termination VCM, an end of another termination switch 7,8,13, another termination Vdd of switch 7, another termination Gnd of switch 8, the same capacitor C of the other end of switch 11,13,14 D2An end link to each other the same capacitor C of an end of switch 17,18 D2The end that is connected with switch 11,13,14 is connected, and the other end of switch 17 connects with common mode voltage VCM, capacitor C D2The other end with the link of the positive input terminal of fully differential mutual conductance, an end of switch 20 also is connected to the inverting input of fully differential, the switch 18 and 20 the other end meet C with electric capacity I2And C I4An end link to each other C I2The other end link to each other C with the positive output end of fully differential mutual conductance I4The other end connect with an end of switch 23, the other end of switch 23 connects with the positive output end of fully differential operational transconductance amplifier, switch 24 is connected across capacitor C I1Two ends.
Wherein, reference capacitance array C R1And C R2Connection respectively shown in Fig. 1 a and Fig. 1 b, C wherein R11And C R21The size of size electric capacity when being in the equilibrium position near sensing capacitance, C R11An end connect common mode voltage VCM, another terminated nodes a (the node a among Fig. 1 and Fig. 1 a is same node), C R12, C R13And C R14For being used to regulate the electric capacity of reference capacitance array size, their a terminated nodes a, the other end is connected C by switch with common mode voltage VCM respectively R21An end connect common mode voltage VCM, another terminated nodes b (the node b among Fig. 1 and Fig. 1 b is same node), C R22, C R23And C R24For being used to regulate the electric capacity of reference capacitance array size, their a terminated nodes b, the other end is connected with common mode voltage VCM by switch respectively.
Circuit structure of the present invention is symmetrical fully, by add a fixing common mode voltage VCM (generally getting 2VCM=Vdd) between sensor capacitance and reference capacitance, with sensor capacitance C S1(C S2) and reference capacitance C R1(C R2) electric charge poor, transfer on the integrating capacitor, ideally, when sensor does not have extraneous input signal (acceleration or angular velocity), C S1=C S2=C R1=C R2, and when outer signals was imported, sensing capacitance can change, the electric charge on the integrating capacitor has directly reflected the variation delta C of sensor capacitance.So traditional testing circuit all requires C S1=C R1, C S2=C R2But because the error of making, even do not have outer signals input, C S1And C S2And C R1And C R2All can not be equal fully, therefore, the output voltage of integrating capacitor can not reflect sensor capacitance variation delta C directly and accurately.The present invention has adopted the fully differential circuit structure of ALTERNATE SAMPLING secondary summation, reference capacitance C R1And C R2Mismatch, and C S1With C R1And C S2With C R2Equate that not exclusively all without any influence, the voltage difference of circuit output end can reflect accurately that the difference Δ C of sensor capacitance (is C to net result S1-C S2).The introducing of reference capacitance mainly be for offset on a part of sensing capacitance with electric charge, to prevent integrator saturated (output voltage exceeds the output voltage swing of fully differential operational transconductance amplifier), help improving the gain and the dynamic range of circuit like this.In addition, circuit has also adopted the correlated-double-sampling technology, can suppress the imbalance and the low frequency 1/f noise of circuit, to improve electric capacity resolution.
So as Fig. 1, when capacitance type transducers was subjected to the driving of external force, differential capacitance can change on difference ground, by the transfer of electric charge and heavily distribution, the electric capacity Δ C of this differential variation can be converted into differential voltage output.Consider influences such as process deviation, C S1, C S2, C R1And C R2Equate that not exclusively sensing capacitance is C when making sensor be in balance S0, common mode voltage is generally VCM=Vdd/2, and the concrete course of work of circuit is as described below:
1) Φ 1Phase: be subjected to Φ 1The switch closure of control, rest switch disconnects.Equivalent electrical circuit is as shown in Figure 2:
Capacitor C S1On electric charge be:
Q CS1=(C S0+ΔC)(Vdd-VCM)=(C S0+ΔC)VCM (1)
Capacitor C S2On electric charge be:
Q CS2=(C S0-ΔC)(Vdd-VCM)=(C S0-ΔC)VCM (2)
Capacitor C R1And C R2On electric charge be:
Q CR1=-C R1·VCM (3)
Q CR2=-C R2·VCM (4)
Capacitor C is eliminated in imbalance D(owing to C among Fig. 1 D1=C D2, need not separately consider, so use C among Fig. 2 entirely DReplacement) electric charge on is:
Q CD=C D(V OCM-VCM) (5)
V wherein OCMCommon mode output voltage for operational transconductance amplifier.
2) Φ 2Phase: be subjected to Φ 2The switch closure of control, rest switch disconnects.Circuit connects as shown in Figure 3.
Capacitor C S1, C S2, C R1And C R2On electric charge be 0, their electric charge has all been transferred to integrating capacitor C IGo up (need to guarantee the integrating capacitor coupling in the fully differential circuit design, and C among Fig. 1 I1=C I2, C I3=C I4So integrating capacitor is used C entirely IReplace), C D1And C D2On electric charge remain unchanged, with Φ 1The state of phase is identical.
V ON=(C S0+ΔC-C R1)·VCM/C 1 (6)
V OP=(C S0-ΔC-C R2)·VCM/C 1 (7)
3) Φ 3Phase: be subjected to Φ 3The switch closure of control, rest switch disconnects.Circuit connects as shown in Figure 4.
Capacitor C S1On electric charge be:
Q CS1=-(C S0+ΔC)VCM (8)
Capacitor C S2On electric charge be:
Q CS2=-(C S0-ΔC)VCM (9)
Capacitor C R1And C R2On electric charge be:
Q CR1=C R1·(Vdd-VCM)=C R1·VCM (10)
Q CR2=C R2·(Vdd-VCM)=C R2·VCM (11)
At this moment, capacitor C D1And C D2And C IOn electric charge remain unchanged, with Φ 2The state of phase is identical.
4) Φ 4Phase: be subjected to Φ 4The switch closure of control, rest switch disconnects.Circuit connects as shown in Figure 5.
Same Φ 2Phase, capacitor C S1+ Δ C, C S2-Δ C, C R1And C R2On electric charge be 0, their electric charge has all been transferred to integrating capacitor C IOn, and at C IOn finished the summation of electric charge, C D1And C D2On electric charge remain unchanged, identical with the state of other phase, do not considering that the electric charge on the integrating capacitor is respectively under the situation that electric charge injects:
Q CIN=(C S0+ΔC)VCM-C R1VCM-(C S0-ΔC)VCM+C R1VCM=2ΔC·VCM (12)
Q CIP=(C S0-ΔC)VCM-C R2VCM-(C S0+ΔC)VCM+C R2VCM=2ΔC·VCM (13)
V ON = ΔC C I Vdd - - - ( 14 )
V OP = - ΔC C I Vdd - - - ( 15 )
The effect of reference capacitance mainly is to neutralize C S0Most of electric charge, in order to avoid cause that integrator voltage is saturated, promptly the output voltage of integrator has exceeded the output voltage swing of operational amplifier, thereby can suitably increase the gain (sensitivity) and the dynamic range of sensing circuit.By formula (12) and (13) as can be known, though the reference capacitance mismatch, to not having influence at last yet.
Above process is considered ideally, and sensing capacitance is when being in balance, C S1=C S2=C R1=C R2Conclusion is set up equally, if ignore the deviation of microelectronic technique, and satisfies C R1=C R2, then when drift takes place in common mode voltage, i.e. VCM ≠ Vdd/2, the conclusion of formula (14) and (15) is also set up, and circuit also can correctly detect the poor of sensing capacitance, and promptly circuit drifts about insensitive to common mode voltage.

Claims (6)

1. the electric capacity sensing circuit of ALTERNATE SAMPLING electric charge secondary summation, the circuit structure for symmetry mainly comprises:
The capacitive transducer of a pair of differential variation has sensor capacitance C S1And C S2
The reference capacitance array C of two adjustable size R1And C R2, and C R1=C R2
The capacitor C that is used to eliminate the sensing circuit imbalance and suppresses low-frequency noise DIAnd capacitor C D2, and C D1=C D2
The integrating capacitor array of the adjustable size of two symmetries is respectively by the integrating capacitor C that is used for the memory transfer electric charge I1And C I2, and the integrating capacitor C that is used for the regulating circuit gain I3And C I4Form;
A fully differential operational transconductance amplifier;
Wherein:
Capacitor C S1A termination common mode voltage, the other end links to each other with switch 1, switch 2, switch 9 and switch 11, another termination power of switch 1, another termination common port of switch 2; Switch 1 and switch 2 are used to sensor capacitance C S1Charging;
Reference capacitance array C R1A termination common mode voltage, the other end connects an end of switch 3, switch 4 and switch 10, another termination common port of switch 3, another termination power of switch 4, switch 3 and switch 4 are used to reference capacitance array C R1Charging;
The same capacitor C of the other end of switch 9, switch 10 and switch 12 D1An end link to each other;
The same capacitor C of one end of switch 15 and switch 16 D1An end that is connected with the switch 9, switch 10 and the switch 12 that are used for the electric charge transfer is connected, and the other end of switch 16 connects common mode voltage;
Eliminate the capacitor C of imbalance and inhibition low-frequency noise D1The normal phase input end that is connected the fully differential mutual conductance with an end of switch 19;
The other end of switch 15 and switch 19 is connected integrating capacitor C I1With integrating capacitor C I3An end, integrating capacitor C I3The other end connect an end of switch 22, integrating capacitor C I1The other end be connected the reversed-phase output of fully differential operational transconductance amplifier with the other end of switch 22;
Switch 21 is connected across integrating capacitor C I1Two ends;
C S2A termination common mode voltage, the other end links to each other with switch 5, switch 6, switch 12 and switch 14, another termination common port of switch 5, another termination power of switch 6; Switch 5 and switch 6 are used to sensor capacitance C S2Charging;
Reference capacitance array C R2A termination common mode voltage, the other end connects an end of switch 7, switch 8 and switch 13, another termination power of switch 7, another termination common port of switch 8, switch 7 and switch 8 are used to reference capacitance array C R2Charging;
The same capacitor C of the other end of switch 11, switch 13 and switch 14 D2An end link to each other;
The same capacitor C of one end of switch 17 and switch 18 D2An end that is connected with the switch 11, switch 13 and the switch 14 that are used for the electric charge transfer is connected, and the other end of switch 17 connects common mode voltage;
Eliminate the capacitor C of imbalance and inhibition low-frequency noise D2The inverting input that is connected the fully differential mutual conductance with an end of switch 20;
The other end of switch 18 and switch 20 is connected integrating capacitor C I2With integrating capacitor C I4An end, integrating capacitor C I4The other end connect integrating capacitor C with an end of switch 23 I2The positive output end that is connected the fully differential operational transconductance amplifier with the other end of switch 23;
Switch 24 is connected across capacitor C I2Two ends.
The integrating capacitor C of memory transfer electric charge I1And C I2,
2. according to the electric capacity sensing circuit of the described ALTERNATE SAMPLING electric charge of claim 1 secondary summation, wherein, be used for control end to the switch 1 of sensor electrical capacity charge and switch 6 by clock Φ 1Control; The control end of switch 2 and switch 5 is by clock Φ mutually 3Control.
3. according to the electric capacity sensing circuit of the described ALTERNATE SAMPLING electric charge of claim 1 secondary summation, wherein, be used to the switch 3 of reference capacitance array charging and switch 8 by clock Φ 1Control; Switch 4 and switch 7 are by clock Φ mutually 3Control.
4. according to the electric capacity sensing circuit of the described ALTERNATE SAMPLING electric charge of claim 1 secondary summation, wherein, be used for switch 9 that electric charge shifts and switch 14 by clock Φ mutually 2Control; Switch 11 and switch 14 are by clock Φ mutually 4Control; Switch 10, switch 13, switch 15 and switch 18 are by clock Φ mutually 2And Φ 4Φ is worked as in common control 2Or Φ 4Switch closure when being high level mutually.
5. according to the electric capacity sensing circuit of the described ALTERNATE SAMPLING electric charge of claim 1 secondary summation, wherein, switch 16 and switch 17 are by clock Φ mutually 1Control.
6. according to the electric capacity sensing circuit of the described ALTERNATE SAMPLING electric charge of claim 1 secondary summation, wherein, switch 19, switch 20, switch 21 and switch 24 are used to fully differential operational transconductance amplifier input end that direct current biasing is provided.
CN2010102184675A 2010-06-25 2010-06-25 Full-differential capacitance reading circuit for crosswise sampling secondary charge summation Pending CN102297688A (en)

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