GB2598121A - Fully differential switched capacitor integrator circuit - Google Patents

Abstract

A fully differential switched capacitor integrator circuit 100, operable in three modes, comprises a switching arrangement 102 and fully differential amplifier 120. The fully differential amplifier includes a series connected switch S1, S2 and capacitor C3, C4 in parallel with a reset switch S3, S4 between each amplifier output and its opposite polarity input. The switching arrangement has first and second input terminals 101a, 101b and first and second outputs 103a, 103b, the outputs being connected via input capacitors C1, C2 to the positive and negative inputs of the differential amplifier, respectively. In a first switch mode each input terminal is connected to its respective output, and in a second switch mode each input terminal is connected to the alternative output, i.e. cross-coupled. Each input capacitor C1, C2 is selectively connected to its associated signal input terminal, a reference voltage, or its opposite signal input terminal in respective first, second and third operating modes. Additionally, in the first operating mode the reset switches S3, S4 are closed, and in the second and third modes the series switches S1, S2 are closed. An apparatus for, and methods of, reducing differential to common mode error in an input differential signal or in a signal processing block, each using the fully differential switched capacitor integrator circuit, are also provided.

Description

FULLY DIFFERENTIAL SWITCHED CAPACITOR INTEGRATOR CIRCUIT

FIELD OF THE INVENTION

[0001] The present disclosure relates to the field of fully differential circuits. In particular, the present disclosure concerns circuitry for reducing common mode to differential error in fully differential circuits.

BACKGROUND

[0002] To achieve higher integration density and performance, integrated circuits (lCs) and the electronic components (including complementary metal-oxide-semiconductor -"CMOS" components) on which they rely have been scaled down in size in recent years, to the extent that process variability may play a role and small differences between ostensibly identical components may have a larger effect on the output of a circuit than might be expected. Process variability is particularly relevant at small scales, where the variation may be a large percentage of the full length or width of a component and as feature sizes approach fundamental dimensions such as the size of atoms and the wavelength of light for patterning lithography masks. Process variability can be environmental, temporal, or spatial. Spatial variations cause performance differences among components, the differences dependent on the distances between the components or the locations of the components on, for example, an IC. Typical spatial variations, such as line width or film thickness non-uniformity, universally exist across lots, across wafers (also known as slices or substrates), across chips and dies, and between circuit blocks and devices.

[0003] Such process variability can be particularly relevant to the output of, for example, fully differential circuits. Consider, for example, a fully differential amplifier. A fully differential amplifier is a DC-coupled high-gain electronic voltage amplifier with differential inputs and differential outputs. In some circumstances the differential may be a differential input voltage Vd defined as the difference between a first input voltage Vim, and a second input voltage Vim,.

In this context, the first input voltage may be expressed as Vi"p = vc", + and and the second input voltage as Vim,. = Vcm -ilia, where Km is the common mode voltage. In its ordinary usage, the output of the fully differential amplifier is controlled by two feedback paths which, because of the amplifier's high gain, almost completely determine the output voltage for any given input.

[0004] However, due to fabrication limitations, discrepancies between components may give rise to an asymmetric transfer function such that common mode voltage is not entirely removed and, as such, the output of the amplifier includes common mode to differential error. 1.

[0005] Such common mode to differential error can be particularly troublesome if the differential input voltage Va is very small, for example on the nanovolt scale or smaller, especially if the common mode voltage is large.

[0006] It is in this context that the subject matter contained in the present application has been devised.

SUMMARY OF THE INVENTION

[0007] According to an aspect of the invention, a fully differential switched capacitor integrator circuit is provided. The fully differential switched capacitor integrator circuit has a first input terminal and a second input terminal. The circuit is operable in at least a first mode, a second mode and a third mode.

[0008] The switched capacitor integrator circuit comprises a switching arrangement configurable to operate in a first switch mode and a second switch mode. In the first switch mode, the first input terminal is connected to a first output of the switching arrangement, and the second input terminal is connected to a second output of the switching arrangement. In the second switch mode, the first input terminal is connected to the second output of the switching arrangement, and the second input terminal is connected to the first output of the switching arrangement.

[0009] The switched capacitor integrator circuit further comprises a fully differential amplifier for amplifying a differential signal. The switched capacitor integrator circuit further comprises a first capacitor connected in series between the first output of the switching arrangement and a positive input of the fully differential amplifier, and a second capacitor connected in series between the second output of the switching arrangement and a negative input of the fully differential amplifier.

[0010] The switched capacitor integrator circuit further comprises a third capacitor connected in parallel to the positive input of the fully differential amplifier and a negative output of the fully differential amplifier and a fourth capacitor connected in parallel to the negative input of the fully differential amplifier and a positive output of the fully differential amplifier. A first switch is connected in series between the third capacitor and the negative output of the fully differential amplifier and a second switch is connected in series between the fourth capacitor and the positive output of the fully differential amplifier. A third switch is connected in parallel to the third capacitor, the first switch and the fully differential amplifier, and a fourth switch is connected in parallel to the fourth capacitor, the second switch and the fully differential amplifier.

[0011] In the first mode of operation, the switching arrangement is configured in the first switch mode to connect the first capacitor to the first input terminal and to connect the second capacitor to the second input terminal. In the first mode of operation, the first switch and the second switch are open, and the third switch and the fourth switch are closed.

[0012] In the second mode of operation, the first capacitor is disconnected from the first input terminal and the second capacitor is disconnected from the second input terminal. In the second mode of operation, the first switch and the second switch are closed, and the third switch and the fourth switch are open. In use, in the second mode of operation, a first junction between the first output of the switching arrangement and the first capacitor, and a second junction between the second output of the switching arrangement and the second capacitor, are both held at a reference potential.

[0013] In the third mode of operation, the switching arrangement is configured in the second switch mode to connect the first capacitor to the second input terminal and to connect the second capacitor to the first input terminal. In the third mode of operation the first switch and the second switch are closed, and the third switch and the fourth switch are open.

[0014] Advantageously, the fully differential switched capacitor integrator circuits described herein reduce common mode to differential error by mitigating the effect of any asymmetric transfer function of the circuit. Further advantageously, the gain in amplifying any differential input signal is approximately doubled.

[0015] The fully differential switched capacitor integrator circuit may be further operable in a reset mode. In the reset mode, a third junction between the third capacitor and the first switch is held at a second reference potential, and a fourth junction between the fourth capacitor and the second switch is also held at the second reference potential. In the reset mode, the first switch and the second switch may both be open, and the third switch and the fourth switch may both be closed.

[0016] Advantageously, operating the circuit in the reset mode configures the third capacitor and the fourth capacitor such that they are held at the same voltage.

[0017] The reference potential may be equal to the second reference potential. The reference potential and/or the second reference potential may be a ground.

[0018] The fully differential switched capacitor integrator circuit may further comprise a controller configured to operate the circuit in the first mode, the second mode or the third mode. The controller may be configured to sequentially operate the circuit in the first mode for a first time period, the second mode for a second time period and the third mode for a third time period. Alternatively, the controller may be configured to sequentially operate the circuit in the third mode for a first time period, the first mode for a second time period and the second mode for a third time period. Either sequence of operations produce the same effect -a near-zeroing of common mode signal and a near-doubling of the differential component of the input signal.

[0019] According to an aspect of the invention, a method of reducing a differential to common mode error in an input differential signal using a fully differential switched capacitor integrator circuit as described herein. The method comprises, whilst receiving the input differential signal at the first input terminal and the second input terminal, operating the fully differential switched capacitor integrator circuit in the first mode for a first time period, operating the fully differential switched capacitor integrator circuit in the second mode for a second time period in which the reference terminal is connected to a reference potential, and operating the fully differential switched capacitor integrator circuit in the third mode for a third time period. An amplified differential signal with a reduced common mode to differential error may therefore be output across the positive output and negative output of the fully differential amplifier when the circuit is operating in the third mode. The method thereby amplifies the input differential signal while supressing any common mode signal.

[0020] The input differential signal may be a voltage signal, a current signal, a tunnelling current signal, or any other suitable input differential signal.

[0021] According to an aspect of the invention, a computer-readable medium is provided. The computer-readable medium has instructions stored thereon, which when executed by one or more processors, cause the one or more processors processor to perform a method of reducing a differential to common mode error in an input differential signal as described herein. The computer-readable medium may be a non-transitory.

[0022] According to an aspect of the invention, an apparatus for reducing differential to common mode error in a signal processing block is provided, the signal processing block for implementing an additive function to a first signal and to a second signal. The apparatus comprises a fully differential switched capacitor integrator circuit as described herein, the first input terminal of the fully differential switched capacitor integrator circuit for connection to a first output terminal of the signal processing block, the second input terminal of the fully differential switched capacitor integrator circuit for connection to a second output terminal of the signal processing block.

[0023] The apparatus further comprises a primary switching arrangement configurable to operate in a third switch mode and a fourth switch mode. In the third switch mode, a first input terminal of the primary switching arrangement is connected to a first output terminal of the primary switching arrangement, and a second input terminal of the primary switching arrangement is connected to a second output terminal of the primary switching arrangement. In the fourth switch mode, the first input terminal of the primary switching arrangement is connected to the second output terminal of the primary switching arrangement, and the second input terminal of the primary switching arrangement is connected to the first output terminal of the primary switching arrangement. The first output terminal of the primary switching arrangement is for connection to a first input terminal of the signal processing block and the second output terminal of the primary switching arrangement is for connection to a second input terminal of the signal processing block.

[0024] The apparatus further comprises a controller configured to operate the fully differential switched capacitor integrator circuit in the first mode and the primary switching arrangement in the third switch mode for a first time period. The controller is further configured to operate the fully differential switched capacitor integrator circuit in the second mode for a second time period. The controller is further configured to operate the fully differential switched capacitor integrator circuit in the third mode and the primary switching arrangement in the fourth switch mode for a third time period.

[0025] Advantageously, and as will be demonstrated herein, such an apparatus may reduce the common mode to differential error in the fully differential signal processing block.

[0026] The apparatus may further comprise the signal processing block, wherein the signal processing block is connected between the first and the second output terminals of the primary switching arrangement and the first and the second input terminals of the fully differential switched capacitor integrator circuit and configured to, in use, implement the additive function to a first signal received from the first output terminal of the primary switching arrangement and a second signal received from the second output terminal of the primary switching arrangement.

[0027] The signal-processing block may be any suitable fully differential signal-processing block for performing an additive function. For example, the signal processing block may be configured to perform current-to-voltage amplification.

[0028] According to an aspect of the invention, a method of reducing common mode to differential error in a signal processing block using apparatus as described herein. The method comprises, whilst receiving an input differential signal at the first input terminal and the second input terminal of the primary switching arrangement, operating the fully differential switched capacitor integrator circuit in the first mode and the primary switching arrangement in the third switch mode for a first time period; operating the fully differential switched capacitor integrator circuit in the second mode for a second time period; and operating the fully differential switched capacitor integrator circuit in the third mode and the primary switching arrangement in the fourth switch mode for a third time period. The input differential signal may be a current signal or a voltage signal or any other suitable input differential signal.

[0029] According to an aspect of the invention, a computer-readable medium is provided. The computer-readable medium has instructions stored thereon, which when executed by one or more processors, cause the one or more processors processor to perform a method of reducing a differential to common mode error in a signal-processing block as described herein. The computer-readable medium may be a non-transitory.

[0030] According to an aspect of the invention, a computer readable medium is provided. The computer-readable medium has stored thereon comprising a computer readable description of a fully differential switched capacitor integrator circuit as described herein and or an apparatus as described herein. The computer-readable description may be suitable for enabling manufacture of the fully differential switched capacitor integrator circuit and/or the apparatus.

[0031] The computer program and/or the code for performing such methods as described herein may be provided to an apparatus, such as a computer, on the computer readable medium or computer program product. The computer readable medium could be, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, or a propagation medium for data transmission, for example for downloading the code over the Internet. Alternatively, the computer readable medium could take the form of a physical computer readable medium such as semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disc, and an optical disk, such as a CD-ROM, CD-R/VV or DVD.

[0032] Many modifications and other embodiments of the inventions set out herein will come to mind to a person skilled in the art to which these inventions pertain in light of the teachings presented herein. Therefore, it will be understood that the disclosure herein is not to be limited to the specific embodiments disclosed herein. Moreover, although the description provided herein provides example embodiments in the context of certain combinations of elements, steps and/or functions may be provided by alternative embodiments without departing from the scope of the invention.

BRIEF DESCRIPTION OF FIGURES

[0033] One or more embodiments of the invention are shown schematically, by way of example only, in the accompanying drawings, in which: - Figure 1 depicts a fully differential switched capacitor integrator; - Figure 2 depicts a fully differential switched capacitor integrator circuit; - Figure 3 depicts an apparatus for reducing the common mode to differential error in a signal processing block; - Figure 4 depicts another apparatus for reducing the common mode to differential error in a signal processing block; -Figure 5 depicts an example of a signal processing block; and -Figure 6 depicts a switching timing diagram for depicting the operation of a fully differential switched capacitor integrator.

[0034] Throughout the description and the drawings, like reference numerals refer to like parts.

DETAILED DESCRIPTION

[0035] Before particular examples of the present invention are described, it is to be understood that the present disclosure is not limited to the particular circuit and methods described herein. It is also to be understood that the terminology used herein is used for describing particular examples only and is not intended to limit the scope of the claims.

[0036] In describing and claiming the circuit and methods of the present invention, the following terminology will be used: the singular forms "a", "an", and "the" include plural forms unless the context clearly dictates otherwise.

[0037] Figure 1 depicts a fully differential switched capacitor integrator circuit 100 according to an example of the present invention. The fully differential switched capacitor integrator circuit 100 may be fabricated using CMOS fabrication techniques. The skilled person would appreciate that the circuit of Figure 1 may be modified in numerous ways while still providing the same effect, for example further or fewer components and switches may be included.

[0038] The fully differential switched capacitor integrator circuit 100 comprises a switching arrangement 102. The switching arrangement 102 may be referred to as, for example, a mixer or a switching block.

[0039] The switching arrangement 102 comprises a first input terminal 101a and a second input terminal 101b. The first input terminal 101a may be referred to as a positive input terminal and the second input terminal 101b may be referred to as a negative input terminal. Alternatively, the first input terminal 101a and the second input terminal 101b may be referred to together as a differential input terminal.

[0040] The switching arrangement 102 further comprises a first output 103a and a second output 103b. The first output 103a may be referred to as a positive output and the second output 103b may be referred to as a negative output. Alternatively, the first output 103a and the second output 103b may be referred to together as a differential output.

[0041] The switching arrangement 102 is configurable to operate in a first switch mode and a second switch mode. In the first switch mode, the switching arrangement 102 is configured such that the first input terminal 101a is connected to a first output 103a of the switching arrangement 102 and the second input terminal 101b is connected to a second output 103b of the switching arrangement 102. The first input terminal 101a may be switchably connected to the first output 103a and the second input may be switchably connected to the second output 103b. Referring to the figure, in the first switch mode the first input terminal 101a is connected to the first output 103a by a switch SA1 and the second input terminal 101b is connected to the second output 103b by a switch SA2. In the second switch mode, the switching arrangement 102 is configured such that the first input terminal 101a is connected to the second output 103b of the switching arrangement 102 and the second input terminal 101b is connected to the first output 103a of the switching arrangement 102. The first input terminal 101a may be switchably connected to the second output 103b and the second input may be switchably connected to the first output 103a. In Figure 1, in the second switch mode the first input terminal 101a is connected to the second output 103b by a switch SA4 and the second input terminal 101b is connected to the first output 103a by a switch SA3.

[0042] The switches SA1-SA4 may comprise transistors or any other known fast switches.

[0043] The fully differential switched capacitor integrator circuit 100 further comprises a fully differential amplifier 120 for amplifying a differential signal. The fully differential amplifier 120 may be referred to as, for example, a fully differential operational amplifier, a differential amplifier, an operational amplifier or an amplifier. The fully differential amplifier 120 has a positive input and a negative input, and a negative output 111a and a positive output 111b.

[0044] The fully differential switched capacitor integrator circuit 100 further comprises a first capacitor Cl and a second capacitor 02. The first capacitor Cl is connected in series between the first output 103a of the switching arrangement 102 and the positive input of the fully differential amplifier 120 and the second capacitor 02 is connected in series between the second output 103b of the switching arrangement 102 and the negative input of the fully differential amplifier 120. The first capacitor Cl may have a capacitance of C, and the second capacitor 02 may have a capacitance of C2. While it would in many circumstances be beneficial for the two capacitances C1 and C2 to be equal, in practice due to differences that inherently creep in during manufacture this may not, and indeed most likely will not, be the case. Such differences in capacitance may be very small but can still lead to errors when attempting to amplify a differential input signal using the amplifier 120. In particular, if the two capacitances are not equal then the switched capacitor integrator has an asymmetric transfer function.

[0045] The fully differential switched capacitor integrator circuit 100 further comprises a third capacitor C3 and a fourth capacitor C4. The third capacitor C3 is connected in parallel to the positive input of the fully differential amplifier 120 and the negative output 111a of the fully differential amplifier 120. The fourth capacitor 04 is connected in parallel to the negative input of the fully differential amplifier 120 and the positive output 111b of the fully differential amplifier 120. That is to say, the third capacitor C3 is connected to the positive input of the fully differential amplifier 120 and the negative output 111a of the fully differential amplifier 120 and in parallel with the fully differential amplifier 120, and the fourth capacitor 04 is connected to the negative input of the fully differential amplifier 120 and the positive output 111b of the fully differential amplifier 120 and in parallel with the fully differential amplifier 120. The third capacitor C3 may have a capacitance of C3 and the second capacitor C4 may have a capacitance of C4. Once again, while it may be desirable for the capacitance C3 to equal the capacitance C4, in practice very small differences may creep in during the manufacturing process, such that this may not be the case. This may in turn contribute to the switched capacitor integrator circuit having an asymmetric transfer function.

[0046] The fully differential switched capacitor integrator circuit 100 further comprises a first switch Si and a second switch S2. The first switch Si is connected in series between the third capacitor 03 and the negative output 111a of the fully differential amplifier 120 and the second switch 52 connected in series between the fourth capacitor 04 and the positive output 111b of the fully differential amplifier 120. That is, the first switch Si is connected in parallel with the fully differential amplifier 120 and between the third capacitor C3 and the negative output 111a of the fully differential amplifier 120. The second switch S2 is connected in parallel with the fully differential amplifier 120 and between the fourth capacitor C4 and the positive output 111b of the fully differential amplifier 120.

[0047] The fully differential switched capacitor integrator circuit 100 further comprises a third switch S3 and a fourth switch S4. The third switch S3 is connected in parallel with the third capacitor 03, the first switch Si and the full differential amplifier 120. The fourth switch 54 is connected in parallel with the fourth capacitor C4, the second switch S2 and the fully differential amplifier 120. That is, the third switch S3 is connected to the positive input of the fully differential amplifier 120 and negative output 111a of the fully differential amplifier 120 and in parallel with the fully differential amplifier 120, the third capacitor 03 and the first switch Si, and the fourth switch S4 is connected to the negative input of the fully differential amplifier 120 and positive output 111b of the fully differential amplifier 120 and in parallel with the fully differential amplifier 120, the fourth capacitor 04 and the second switch S2.

[0048] The fully differential switched capacitor integrator circuit 100 further comprises a first junction 104a and second junction 104b for connection to a reference potential. In particular, the first junction 104a is between the first output 103a of the switching arrangement 102 and the first capacitor C1 and is switchably connected to a reference potential Vren via switch SREF1. The second junction 104b between the second output 103b of the switching arrangement 102 and the second capacitor C2 is switchably connected to the reference potential V"" via switch SREF2. In this way, the left hand plates of the first capacitor Cl and the second capacitor 02 may be connected to the reference potential V"ri. The skilled person would appreciate that while the two junctions are connectable to the reference potential via two switches in Figure 1, other architectures would be equally applicable, for example a single switch may be used to connect both junctions to the reference potential, or multiple switches may be used.

[0049] The reference potential V"" may be a ground.

[0050] The fully differential switched capacitor integrator circuit 100 is operable in at least three modes.

[0051] In a first mode of operation, the switching arrangement 102 is configured in the first switch mode to connect the first input terminal 101a to the first capacitor C1 and connect the second input terminal 101b to the second capacitor C2, the first switch Si and the second switch 32 are configured open, and the third switch 33 and the fourth switch 34 are configured closed. That is to say, the switching arrangement 102 is configured to connect the first input terminal 101a to the first output 103a of the switching arrangement 102 and the second input terminal 101b to the second output 103b of the switching arrangement 102. With respect to Figure 1, switches SA1 and SA2 are closed and switches SA3 and 5A4 are open. In the first mode, the junctions 104a, 104b may not be connected to the reference potential -the switches SREF1 and SREF2 are open.

[0052] In a second mode of operation, the first capacitor C1 is disconnected from the first input terminal 101a and the second capacitor 02 is disconnected from the second input terminal 101b. In the circuit 100 of Figure 1, all switches SA1-5A4 of the switching arrangement 102 are opened. Furthermore, in the second mode, the first switch Si and the second switch 32 are closed, the third switch 33 and the fourth switch 34 are open and the switches SREF1 and SREF2 are closed so as to hold the junctions 104a, 104b at the reference potential Vrefi.

[0053] In the third mode, the switching arrangement 102 is configured in the second switch mode to connect the first input terminal 101a to the second capacitor 02 and connect the second input terminal 101b to the first capacitor C1. In Figure 1, the switches 5A3 and 5A4 are closed and the switches SA1 and SA2 are open. Furthermore, in the third mode, the first switch Si and the second switch 32 are configured closed, and the third switch S3 and the fourth switch 34 are configured open. In the third mode, the junctions 104a, 104b are not connected to the reference potential 1/7011.

[0054] When in use, the first input terminal 101a receives a first input signal Vinp and the second input terminal 101b receives a second input signal Vim,. The differential input signal Vd received at the first input terminal 101a and the second input terminal 101b is a function of the difference in voltage between the first input and the second input and can be written in terms of the first input signal Vinp and the second input signal Vin": Vd = Vi"p -17i," [0055] The common mode input signal 14m received at the first input terminal 101a and the second input terminal 101b can be written in terms of the first input signal Vinp and the second input signal Vi"": Vcrn -(Vmp Vunn)/2.

[0056] Accordingly, the first input signal Vi"p and the second input signal Vi"" may be written in terms of the differential input signal and the common mode input signal as Vpm = 17,m + Vd and 17pm = Vcm -Vd, respectively.

[0057] When the circuit 100 is operating in the first mode, the switching arrangement 102 is configured in the first switch mode, the first switch Si and the second switch S2 are open, the third switch 33 and the fourth switch S4 are closed and the junctions 104a, 104b are not connected to the reference potential 17,-61,1. When receiving the first input signal Vi"p at the first input terminal 101a and the second input signal Vpm at the second input terminal 101b in the first mode there is a voltage 171p at the first output 103a of the switching arrangement 102 and a voltage V1" at the second output 103b of the switching arrangement 102. The voltages at the first output 103a and the second output 103b are given by 171p = = Von + -17,1 and = Vi" = 'cm - , respectively, in the first mode. Accordingly, the differential voltage Vld at the first output 103a and the second output 103b is equal to the differential input signal, Via = V. Therefore, when operating in the first mode, the first capacitor Cl and the second capacitor C2 are charged based on voltages Vim, and Vim,. respectively.

[0058] Furthermore, as the first switch Si and the second switch 32 are open when operating in the first mode, a voltage across the third capacitor VG3 and a voltage across the fourth capacitor li4 remain unchanged. For example, if the voltages across both the third capacitor 03 and the fourth capacitor 04 are initially OV, then when operating in the first mode the voltages will remain at OV.

[0059] The first mode may be considered to be a sampling mode or a non-inverting sampling mode, as the first capacitor Cl and the second capacitor C2 effectively "sample" the first input signal 14,p and the second input signal Vinn, storing voltages corresponding to the first input signal Vinp and the second input signal V across the first capacitor Cl and the second capacitor C2, respectively.

[0060] Following operating the circuit 100 in the first mode for a first time period, the circuit 100 may operate in the second mode. The circuit 100 may transition from the configuration of the first mode to the configuration of the second mode in such a way that the voltages stored across the first capacitor 01 and the second capacitor 02 are held on the capacitors during a transition period (i.e. the voltage on the first capacitor Cl and the voltage on the second capacitor C2 do not change during the transition period from the first mode to the second mode). An example switching timing diagram, showing a possible switching transition between the first mode and the second mode, is depicted in Figure 6 (discussed below).

[0061] In the second mode, the switching arrangement 102 is configured such that both the first input terminal 101a and the second input terminal 101b are disconnected from both the first output 103a and the second output 103b of the switching arrangement 102, the junctions 104a, 104b are connected to the reference potential V"fi, the first switch Si and second switch S2 are closed (connecting the third capacitor C3 and fourth capacitor 04 to the negative output 111a and positive output 111b of the fully differential amplifier 120 respectively) and the third switch S3 and fourth switch S4 are open. Operating the circuit 100 in the second mode having previously operated the circuit 100 in the first mode causes a charge transfer from the first capacitor Cl and the second capacitor 02 to the third capacitor C3 and fourth capacitor C4 respectively, thereby storing a voltage across the third capacitor C3 and the fourth capacitor C4. The charge transfer causes the voltage across the third capacitor C3 to increase by Vc3 = (C1/C3)V1np and the voltage across the fourth capacitor C4 to increase by VC4 = (C2/ C4)171". For example, if the voltages across the third capacitor C3 and the fourth capacitor C4 were initially OV, the voltages stored across the third capacitor 03 and the fourth capacitor C4 having operated the circuit 100 in the first mode followed by the second mode would be by Vc3 = (C1/C3)Vinp and Vc4 = (C2/C4)Vinn respectively. Accordingly, an amplified voltage signal 17,,,,,t" is output at the negative output 111a of the fully differential amplifier 120 and an amplified voltage signal V0 is is output at the positive output 111b of the fully differential amplifier 120. In the case that the third capacitor 03 and the fourth capacitor C4 were initially at OV, the amplified voltage signal output at the negative output 111a of the fully differential amplifier 120 is given by Voutu = VC3 = (C1/C3)Virip and the amplified voltage signal output at the positive output 111b of the fully differential amplifier 120 is given by Voutp = VC4 = (C2/C4)V1nn.

[0062] The second mode may therefore be considered to be an amplification mode, or a non-inverting amplification mode, as an amplified differential single is output at the negative output 111a and positive output 111b of the fully differential amplifier 120 and the output amplified voltage signals are proportional to the input signals (i.e. non-inverting).

[0063] The amplified voltage output at the negative output 111a in the second mode may be proportional to the total voltage stored across the third capacitor C3, and the amplified voltage output at the positive output 111b in the second mode may be proportional to the total voltage stored across the fourth capacitor C4.

[0064] The circuit 100 may also be operated in a third mode. When operating in the third mode, the switching arrangement 102 is configured in the second switch mode such that the first input terminal 101a is connected to the second output 103b and the second input terminal 101b is connected to the first output 103a, the first switch Si and the second switch S2 are closed, the third switch S3 and the fourth switch 54 are open, and the junctions 104a, 104b are not connected to the reference potential Vrefi. The first input terminal 101a receives the first input signal Vinp and the second input terminal 101b receives the second input signal signal V. When receiving the first input signal Vinp at the first input terminal 101a and the second input signal Vt" at the second input terminal 101b in the first mode, there is a voltage V'w at the first output 103a of the switching arrangement 102 and there is a voltage V'1. at the second output 103b of the switching arrangement 102, (wherein, defining Va as above as = Vinp -Vi" ) the voltages are given by vnn = * i -Vc*in - 1217,1 and 1P,, = Vi" = Vern +12 Va in the second mode. Accordingly, when operating in the third mode, the differential signal V'w at the first output 103a and the second output 103b is inverted relative to the differential signal Vw at the first output 103a and second output 103b when operating in the first mode, whereas the common mode signal remains the same. The differential input signal at the first output 103a and the second output 103b is therefore V'w = -1/(j.

[0065] Considering an example in which the third capacitor C3 and the fourth capacitor C4 are both held at OV before operating in the third mode, when operating in the third mode, the voltage across the third capacitor C3 becomes Vc3 = -(C1/C3)V1n" and the voltage across the fourth capacitor C4 becomes lic4 = -(C2/C4)V1np. This gives an amplified voltage signal at the negative output 111a of the fully differential amplifier 120 of V"t, = -(Ci/C3)Vi" and an amplified voltage signal at the positive output 111b of the fully differential amplifier 120 of Voutp -(C2 /C4Wirtp [0066] The third mode may therefore be considered to be an amplification mode, or an inverting amplification mode, as an amplified voltage signal at the negative output 111a is proportional to the (-ve) input signal at the second input terminal 101b and the amplified voltage signal at the positive output 111b is proportional to the (-ve) input signal at the first input terminal 101a (i.e. the output signals are inverted relative to the input signals).

[0067] Whilst receiving the first input signal Vim, at the first input terminal 101a and the second input signal Vinn at the second input terminal 101b the circuit 100 may be operated sequentially in the first mode for a first time period, the second mode for a second time period and the third mode for a third time period.

[0068] As detailed above, sequentially operating the circuit 100 in the first mode and the second mode results in a voltage of Vc3 = (C1/C3)Vinp being stored across the third capacitor C3 and a voltage of lin, = (C2/C4)Vi" being stored across the fourth capacitor C4. The circuit 100 may then transition from the configuration of the second mode to the configuration of the third mode in such a way that the voltages stored across the third capacitor C3 and the fourth capacitor C4 are held on the capacitors during a transition period (i.e. the voltage on the third capacitor C3 and the voltage on the fourth capacitor C4 do not change during the transition period from the first mode to the second mode -see Figure 6). Subsequently, operating the circuit 100 in the third mode, the voltage across the third capacitor C3 becomes Vc3 = (C1/C3)V1np (C1/C3)Vinn = (Ci /C3) [Vim) Vind = (Ci/C3)Vd, and the voltage across the fourth capacitor C4 becomes Vc4 = (C2 /C4)Vi" (C2/C4)V1"p = (C2 /C4) [Vi" Vinp] = -(C1/C3)Vd. Hence, the amplified voltage output at the negative output 111a of the fully differential amplifier 120 in the third mode is V" t, = (C1/C3)tra and the amplified voltage output at the positive output 111b of the fully differential amplifier 120 in the third mode is Voutp -(Cl/C3)Vd. Therefore, the common mode signal is cancelled and the differential output signal at the negative output 111a and the positive output 111b of the fully differential amplifier 120 is given by Voutd -Vouttt Voutp =V.

-j3 j4

[0069] Accordingly, by operating the circuit 100 sequentially in the first mode, second mode and third mode, the input signals are sampled twice and different transfer functions are applied, thereby effectively minimising the influence of the common mode voltage on the differential output of the circuit 100 and, at the same time, increasing the differential signal gain. Such an operation of the circuit may be described in relation to the switching diagram of Figure 6.

[0070] Figure 6 depicts a switching timing diagram 600 describing the operation of the switches SA1-SA4, S1-S4 and SREF1-SREF4 during the sequential operation of the circuit in the first mode, the second mode and the third mode. The switching timing diagram 600 depicts a closed switch with a line which is raised relative to when a switch is open.

[0071] The transitions between the modes can be seen in the switching timing diagram 600. For example, in transitioning from the second mode to the third mode the switching sequence is (starting at the end of the second mode): switches Si and S2 open, switches S2 and S4 close, switches SREF1 and SREF2 open, switches SA3 and SA4 close, switches 52 and 54 open and switches Si and S2 close.

[0072] A similar result to that described above can be achieved by sequentially operating the circuit 100 in the third mode for the third time period, the first mode for the first time period and the second mode for the second time period (not shown in Figure 6). In this case, operating the circuit 100 in the third mode initially gives a voltage across the third capacitor 03 of VG, = -(C1/C3) Vi" and a voltage across the fourth capacitor C4 of Vc4 = -(C2/C4)Vinc. Subsequently operating the circuit 100 in the first mode for the first time period will store a voltage across the first capacitor C1 and second capacitor 02 (as described above) and operating the circuit 100 in the second mode for the second time period will cause a charge transfer from the first capacitor Cl and the second capacitor C2 to the third capacitor C3 and the fourth capacitor 04 respectively. Accordingly, the voltage across the third capacitor 03 becomes Vc3 = (C4/C3)V1np -(C4/C3)V111" = (C4/C3) [Vinp -Vinn] = (Cl/ C3)Vd, and the voltage across the fourth capacitor C4 becomes Vc4 = (C2/C4)V -(C2/C4)V1np = (C2/ C4)[Vi" -Vinp] = -(C4/C3)Vd. This again results in an amplified voltage output at the negative output 111a of the fully differential amplifier 120 of V,,"tn = (CIC3)1/a and an amplified voltage output at the positive output 111b of the fully differential amplifier 120 of Voutp = (Ci 7 C3)Vd. * [0073] As can be seen, sequentially operating the circuit 100 in the first mode for the first time period, the second mode for the second time period and the third mode for the third time period achieves substantially the same result as sequentially operating the circuit 100 in the third mode for the third time period, the first mode for the first time period and the second mode for the second time period.

[0074] The fully differential switched capacitor integrator circuit 100 of Figure 1 may comprise further junctions 105a, 105b for connection to a second reference potential!cep.

The third junction 105a is located between the third capacitor 03 and the first switch Si. The fourth junction 105b is located between the fourth capacitor C4 and the second switch 52. The junctions 105a and 105b are switchably connected to the second reference potential liren via switches SREF3 and SREF4. While two switches SREF3 and SREF4 are shown in Figure 1, the skilled person would appreciate that further or fewer switches may be used to connect both junctions to second reference potential V"f2. By coupling the capacitors 03 and 04 to the reference potential V1012, one can effectively "reset' the capacitors 03 and C4.The circuit 100 may further be operated in a reset mode. The reset mode may also be referred to as an initialisation mode.

[0075] In the reset mode, the switching arrangement 102 may be configured in the first switch mode or the second switch mode, the first switch Si and the second switch S2 are configured open, the third switch S3 and the fourth switch S4 are configured closed and the third and fourth junctions 105a, 105b are connected to the second reference potential V"[2. The junctions 104a, 104b are not connected to the reference potential V"fi [0076] Connecting the junctions 105a, 105b to the second reference potential Vref2 resets the third capacitor C3 and the fourth capacitor C4 and may store the fully differential amplifier's offset across the third capacitor 03 and the second capacitor 04. The second reference potential may therefore be set according to the offset of the fully differential amplifier 120. Alternatively, any potential may be stored across the third capacitor 03 and the fourth capacitor C4 by connecting the junctions 105a, 105b to the second reference potential Vref2.

[0077] The circuit 100 may be operated in the reset mode prior to operating in any of the first mode, the second mode or the third mode. Similarly, the circuit may be operated in the reset mode following operation of the circuit in any of the first mode, the second mode or the third mode in order to reset the circuit.

[0078] The switches SREF3 and SREF4 are configured open in all modes other than the reset mode. For example, in the first mode, the second mode or the third mode, the switches SREF3 and SREF4 are open.

[0079] The second reference potential V"f 2 may be a ground. For example, if the second reference potential is a ground then the capacitors 03 and 04 will be reset to DV. The second reference potential V"f2 may be equal to the first reference potential Vref, . [0080] Figure 2 depicts a fully differential switched capacitor integrator circuit according to Figure 1, wherein the circuit 200 further comprises a controller 240.

[0081] The controller 240 may be configured to operate the circuit 100 in the first mode, the second mode, the third mode or the reset mode. The controller 240 may be referred to as a control unit, control logic or a processor.

[0082] The controller 240 may control the operation of the fully differential switched capacitor integrator circuit. For example, the controller 240 may be configured to control the operation of the circuit by opening and closing the switches Si, S2, S3, S4, by connecting the junctions 104a, 104b to the reference potential V"fi, or by connecting the second reference terminals 105a, 105b to the second reference potential Vr ef 2.

[0083] Additionally, the controller 240 may configure the switching arrangement 202 in the first switch mode or the second switch mode, or configure the switching arrangement 202 such that the first input terminal 101a and the second input terminal 101b are disconnected from both the first output 103a and the second output 103b. The controller 240 may configure any of the switches of the switching arrangement 202 open or closed.

[0084] In one example, the controller 240 may be configured to sequentially operate the circuit in the first mode for the first time period, the second mode for the second time period and the third mode for the third time period.

[0085] In another example, the controller 240 may be configured to sequentially operate the circuit in the third mode for the third time period, the first mode for the first time period and the second mode for the second time period.

[0086] The first time period may or may not be the same as the second time period which may or may not be the same as the third time period.

[0087] Whilst the controller 240 is for controlling the operation of the circuit 200, it is understood that the controller 240 may be described as a constituent part of the circuit 200. The controller 240 may still be described as part of the circuit 200 even if the controller 240 itself is external to the circuit 200 (e.g. if the controller 240 takes the form of a computer or processor external to the circuit).

[0088] As has been demonstrated above, the switched capacitor integrator circuit 100, may be operated so as to advantageously reduce common mode to differential error as compared to known switched capacitor integrator circuits. The circuits described above may further be used to reduce common mode to differential error in other differential signal processing blocks.

[0089] In an ideal differential circuit, there is an infinite common mode rejection ratio. However, as described previously, in practice due to CMOS fabrication limitations, real-world differential circuits exhibit asymmetric transfer functions in the differential signal path, inhibiting them from achieving the theoretical infinite common mode rejection ratio as any common mode signal unevenly couples to the different branches, causing an error to appear at the differential output.

[0090] A differential block/circuit that suffers from common-mode to differential error may be referred to herein as a "processing block" or "signal processing block". An additive signal processing block is a processing block for implementing an additive function (an additive function is a function f that satisfies the equation [(A + = [(A) + [(B)) to each of its inputs.

[0091] Figure 3 depicts an apparatus 300 for reducing differential to common mode error in a signal processing block 320 (which may or may not be part of the apparatus).

[0092] The apparatus 300 comprises a primary switching arrangement 310, a secondary switching arrangement 330 and a summation unit 340.

[0093] The primary switching arrangement 310 comprises a first input terminal and a second input terminal. The first input terminal may be referred to as a positive input terminal and the second input terminal may be referred to as a negative input terminal. Alternatively, the first input terminal and the second input terminal may be referred to together as a differential input terminal.

[0094] The primary switching arrangement 310 further comprises a first output and a second output. The first output may be referred to as a positive output and the second output may be referred to as a negative output. Alternatively, the first output and the second output may be referred to together as a differential output.

[0095] The primary switching arrangement 310 is configurable to operate in a first switch mode and a second switch mode. In the first switch mode, the primary switching arrangement 310 is configured such that the first input terminal is connected to a first output of the primary switching arrangement 310 and the second input terminal is connected to a second output of the switching arrangement 310. The first input terminal may be switchably connected to the first output and the second input may be switchably connected to the second output. For example, the first input terminal may be connected to the first output by a switch and the second input terminal may be connected to the second output by a switch. In the second switch mode, the primary switching arrangement 310 is configured such that the first input terminal is connected to the second output of the primary switching arrangement 310 and the second input terminal is connected to the first output of the primary switching arrangement 310. The first input terminal may be switchably connected to the second output and the second input may be switchably connected to the first output. For example, the first input terminal may be connected to the second output by a switch and the second input terminal may be connected to the first output by a switch.

[0096] When in use, the primary switching arrangement 310 may receive a first input signal INAp at the first input terminal and a second input signal MAR at the second input terminal. Furthermore, the primary switching arrangement may be configured to output a signal 1NBp at the first output terminal of the primary switching arrangement 310 and a signal IN!?,, at the second output terminal of the primary switching arrangement 310.

[0097] The signal processing block 320 may be configured to receive the signal IN Bp at a first input and receive the signal [NB,., at a second input. The signal processing block 320 may be configured to output a signal OUTBp at a first output and may be configured to output a signal OUT!?,, at a second output.

[0098] The signal processing block 320 may be for implementing an additive function fp to a signal received at the first input and for implementing an additive function f" to a signal received at the second input. Even if the additive functions fp and fn are designed to be the same, due to, for example, fabrication tolerance errors, there will most likely be a difference in the two functions and functions fp # fn. When the signal processing block 320 receives a signal INBp at the first input and receives a signal INF), at the second input, the function fp is such that fi(/NBp) = OUTBI, and the function f, is such that [(/NB) = OUTB", wherein the signal OUTBp is output at the first output and the signal OUTS,, is output at the second output.

An additive function is one that satisfies the relationship f (A + = f (A) + f (B).

[0099] The secondary switching arrangement 330, which may be substantially the same as the primary switching configuration 310, is configured to receive the signal OUTBp at a first input and receive the signal OUTS,., at a second input. The secondary switching arrangement may output an output signal OUT; at a first output and output an output signal OUTC, at a second output. The secondary switching arrangement 330 is configured to operate in a first switch mode (corresponding to the first switch mode of the primary switching arrangement 310) and a second switch mode (corresponding to the second switch mode of the primary switching arrangement 310).

[00100] The summation unit 340 may receive the signal OUTCp at a first input and receive the signal OUTC" at a second input and output a signal OUTAp at a first output and output a signal OUTA" at a second output.

[00101] The summation unit 340 may be configured to sample and store signals received at the first input and the second input at a given time. Furthermore, the summation unit 340 may be configured to perform summations of signals sampled and stored at different times.

[00102] The apparatus 300 may further comprise a controller 350. The controller 350 may be configured to operate the primary switching arrangement in the first switch mode or the second switch mode, and configured to operate the secondary switching arrangement in the first switch mode or the second switch mode. The controller 350 may be further configured to control the summation unit 340. The controller 350 may be referred to as a control unit, control logic or a processor.

[00103] For example, whilst receiving the signals INAp and INA" at the first input terminal and second input terminal of the primary switching arrangement 310 respectively, the controller 350 may be configured to operate the primary switching arrangement 310 in the first switch mode and the secondary switching arrangement 330 in the first switch mode.

[00104] Operating the primary switching arrangement 310 in the first switch mode, the signal output at the first output is given by 1NBp = INAp and the signal output at the second output is given by INB" = IN An. Therefore, the outputs from the signal processing block 320 will be given by OUTBp = fp(INAp) and OUTB" = f"(INA"). Furthermore, as the secondary switching arrangement 330 is configured in the first switch mode, the signal OUTCp = OUTBp = fp(INAp) and the signal OUTC" = OUTB" = f"(INAn.)* [00105] The summation unit 340 may then sample and store the signals OUTC, and OUTC" at a first time T1. The signals sampled at the first time Ti may be referred to as OUTCp(Ti) and OUTC"(Ti). For example, the summation unit 340 may comprise a sampling block (not shown) for sampling the signals received at the first input and the second input at any given time, and a storage block (not shown) in which the sampled signals may be stored for a time period. For example, the first and second signals which were sampled and stored at a first time may be stored whilst the summation unit 340 samples a third and a fourth signal at a second time.

[00106] Next, whilst the apparatus 300 is still receiving the signals INAp and INA" at the first input terminal and second input terminal respectively, the controller may be configured to operate the primary switching arrangement 310 in the second switch mode and the secondary switching arrangement 330 in the second switch mode.

[00107] Operating the primary switching arrangement 310 in the second switch mode, the signal output at the first output is given by INBp = INA" and the signal output at the second output is given by 1NB" = 1NAp. Therefore, the outputs from the signal processing block 320 will be given by OUTBp = fp(INA") and OUTB" = f"(INAp). Furthermore, as the secondary switching arrangement 330 is configured in the second switch mode, the signal OUTCp = OUTB" = f1(1NAp) and the signal OUTC" = OUTBp = fp(INA").

[00108] The summation unit 340 may then sample the signals OUTCp and OUTC" at a second time T2. The signals sampled at the second time Ty may be referred to as OUTCp(T2) and OUT Cm (T2) . [00109] After the summation unit 340 has sampled the signals OUTCp(T2) and OUTCp(T2), the summation unit 340 may perform a sum of the signals sampled and stored at the first time with the signals sampled at the second time, and output the summed signals at the first output and second output of the summation block. For example, the summation block 340 may perform this sum by storing the signals sampled at the second time at the first input on top of the signals sampled at the first time at the first input, and storing the signals sampled at the second time at the second input on top of the signals sampled at the first time at the second input. That is, the summation bock may perform the sum of the sampled signals from time points T1 and T2, and output the summed samples at the first output and the second output, such that the signal output at the first output of the summation block 340 is given by OUTAp = OUT Cp(T2) + OUT Cp(Ti) = f"(IN Ap) + fp(I N Ap), and the signal output at the second output of the summation block 340 is given by OUTA, = OUTC,(T2) OUTC"(TO = fp(INAn)± f"(I N An).

[00110] As was described in relation to Figures 1 and 2, the input signals I NAp and IN An may be written in terms of their differential and common mode components, such that IN Ap = JNAcm INAd and INA" = INAd. The output signals hence become OUTAp = f"(IN Ap) + fp(INAp) =fn (IN Ac.," IN Ad) + fp(I N Atm + 12 N A d) and OUTA" = fp(IN An) + f"(IN An) = fp (INAcm IN Ad) + f"(INAcm I NAd).

[00111] Therefore, as the functions fp and f" are additive functions which satisfy the relationship [(A + = [(A) + [(B), the common mode input signal is substantially cancelled in the differential output signal, resulting in a differential output signal OUTAd which is independent of the common mode input signal INAcm: OUT Ad = OUT Ap -OUT An = (f" (IN Acm -mAcrn + -2INAd + -/NA) 1 1 + fp (Mk, -IN Ann + INAd + 11'144d)) = (.1.11( 1N Ad) + fp(1N A)) [00112] Figure 4 depicts an example of the apparatus 400 for reducing the common mode to differential error in an additive function block 420 according to Figure 3, wherein the secondary switching arrangement 430 and the summation block 440 is implemented by a fully differential switched capacitor integrator circuit 460 according to the example of Figure 1 or Figure 2.

[00113] For example, the primary switching arrangement 410 may be substantially the same as the primary switching arrangement 310 described in relation to Figure 3, and the additive function block 420 may be substantially the same as the additive function block 320 described in relation to Figure 3. The secondary switching arrangement 430 may be substantially the same as the secondary switching arrangement 330 described in relation to Figure 3, or the switching arrangements 102 or 202 described in relation to Figures 1 and 2 respectively. The switching arrangement 430 and the summation block 440 may be collectively substantially the same as a fully differential switched capacitor integrator circuit 100 of Figure 1.

[00114] The controller 450 may be configured to control the operation of the primary switching arrangement 410 and the fully differential switched capacitor integrator 460. For example, the controller 450 may be configured to operate the primary switching arrangement 410 in a first switch mode and a second switch mode, as described in relation to Figure 3. Furthermore, the controller 450 may be configured to operate the fully differential switched capacitor integrator 460 in the first mode, the second mode or the third mode, as was described in relation to Figures 1 and 2.

[00115] In use, in order to reduce the common mode input signal (as described in relation to Figure 3), the apparatus 400 may receive a first input signal /NAp at a first input terminal and a second input signal [NA,, at a second input terminal. The controller 450 may configure the primary switching arrangement 410 in the first switch mode and the fully differential switched capacitor integrator 460 in the first mode for a first time period. This step effectively corresponds to the sampling of the signals by the summation block described in relation to Figure 3, in that a first input signal and a second input signal received a the fully differential switch capacitor integrator 460 are stored across a first capacitor and a second capacitor.

[00116] Next, the controller 450 may configure the fully differential switched capacitor integrator 450 to operate in the second mode for a second time period. This is equivalent to the storing of the sampled signals in a storage block, described in relation to Figure 3, as the sampled signals initially stored across the first capacitor and the second capacitor are stored across the third capacitor and the fourth capacitor of the fully differential switched capacitor integrator 460.

[00117] Finally, the controller 450 may operate the primary switching arrangement 410 in the second switch mode and the fully differential switched capacitor integrator 460 in the third mode for a third time period. This results in the signals received at the fully differential switched capacitor integrator 460 being summed on top of the signals previously stored in the third and fourth capacitors. Consequentially, the common mode input signal is cancelled in the differential output signal, OUTAd = (OUTAp -OUTA,), which is output across a first output and a second output of the fully differential switched capacitor integrator 460.

[00118] Alternatively, the common mode input signal may be reduced by the controller 450 operating the primary switching arrangement 410 in the second switch mode and the fully differential switched capacitor integrator 460 in the third mode for a third time period. Then, the controller 450 operates the primary switching arrangement 410 in the first switch mode and the fully differential switched capacitor integrator 460 in the first mode for a first time period. Finally, the controller 450 operates the fully differential switched capacitor integrator 460 in the second mode for a second time period.

[00119] An example of a signal processing block according to either Figure 3 or Figure 4, is shown in Figure 5.

[00120] In this example, the signal processing block 500 takes the form of a precision circuit that perform current-to-voltage amplification. In this case, the mismatch in the functions fp and fn such that fp # fn may be due to the mismatch in the capacitors Cl and 02.

[00121] The circuits described above may include more components than shown. For example, power supplies to the differential amplifiers are not shown but may be included.

[00122] Input signal can be voltage signals or current signals. For example, the input signal may be a quantum tunnelling current.

[00123] A computer-readable medium may comprise a computer-readable description of circuitry as described herein. The computer readable medium may be a non-transitory computer readable medium.

[00124] A circuit or system described above may be implemented on a chip, a computer, a tablet, a mobile phone or any other such device. Moreover, a description of a circuit or system described above may be provided on a computer readable medium. Such a computer readable medium may then be used, for example, to instruct a machine to produce the circuit or system.

[00125] It will be appreciated that embodiments of the present invention can be realised in the form of hardware, software or a combination of hardware and software. Any such software may be stored in the form of volatile or non-volatile storage such as, for example, a storage device like a ROM, whether erasable or rewritable or not, or in the form of memory such as, for example, RAM, memory chips, device or integrated circuit 100s or on an optically or magnetically readable medium such as, for example, a CD, DVD, magnetic disk or magnetic tape. It will be appreciated that the storage devices and storage media are embodiments of machine-readable storage that are suitable for storing a program or programs that, when executed, implement embodiments of the present invention. Accordingly, embodiments provide a program comprising code for implementing a system or method as claimed in any preceding claim and a machine readable storage storing such a program. Still further, embodiments of the present invention may be conveyed electronically via any medium such as a communication signal carried over a wired or wireless connection and embodiments suitably encompass the same.

[00126] Features, integers, characteristics, compounds, chemical moieties or groups described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive. The invention is not restricted to the details of any foregoing examples. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims (15)

1. Claims 1. A fully differential switched capacitor integrator circuit having a first input terminal and a second input terminal, the circuit operable in a first mode, a second mode and a third mode, the circuit comprising: a switching arrangement configurable to operate in a first switch mode and a second switch mode, wherein, in the first switch mode, the first input terminal is connected to a first output of the switching arrangement, and the second input terminal is connected to a second output of the switching arrangement; and wherein, in the second switch mode, the first input terminal is connected to the second output of the switching arrangement, and the second input terminal is connected to the first output of the switching arrangement; a fully differential amplifier for amplifying a differential signal; a first capacitor connected in series between the first output of the switching arrangement and a positive input of the fully differential amplifier, and a second capacitor connected in series between the second output of the switching arrangement and a negative input of the fully differential amplifier; a third capacitor connected in parallel to the positive input of the fully differential amplifier and a negative output of the fully differential amplifier and a fourth capacitor connected in parallel to the negative input of the fully differential amplifier and a positive output of the fully differential amplifier; a first switch connected in series between the third capacitor and the negative output of the fully differential amplifier and a second switch connected in series between the fourth capacitor and the positive output of the fully differential amplifier; a third switch connected in parallel to the third capacitor, the first switch and the fully differential amplifier, and a fourth switch connected in parallel to the fourth capacitor, the second switch and the fully differential amplifier; wherein, in the first mode: the switching arrangement is configured in the first switch mode to connect the first capacitor to the first input terminal and to connect the second capacitor to the second input terminal, the first switch and the second switch are open, and the third switch and the fourth switch are closed; wherein, in the second mode: the first capacitor is disconnected from the first input terminal and the second capacitor is disconnected from the second input terminal; the first switch and the second switch are closed, the third switch and the fourth switch are open, and in use, a first junction between the first output of the switching arrangement and the first capacitor, and a second junction between the second output of the switching arrangement and the second capacitor, are both held at a reference potential; and wherein, in the third mode: the switching arrangement is configured in the second switch mode to connect the first capacitor to the second input terminal and to connect the second capacitor to the first input terminal, the first switch and the second switch are closed, and the third switch and the fourth switch are open.
2. 2. The fully differential switched capacitor integrator circuit of claim 1, wherein the circuit is further operable in a reset mode in which: a third junction between the third capacitor and the first switch is held at a second reference potential; and a fourth junction between the fourth capacitor and the second switch is held at the second reference potential.
3. 3. The fully differential switched capacitor integrator circuit of claim 2, wherein in the reset mode, the first switch and the second switch are both open, and the third switch and the fourth switch are both closed.
4. 4. The fully differential switched capacitor integrator circuit of any preceding claim, further comprising: a controller configured to operate the circuit in the first mode, the second mode or the third mode.
5. 5. The fully differential switched capacitor integrator circuit of claim 4, wherein the controller is further configured to: sequentially operate the circuit in the first mode for a first time period, the second mode for a second time period and the third mode for a third time period.
6. 6. The fully differential switched capacitor integrator circuit of claim 4, wherein the controller is further configured to: sequentially operate the circuit in the third mode for a first time period, the first mode for a second time period and the second mode for a third time period.
7. 7. A method of reducing a differential to common mode error in an input differential signal using the fully differential switched capacitor integrator circuit according to any preceding claim, the method comprising: whilst receiving the input differential signal at the first input terminal and the second input terminal: operating the fully differential switched capacitor integrator circuit in the first mode for a first time period; operating the fully differential switched capacitor integrator circuit in the second mode for a second time period in which the reference terminal is connected to a reference potential; and operating the fully differential switched capacitor integrator circuit in the third mode for a third time period;
8. 8. The method of claim 7, wherein an amplified differential signal with a reduced common mode to differential error is output across the positive output and negative output of the fully differential amplifier when the circuit is operating in the third mode.
9. 9. An apparatus for reducing differential to common mode error in a signal processing block, the signal processing block for implementing an additive function to a first signal and to a second signal, the apparatus comprising: a fully differential switched capacitor integrator circuit according to any preceding claim, the first input terminal of the fully differential switched capacitor integrator circuit for connection to a first output terminal of the signal processing block, the second input terminal of the fully differential switched capacitor integrator circuit for connection to a second output terminal of the signal processing block; a primary switching arrangement configurable to operate in a third switch mode and a fourth switch mode, wherein, in the third switch mode, a first input terminal of the primary switching arrangement is connected to a first output terminal of the primary switching arrangement, and a second input terminal of the primary switching arrangement is connected to a second output terminal of the primary switching arrangement; and wherein, in the fourth switch mode, the first input terminal of the primary switching arrangement is connected to the second output terminal of the primary switching arrangement, and the second input terminal of the primary switching arrangement is connected to the first output terminal of the primary switching arrangement; wherein the first output terminal of the primary switching arrangement is for connection to a first input terminal of the signal processing block and the second output terminal of the primary switching arrangement is for connection to a second input terminal of the signal processing block; and a controller configured to: operate the fully differential switched capacitor integrator circuit in the first mode and the primary switching arrangement in the third switch mode for a first time period; operate the fully differential switched capacitor integrator circuit in the second mode for a second time period; and operate the fully differential switched capacitor integrator circuit in the third mode and the primary switching arrangement in the fourth switch mode for a third time period.
10. 10. An apparatus according to claim 9, further comprising: the signal processing block; wherein the signal processing block is connected between the first and the second output terminals of the primary switching arrangement and the first and the second input terminals of the fully differential switched capacitor integrator circuit and configured to, in use, implement the additive function to a first signal received from the first output terminal of the primary switching arrangement and a second signal received from the second output terminal of the primary switching arrangement.
11. 11. The apparatus of claim 10, wherein the signal processing block is configured to perform current-to-voltage amplification
12. 12. A method of reducing the common mode to differential error in a signal processing block using the apparatus of any of claims 9 to 11, the method comprising: whilst receiving an input differential signal at the first input terminal and the second input terminal of the primary switching arrangement: operating the fully differential switched capacitor integrator circuit in the first mode and the primary switching arrangement in the third switch mode for a first time period; operating the fully differential switched capacitor integrator circuit in the second mode for a second time period; and operating the fully differential switched capacitor integrator circuit in the third mode and the primary switching arrangement in the fourth switch mode for a third time period.
13. 13. The method of claim 12, wherein the input differential signal is a current signal.
14. 14. A computer-readable medium having instructions stored thereon that, when executed by a processor, causes the processor to perform a method according to any of claims 7-8 or 1213.
15. 15. A computer readable medium comprising a computer readable description of the circuitry of any of claims ito 11.