CN206990625U - A kind of relatively low accelerometer capacitive detection circuit of power consumption - Google Patents
A kind of relatively low accelerometer capacitive detection circuit of power consumption Download PDFInfo
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- CN206990625U CN206990625U CN201720864903.3U CN201720864903U CN206990625U CN 206990625 U CN206990625 U CN 206990625U CN 201720864903 U CN201720864903 U CN 201720864903U CN 206990625 U CN206990625 U CN 206990625U
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Abstract
The utility model discloses a kind of relatively low accelerometer capacitive detection circuit of power consumption, the circuit includes：Modulator structure module；Capacitance compensation array module；D/A converting circuit module；Input Common-mode compensation circuitry module, wherein, capacitance compensation array is connected to the front end of modulator block first order switched-capacitor integrator, D/A converting circuit is connected to first order switched-capacitor integrator under the control that one-bit digital exports, input the output of Common-mode compensation circuitry sampling first order switched-capacitor integrator, try to achieve and the input of first order switched-capacitor integrator is fed back to after common-mode voltage eliminate its common mode input deviation, solve existing accelerometer capacitive detection circuit presence is easily influenceed by environment and oneself factor, and power consumption is higher, it is not easy to the technical problem of processing, it is reasonable to realize circuit design, it is not easily susceptible to environment and the influence of itself, testing result is accurate, and the technique effect that power consumption is relatively low.
Description
Technical field
Accelerometer research field is the utility model is related to, in particular it relates to the accelerometer electric capacity that a kind of power consumption is relatively low
Detect circuit.
Background technology
Current acceleration meter is widely used in automobile, industrial automation, Aero-Space and other various fields.Compared to pressure
Resistance accelerometer, capacitive accelerometer are popular with its low temperature sensitivity.In addition, with analog acceleration meter phase
Than there is digital accelerometer the advantage that error correction and compensation are directly carried out without extra ADC cans to be selected as main flow
Select.
Fig. 2 is traditional open loop accelerometer capacitive detection circuit, is had in traditional accelerometer capacitive detection circuit
The voltage digitizer (V/D) of two important modules, capacitance-voltage converter (C/V) and following stage.But this group
Close there is three it is main the shortcomings that：First, be converted to this mode of voltage and be easy to by environmental factor (such as temperature), Yi Ji electricity
The influence of road self-noise；Second, in most capacitive detection circuit, C/V modules all consume considerable power consumption, because
Needing larger bandwidth and very high gain for it, this is that low power dissipation design is highly undesirable to realize the output of low noise.The
Three, due to that can have big process deviation in MEMS manufacturing processes, the basic electric capacity of transducer sensitive structure might have very
Big change, this will design to front end C/V and bring very big problem.
In summary, present inventor has found above-mentioned skill during the application utility model technical scheme is realized
Following technical problem at least be present in art：
In the prior art, existing accelerometer capacitive detection circuit is present easily by environment and oneself factor shadow
Ring, the higher technical problem of power consumption.
Utility model content
The utility model provides a kind of relatively low accelerometer capacitive detection circuit of power consumption, solves existing acceleration
Meter capacitive detection circuit exists and easily influenceed by environment and oneself factor, and power consumption is higher, and it is reasonable to realize circuit design, is not easy
By environment and itself influenceed, testing result is accurate, and the technique effect that power consumption is relatively low.
In order to solve the above technical problems, this application provides a kind of relatively low accelerometer capacitive detection circuit of power consumption, institute
Stating circuit includes：
Modulator structure module；Capacitance compensation array module；D/A converting circuit module；Input Common-mode compensation circuitry mould
Block, wherein, modulator structure module is used to the change of accelerometer electric capacity being converted to numeral output, capacitance compensation array module
For offsetting the imbalance of the basic electric capacity in accelerometer sensitive structure and error, D/A converting circuit module is used to realize one digit number
Word is output to the feedback of first order switched-capacitor integrator, and input Common-mode compensation circuitry is used to eliminate first order switching capacity integration
The common mode input deviation of device；Capacitance compensation array is connected to the front end of modulator block first order switched-capacitor integrator,
D/A converting circuit is connected to first order switched-capacitor integrator under the control that one-bit digital exports, and inputs Common-mode compensation circuitry
The output of first order switched-capacitor integrator is sampled, tries to achieve the input that first order switched-capacitor integrator is fed back to after common-mode voltage
Eliminate its common mode input deviation.
Further, modulator structure module includes：Equivalent capacity Cs1, Cs2 of accelerometer sensitive structure, computing are put
Big device AMP1, AMP2, AMP3, comparator CMP, switch S1 ..., S30, electric capacity C1 ..., C14, correlated-double-sampling electric capacity Ch1,
Ch2, the first order integrator electric capacity Cf1, Cf2.
Further, capacitance compensation array module includes：Switch S31, S32 and electric capacity Cc1, Cc2.
Further, D/A converting circuit module includes：Switch S33 ..., S40 and electric capacity Cb1, Cb2.
Further, input Common-mode compensation circuitry module includes：Single end operational amplifier AMP4, switch S41 ..., S50,
Electric capacity C15, C16, Cfb1, Cfb2.
Further, operational amplifier A MP1 and switch S1 ..., S8 and electric capacity Cs1, Cs2, Ch1, Ch2, Cf1, Cf2 structure
Into first order switched-capacitor integrator；Operational amplifier A MP2 and switch S9 ..., S16 and electric capacity C1, C2, C11, C12 form
Second level switched-capacitor integrator；Operational amplifier A MP3 and switch S17 ... S24 and electric capacity C3, C4, C13, C14 form the
Three step switch capacitance integrator；Switch S25 ..., S30 and electric capacity C5 ..., C10 form summing circuit；Comparator CMP is used as one
Position quantizer；Switch S31, S32 and electric capacity Cc1, Cc2 formation base capacitor compensating circuit；Switch S33 ..., S40 and electric capacity
Cb1, Cb2 form the negative-feedback that modulator is output to first switch electric capacity；Operational amplifier A MP4 with switch S41 ..., S50 and
Electric capacity C15, C16, C17, Cfb1, Cfb2 form input Commom-mode feedback circuit.
Further, in modulator structure module, switch S1 one end connection reference voltage Vref, the other end is linked to node
C；Switch S2 one end is linked to node C, and the other end is with being connected to the common mode of circuit or ground；Switch S4 is connected to node A together
Between mould ground, switch S3 is connected between node B and common mode ground；Electric capacity Cs1 is connected between node C and node A, electric capacity Cs2
It is connected between node C and node B, electric capacity Ch1 is connected between node A and operational amplifier A MP1 negative input end, electric capacity
Ch2 is connected between node B and operational amplifier A MP1 positive input terminal；Switch S5 is connected between node B and node N1,
Switch S6 is connected between node A and node N2；Switch S7 be connected to node N1 and operational amplifier A MP1 positive input terminal it
Between, switch S8 is connected between operational amplifier A MP1 negative input end and node N2；Integrating capacitor Cf1 is connected to operation amplifier
Between device AMP1 positive input terminal and negative output terminal, Cf2 be connected to operational amplifier A MP1 negative input end and positive output end it
Between；Switch S11 is connected between node F and node addp1, and switch S12 is connected between node E and addn1；S9 is switched to connect
It is connected between node addn1 and common mode ground, switch S10 is connected between node addp1 and common mode ground；Switch S13 connections
Between node N3 and common mode ground, switch S14 is connected between node N4 and common mode ground；Switch S15 is connected to node N3 and fortune
Between the positive input terminal for calculating amplifier AMP2, switch S16 is connected to node N4 and operational amplifier A MP2 negative input end
Between；Electric capacity C11 is connected across between operational amplifier A MP2 negative input end and positive output end, and C12 is connected across operational amplifier
Between AMP2 positive input output end and negative output terminal；Switch S17 is connected to operational amplifier A MP2 negative output terminals and node
Between addn2, switch S18 is connected between operational amplifier A MP2 positive output end and node addn2；Electric capacity C3 is connected to section
Between point addp2 and node N6, C4 is connected between node addn2 tie points and node N5；Switch S19 is connected to node
Between addn2 and common mode ground, switch S20 is connected between addp2 tie points and common mode ground；Switch S21 be connected to node N5 with
Between common mode ground, switch S22 is connected between node N6 and common mode ground；Switch S23 is connected to node N5 and operational amplifier
Between AMP3 positive input terminal, switch S24 is connected between node N6 and operational amplifier A MP3 negative input end；Electric capacity C13
Operational amplifier A MP3 negative input end and positive output end are connected across, C14 is connected across operational amplifier A MP3 positive input output
End and negative output terminal；Switch S25 is connected to node N7 and operational amplifier A MP3 negative output terminal, and switch S26 is connected to computing
Between amplifier AMP3 positive output ends and node N8；Switch S27 is connected between node N7 and common mode ground, and switch S28 is connected to
Between node N8 and common mode ground；Electric capacity C6 is connected between node N7 and node N9, and electric capacity C5 is connected to out node N8 and node
Between N10；Switch S29 is connected between node N9 and common mode ground, and switch S30 is connected between node N10 and common mode ground；Electricity
Hold C7 to be connected between node addp1 and node N10, C8 is connected between addn1 and node N9；Electric capacity C9 is connected to node
Between addp2 and node N10, C10 is connected between addn2 and node N9.
Further, in capacitance compensation array module, switch S31 is connected between reference voltage Vref end and node N11；
S32 is switched with being connected to node N11 and common mode or between ground；Capacitance compensation array Cc1 be connected to node N11 and node A it
Between, Cc2 is connected between node N11 and node B.
Further, in D/A converting circuit module, switch S33 be connected to the end of reference voltage Vref 1 and node N12 it
Between, by output Y2 controls, switch S34 is connected between the end of reference voltage Vref 2 and node N12, by output Y1 controls；Switch
Between S37 connecting nodes N12 and node N14, switch S39 is connected between node N14 and common mode ground；Electric capacity Cb2 is connected to section
Between point N14 and node B；Switch S35 is connected between the end of reference voltage Vref 2 and node N13, by output Y2 controls；Switch
S36 is connected between the end of reference voltage Vref 1 and node N13, is controlled by output signal Y1；Switch S38 be connected to node N13 with
Between node N15, switch S40 is connected between node N15 and common mode ground；Electric capacity Cb1 be connected to node N15 and node A it
Between.
Further, input in Common-mode compensation circuitry module, switch S47 is connected to node N16 with common mode, electric capacity C15
It is connected between node N16 and node N19, electric capacity C16 is connected between node N16 and node N18, and switch S48 is connected to save
Point N16 and operational amplifier A MP4 negative input end；Switch S49 concatenation operation amplifiers AMP4 negative input end and node N17
Between, switch S50 is connected between node N17 and operational amplifier A MP4 positive input terminal；Electric capacity C17 is connected to node N17
With operational amplifier A MP4 output end；Between switching S41 connecting nodes N20 and node N18, switch S42 is connected to node N19
Between node N20；Between switching S45 connecting nodes N18 and node F, switch S46 is connected between node N19 and node E；
Switch S43 is connected between node N20 and node N21, and switch S44 is connected between node N21 and common mode ground；Electric capacity Cfb1 connects
It is connected between node N21 and A, electric capacity Cfb2 is connected between node N21 and node B.
One or more technical schemes that the application provides, have at least the following technical effects or advantages：
New integrated detection circuit in the application, by the way that sensitive structure is combined to solve with Sigma-Delta modulator
The problem of certainly above-mentioned, the differential capacitance of sensitive structure are used as the sampling capacitance of Sigma-Delta modulator；The change of differential capacitance
Change the error signal being directly changed into Sigma-Delta loops, thus be no longer needed for here using voltage as in conversion
It is situated between；The structure also has another benefit, and front end amplifier is only a simple integrated transporting discharging, without being to need to consume greatly
The C/V of power consumption is measured, therefore, effectively reduces the power consumption of system；Problem is obtained in order to solve front end input common mode simultaneously, this Shen
It please it is also proposed an appropriate input common mode compensation feedback circuit；So solves existing accelerometer capacitance detecting electricity
Road presence is easily influenceed by environment and oneself factor, and power consumption is higher, is not easy to the technical problem of processing, and then realizes electricity
Road is reasonable in design, is not easily susceptible to environment and the influence of itself, and testing result is accurate, and the technique effect that power consumption is relatively low.
Brief description of the drawings
Accompanying drawing described herein is used for providing further understanding the utility model embodiment, forms the one of the application
Part, the restriction to the utility model embodiment is not formed；
Fig. 1 is integrated three rank electric charge Sigma Delta capacitive detection circuit connection diagrams；
Fig. 2 traditional Si gma Delta accelerometer capacitive detection circuit schematic diagrames；
Fig. 3 is digital accelerometer capacitive detection circuit application example schematic diagram；
Fig. 4 is the time diagram of Non-Overlapping Clock (non-overlapping clock) requirements.
Embodiment
The utility model provides a kind of relatively low accelerometer capacitive detection circuit of power consumption, solves existing acceleration
Meter capacitive detection circuit exists and easily influenceed by environment and oneself factor, and power consumption is higher, and it is reasonable to realize circuit design, is not easy
By environment and itself influenceed, testing result is accurate, and the technique effect that power consumption is relatively low.
In order to be more clearly understood that above-mentioned purpose of the present utility model, feature and advantage, below in conjunction with the accompanying drawings and tool
The utility model is further described in detail body embodiment.It should be noted that in the case where not conflicting mutually,
Feature in embodiments herein and embodiment can be mutually combined.
Many details are elaborated in the following description in order to fully understand the utility model, still, this practicality
It is new to be implemented using other different from the other modes in the range of being described herein, therefore, protection of the present utility model
Scope is not limited by following public specific embodiment.
Fig. 1 is refer to, this application provides integrated accelerometer capacitive detection circuit of the present utility model, by that will accelerate
Degree meter sensitive structure is combined with Sigma-Delta modulator, and the differential capacitance of sensitive structure is used as Sigma-Delta modulation
The sampling capacitance of device, its specific circuit connection are as shown in Figure 1.Fig. 1 can be divided into four modules, feedover what is summed using three ranks
The module of Sigma-Delta modulator structure is 1.；Capacitance compensation array module is 2.；Numeral output feeds back to first order integrator
D/A converting circuit module is 3.；Input Common-mode compensation circuitry module 4..Module 1. in it is equivalent comprising accelerometer sensitive structure
Electric capacity【Cs1】【Cs2】, amplifier【AMP1】【AMP2】【AMP3】And comparator【CMP】And switch【S1】…【S30】, electric capacity
【C1】…【C14】, correlated-double-sampling electric capacity【Ch1】【Ch2】, first order integrator electric capacity【Cf1】【Cf2】, module 2. in include
Switch【S31】【S32】And electric capacity【Cc1】【Cc2】, module 3. in comprising switch【S33】…【S40】And electric capacity【Cb1】
【Cb2】, module 4. in include single-ended amplifier【AMP4】, switch【S41】…【S50】, electric capacity【C15】【C16】【Cfb1】【Cfb2】.
Two-phase non-overlapp-ing clock signal【φ1】【φ2】。
Amplifier【AMP1】With switch【S1】…【S8】, electric capacity【Cs1】【Cs2】【Ch1】【Ch2】【Cf1】【Cf2】Form first
Level switched-capacitor integrator；Amplifier【AMP2】With switch【S9】…【S16】, electric capacity【C1】【C2】【C11】【C12】Form the second level
Switched-capacitor integrator；Amplifier【AMP3】With switch【S17】…【S24】, electric capacity【C3】【C4】【C13】【C14】Form ground three-level
Switched-capacitor integrator；Switch【S25】…【S30】, electric capacity【C5】…【C10】Form summing circuit；Comparator【CMP】As one
Position quantizer；Switch【S31】【S32】With electric capacity【Cc1】【Cc2】Formation base capacitor compensating circuit；Switch【S33】…【S40】
With electric capacity【Cb1】【Cb2】Form the negative-feedback that modulator is output to first switch electric capacity；Amplifier【AMP4】With switch【S41】…
【S50】, electric capacity【C15】【C16】【C17】【Cfb1】【Cfb2】Form input Commom-mode feedback circuit.
Circuit module 1. in, switch【S1】One end connects reference voltage【Vref】, the other end is linked to node【C】.Switch
【S2】One end is linked to node【C】, one end is with being connected to the common mode of circuit or ground.Switch【S4】It is connected to node【A】Together
Between mould ground, switch【S3】It is connected to node【B】Between common mode ground.Electric capacity【Cs1】It is connected to node【C】With node【A】It
Between, electric capacity【Cs2】It is connected to node【C】With node【B】Between, electric capacity【Ch1】It is connected to node【A】And amplifier【AMP1】It is negative
Between input, electric capacity【Ch2】It is connected to node【B】With amplifier【AMP1】Positive input terminal between.Switch【S5】It is connected to section
Point【B】With node【N1】Between, switch【S6】It is connected to node【A】With node【N2】Between.Switch【S7】It is connected to node
【N1】With amplifier【AMP1】Positive input terminal between, switch【S8】It is connected to amplifier【AMP1】Negative input end and node【N2】It
Between.Integrating capacitor【Cf1】It is connected to amplifier【AMP1】Positive input terminal and negative output terminal between,【Cf2】It is connected to amplifier
【AMP1】Negative input end and positive output end between.Switch【S11】It is connected to node【F】With node【addp1】Between, switch
【S12】It is connected to node【E】With【addn1】Between.Switch【S9】It is connected to node【addn1】Between common mode ground, switch
【S10】It is connected to node【addp1】Between common mode ground.Switch【S13】It is connected to node【N3】Between common mode ground, open
Close【S14】It is connected to node【N4】Between common mode ground.Switch【S15】It is connected to node【N3】With amplifier【AMP2】Positive input
Between end, switch【S16】It is connected to node【N4】With amplifier【AMP2】Negative input end between.Electric capacity【C11】It is connected across
Amplifier【AMP2】Negative input end and positive output end between,【C12】It is connected across amplifier【AMP2】Positive input output end with it is negative defeated
Go out between end.Switch【S17】It is connected to amplifier【AMP2】Negative output terminal and node【addn2】Between, switch【S18】It is connected to fortune
Put【AMP2】Positive output end and node【addn2】Between.Electric capacity【C3】It is connected to node【addp2】With node【N6】Between,
【C4】It is connected to node【addn2】Tie point and node【N5】Between.Switch【S19】It is connected to node【addn2】With common mode
Between, switch【S20】It is connected to【addp2】Between tie point and common mode ground.Switch【S21】It is connected to node【N5】With common mode
Between, switch【S22】It is connected to node【N6】Between common mode ground.Switch【S23】It is connected to node【N5】With amplifier【AMP3】
Positive input terminal between, switch【S24】It is connected to node【N6】With amplifier【AMP3】Negative input end between.Electric capacity【C13】Across
It is connected on amplifier【AMP3】Negative input end and positive output end,【C14】Transboundary in amplifier【AMP3】Positive input output end with it is negative defeated
Go out end.Switch【S25】It is connected to node【N7】With amplifier【AMP3】Negative output terminal, switch【S26】It is connected to amplifier【AMP3】
Positive output end and node【N8】Between.Switch【S27】It is connected to node【N7】Between common mode ground, switch【S28】It is connected to section
Point【N8】Between common mode ground.Electric capacity【C6】It is connected to node【N7】With node【N9】Between, electric capacity【C5】It is connected to out node
【N8】With node【N10】Between.Switch【S29】It is connected to node【N9】Between common mode ground, switch【S30】It is connected to node
【N10】Between common mode ground.Electric capacity【C7】It is connected to node【addp1】With node【N10】Between,【C8】It is connected to【addn1】
With node【N9】Between.Electric capacity【C9】It is connected to node【addp2】With node【N10】Between,【C10】It is connected to【addn2】With
Node【N9】Between.
Circuit module 2. in, switch【S31】It is connected to reference voltage【Vref】With node【N11】Between.Switch【S32】Even
It is connected on node【N11】And common mode or ground between.Capacitance compensation array【Cc1】It is connected to node【N11】With node【A】It
Between,【Cc2】It is connected to node【N11】With node【B】Between.
Circuit module 3. in, switch【S33】It is connected to reference voltage【Vref1】With node【N12】Between, exported【Y2】
Control, switch【S34】It is connected to reference voltage【Vref2】With node【N12】Between, exported【Y1】Control.Switch【S37】Even
Connect node【N12】With node【N14】Between, switch【S39】It is connected to node【N14】Between common mode ground.Electric capacity【Cb2】Connection
In node【N14】With node【B】Between.Switch【S35】It is connected to reference voltage【Vref2】With node【N13】Between, exported
【Y2】Control.Switch【S36】It is connected to reference voltage【Vref1】With node【N13】Between, by output signal【Y1】Control.Open
Close【S38】It is connected to node【N13】With node【N15】Between, switch【S40】It is connected to node【N15】Between common mode ground.Electricity
Hold【Cb1】It is connected to node【N15】With node【A】Between.
Circuit module 4. in, switch【S47】It is connected to node【N16】With common mode, electric capacity【C15】It is connected to node
【N16】With node【N19】Between, electric capacity【C16】It is connected to node【N16】With node【N18】Between, switch【S48】It is connected to
Node【N16】And amplifier【AMP4】Negative input end.Switch【S49】Connect amplifier【AMP4】Negative input end and node【N17】
Between, switch【S50】It is connected to node【N17】With amplifier【AMP4】Positive input terminal between.Electric capacity【C17】It is connected to node
【N17】With amplifier【AMP4】Output end.Switch【S41】Connecting node【N20】With node【N18】Between, switch【S42】Connection
In node【N19】With node【N20】Between.Switch【S45】Connecting node【N18】With node【F】Between, switch【S46】Connection
In node【N19】With node【E】Between.Switch【S43】It is connected to node【N20】With node【N21】Between, switch【S44】Even
It is connected on node【N21】Between common mode ground.Electric capacity【Cfb1】It is connected to node【N21】With【A】Between, electric capacity【Cfb2】It is connected to
Node【N21】With node【B】Between.
Digital accelerometer capacitive detection circuit of the present utility model, it is necessary to by it is outside produce stable direct current supply voltage and
Clock signal, after detecting processing of circuit, acceleration signal is converted directly into data serial signal output, in rear class
Down-sampled and digital filtering is completed in digital circuit, and digital compensation can be done to result, in the processing Jing Guo digital circuit
After compensation, back can be directly to single-chip microcomputer or host computer, be read data signal by them.As their acceleration signals
Data source.Circuit block diagram as shown in Figure 3, the sequential relationship of its used two-phase non-overlapp-ing clock are as shown in Figure 4.
Technical scheme in above-mentioned the embodiment of the present application, at least has the following technical effect that or advantage：
New integrated detection circuit in the application, by the way that sensitive structure is combined to solve with Sigma-Delta modulator
The problem of certainly above-mentioned, the differential capacitance of sensitive structure are used as the sampling capacitance of Sigma-Delta modulator；The change of differential capacitance
Change the error signal being directly changed into Sigma-Delta loops, thus be no longer needed for here using voltage as in conversion
It is situated between；The structure also has another benefit, and front end amplifier is only a simple integrated transporting discharging, without being to need to consume greatly
The C/V of power consumption is measured, therefore, effectively reduces the power consumption of system；Problem is obtained in order to solve front end input common mode simultaneously, this Shen
It please it is also proposed an appropriate input common mode compensation feedback circuit；So solves existing accelerometer capacitance detecting electricity
Road presence is easily influenceed by environment and oneself factor, and power consumption is higher, is not easy to the technical problem of processing, and then realizes electricity
Road is reasonable in design, is not easily susceptible to environment and the influence of itself, and testing result is accurate, and the technique effect that power consumption is relatively low.
Although having been described for preferred embodiment of the present utility model, those skilled in the art once know substantially
Creative concept, then other change and modification can be made to these embodiments.So appended claims are intended to be construed to wrap
Include preferred embodiment and fall into having altered and changing for the scope of the utility model.
Obviously, those skilled in the art can carry out various changes and modification without departing from this practicality to the utility model
New spirit and scope.So, if these modifications and variations of the present utility model belong to the utility model claims and
Within the scope of its equivalent technologies, then the utility model is also intended to comprising including these changes and modification.
Claims (5)
1. the relatively low accelerometer capacitive detection circuit of a kind of power consumption, it is characterised in that the circuit includes：
Modulator structure module, capacitance compensation array module, D/A converting circuit module, input Common-mode compensation circuitry module；Its
In, modulator structure module is used to the change of accelerometer electric capacity being converted to numeral output, and capacitance compensation array module is used for
The imbalance of basic electric capacity and the error in accelerometer sensitive structure are offset, D/A converting circuit module is used to realize that one-bit digital is defeated
Go out the feedback to first order switched-capacitor integrator, input Common-mode compensation circuitry is used to eliminate first order switched-capacitor integrator
Common mode input deviation；Capacitance compensation array is connected to the front end of modulator block first order switched-capacitor integrator, digital-to-analogue
Change-over circuit is connected to first order switched-capacitor integrator, input Common-mode compensation circuitry sampling under the control that one-bit digital exports
The output of first order switched-capacitor integrator, try to achieve and the input of first order switched-capacitor integrator is fed back to after common-mode voltage eliminate
Its common mode input deviation；Modulator structure module includes：Equivalent capacity Cs1, Cs2 of accelerometer sensitive structure, computing
Amplifier AMP1, AMP2, AMP3, comparator CMP, switch S1 ..., S30, electric capacity C1 ..., C14, correlated-double-sampling electric capacity Ch1,
Ch2, the first order integrator electric capacity Cf1, Cf2；Capacitance compensation array module includes：Switch S31, S32 and electric capacity Cc1, Cc2；Number
Analog conversion circuit module includes：Switch S33 ..., S40 and electric capacity Cb1, Cb2；Input Common-mode compensation circuitry module includes：It is single-ended
Operational amplifier A MP4, switch S41 ..., S50, electric capacity C15, C16, Cfb1, Cfb2；Operational amplifier A MP1 and switch
S1 ..., S8 and electric capacity Cs1, Cs2, Ch1, Ch2, Cf1, Cf2 form first order switched-capacitor integrator；Operational amplifier A MP2
With switch S9 ..., S16 and electric capacity C1, C2, C11, C12 form second level switched-capacitor integrator；Operational amplifier A MP3 is with opening
Pass S17 ... S24 and electric capacity C3, C4, C13, C14 form third level switched-capacitor integrator；Switch S25 ..., S30 and electric capacity
C5 ..., C10 form summing circuit；Comparator CMP is used as a quantizer；Switch S31, S32 and electric capacity Cc1, Cc2 form base
Plinth capacitor compensating circuit；Switch S33 ..., S40 and electric capacity Cb1, Cb2 form modulator and be output to the negative anti-of first switch electric capacity
Feedback；Operational amplifier A MP4 and switch S41 ..., that S50 and electric capacity C15, C16, C17, Cfb1, Cfb2 form input common mode is negative anti-
Current feed circuit.
2. the relatively low accelerometer capacitive detection circuit of power consumption according to claim 1, it is characterised in that modulator structure
In module, switch S1 one end connection reference voltage Vref, the other end is linked to node C；Switch S2 one end is linked to node C, separately
One end is with being connected to the common mode of circuit or ground；Switch S4 is connected between node A and common mode ground, and switch S3 is connected to node B
Between common mode ground；Electric capacity Cs1 is connected between node C and node A, and electric capacity Cs2 is connected between node C and node B, electric capacity
Ch1 is connected between node A and operational amplifier A MP1 negative input end, and electric capacity Ch2 is connected to node B and operational amplifier
Between AMP1 positive input terminal；Switch S5 is connected between node B and node N1, switch S6 be connected to node A and node N2 it
Between；Switch S7 is connected between node N1 and operational amplifier A MP1 positive input terminal, and switch S8 is connected to operational amplifier
Between AMP1 negative input end and node N2；Integrating capacitor Cf1 is connected to operational amplifier A MP1 positive input terminal and negative output
Between end, Cf2 is connected between operational amplifier A MP1 negative input end and positive output end；Switch S11 is connected to node F and section
Between point addp1, switch S12 is connected between node E and addn1；Switch S9 is connected between node addn1 and common mode ground,
Switch S10 is connected between node addp1 and common mode ground；Switch S13 is connected between node N3 and common mode ground, is switched
S14 is connected between node N4 and common mode ground；Switch S15 be connected to node N3 and operational amplifier A MP2 positive input terminal it
Between, switch S16 is connected between node N4 and operational amplifier A MP2 negative input end；Electric capacity C11 is connected across computing and put
Between big device AMP2 negative input end and positive output end, the positive input output end that C12 is connected across operational amplifier A MP2 is defeated with bearing
Go out between end；Switch S17 is connected between operational amplifier A MP2 negative output terminals and node addn2, and switch S18 is connected to computing
Between amplifier AMP2 positive output end and node addn2；Electric capacity C3 is connected between node addp2 and node N6, C4 connections
Between node addn2 tie points and node N5；Switch S19 is connected between node addn2 and common mode ground, switchs S20 connections
Between addp2 tie points and common mode ground；Switch S21 is connected between node N5 and common mode ground, and switch S22 is connected to node N6
Between common mode ground；Switch S23 is connected between node N5 and operational amplifier A MP3 positive input terminal, and switch S24 is connected to
Between node N6 and operational amplifier A MP3 negative input end；Electric capacity C13 be connected across operational amplifier A MP3 negative input end with
Positive output end, C14 are connected across operational amplifier A MP3 positive input output end and negative output terminal；Switch S25 is connected to node N7
With operational amplifier A MP3 negative output terminal, switch S26 is connected between operational amplifier A MP3 positive output ends and node N8；Open
Close S27 to be connected between node N7 and common mode ground, switch S28 is connected between node N8 and common mode ground；Electric capacity C6 is connected to section
Between point N7 and node N9, electric capacity C5 is connected to out between node N8 and node N10；Switch S29 is connected to node N9 and common mode
Between ground, switch S30 is connected between node N10 and common mode ground；Electric capacity C7 is connected between node addp1 and node N10, C8
It is connected between addn1 and node N9；Electric capacity C9 is connected between node addp2 and node N10, and C10 is connected to addn2 and section
Between point N9.
3. the relatively low accelerometer capacitive detection circuit of power consumption according to claim 1, it is characterised in that capacitance compensation battle array
In row module, switch S31 is connected between reference voltage Vref end and node N11；Switch S32 is connected to node N11 and common mode
Between ground or ground；Capacitance compensation array Cc1 is connected between node N11 and node A, and Cc2 is connected to node N11 and node B
Between.
4. the relatively low accelerometer capacitive detection circuit of power consumption according to claim 1, it is characterised in that digital-to-analogue conversion electricity
In the module of road, switch S33 is connected between the end of reference voltage Vref 1 and node N12, and by output Y2 controls, switch S34 is connected to
Between the end of reference voltage Vref 2 and node N12, by output Y1 controls；Between switching S37 connecting nodes N12 and node N14, open
S39 is closed to be connected between node N14 and common mode ground；Electric capacity Cb2 is connected between node N14 and node B；Switch S35 is connected to
Between the end of reference voltage Vref 2 and node N13, by output Y2 controls；Switch S36 is connected to the end of reference voltage Vref 1 and node
Between N13, controlled by output signal Y1；Switch S38 is connected between node N13 and node N15, and switch S40 is connected to node
Between N15 and common mode ground；Electric capacity Cb1 is connected between node N15 and node A.
5. the relatively low accelerometer capacitive detection circuit of power consumption according to claim 1, it is characterised in that input common mode is mended
Repaying in circuit module, switch S47 is connected to node N16 with common mode, and electric capacity C15 is connected between node N16 and node N19,
Electric capacity C16 is connected between node N16 and node N18, and switch S48 is connected to the negative defeated of node N16 and operational amplifier A MP4
Enter end；Between the negative input end and node N17 that switch S49 concatenation operation amplifiers AMP4, switch S50 be connected to node N17 with
Between operational amplifier A MP4 positive input terminal；Electric capacity C17 is connected to node N17 and operational amplifier A MP4 output end；Open
Between closing S41 connecting nodes N20 and node N18, switch S42 is connected between node N19 and node N20；Switch S45 connections section
Between point N18 and node F, switch S46 is connected between node N19 and node E；Switch S43 is connected to node N20 and node
Between N21, switch S44 is connected between node N21 and common mode ground；Electric capacity Cfb1 is connected between node N21 and A, electric capacity
Cfb2 is connected between node N21 and node B.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110470861A (en) * | 2018-05-11 | 2019-11-19 | 中国科学院声学研究所 | A kind of MEMS capacitive accelerometer interface circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110470861A (en) * | 2018-05-11 | 2019-11-19 | 中国科学院声学研究所 | A kind of MEMS capacitive accelerometer interface circuit |
| CN110470861B (en) * | 2018-05-11 | 2020-12-25 | 中国科学院声学研究所 | MEMS capacitive accelerometer interface circuit |
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