CN107290566B - Basic capacitance compensation circuit for digital accelerometer - Google Patents
Basic capacitance compensation circuit for digital accelerometer Download PDFInfo
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- CN107290566B CN107290566B CN201710580696.3A CN201710580696A CN107290566B CN 107290566 B CN107290566 B CN 107290566B CN 201710580696 A CN201710580696 A CN 201710580696A CN 107290566 B CN107290566 B CN 107290566B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P15/125—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values by capacitive pick-up
Abstract
The invention discloses a basic capacitance compensation circuit for a digital accelerometer, which comprises: the accelerometer sensing structure, the switched capacitor integrator, the basic capacitor compensation array, the carrier signal generating circuit, the output common mode detection, the D/A1 and D/A2 digital-to-analog converters, the adders add1 and add2; the technical problems that the existing accelerometer foundation capacitance compensation circuit is unreasonable in design, foundation capacitance is difficult to produce and the arrangement of compensation capacitance is consistent are solved, and the technical effects that the sensitivity structure foundation capacitance and the capacitance compensation array are enabled to be offset to a certain extent and the fault tolerance is better compared with the traditional detection mode are achieved.
Description
Technical Field
The invention relates to the field of accelerometer research, in particular to a basic capacitance compensation circuit for a digital accelerometer.
Background
Accelerometers are currently used in a wide variety of automotive, industrial automation, aerospace, and other applications. Capacitive accelerometers are popular because of their low temperature sensitivity compared to piezoresistive accelerometers. In addition, the advantage of digital accelerometers over analog accelerometers in that they can be used directly for error correction and compensation without the need for an additional ADC is a dominant option.
The design of the basic capacitance compensation circuit of the accelerometer in the market is mainly to adopt a capacitance compensation array counteracting mode, as shown in fig. 3. However, due to the production process, the base capacitor is difficult to produce and the arrangement of the compensation capacitor is consistent. Compared with the traditional detection mode, the input common mode feedback method provided by the invention can allow the basic capacitance of the sensitive structure and the capacitance compensation array to be offset to a certain extent, and has better fault tolerance.
In summary, in the process of implementing the technical solution of the present invention, the present inventors have found that at least the following technical problems exist in the above technology:
in the prior art, the existing accelerometer basic capacitance compensation circuit is unreasonable in design, and the MEMS processing technology has the problem of large deviation.
Disclosure of Invention
The invention provides a basic capacitance compensation circuit for a digital accelerometer, which solves the problems of unreasonable design and large deviation of MEMS processing technology of the existing basic capacitance compensation circuit for the accelerometer, and realizes the technical effects of allowing the basic capacitance of a sensitive structure and a capacitance compensation array to be offset to a certain extent and having better fault tolerance compared with the traditional detection mode.
To solve the above technical problem, the present application provides a basic capacitance compensation circuit for a digital accelerometer, the circuit comprising:
the accelerometer sensing structure, the switched capacitor integrator, the basic capacitor compensation array, the carrier signal generating circuit, the output common mode detection, the D/A1 and D/A2 digital-to-analog converters, the adders add1 and add2; the accelerometer comprises a module (1) for compensating the basic capacitance of the accelerometer, and comprises a basic capacitance compensation array module and a carrier signal generation circuit module; the accelerometer capacitor is used as a module (2) of sampling capacitance of the switch capacitor integrator and comprises an accelerometer sensitive structure module, a switch capacitor integrator module and a carrier signal generation circuit module; the module (3) for detecting the output of the switched capacitor integrator and feeding back the output to the input of the switched capacitor integrator comprises an output common mode detection module, digital-to-analog converters D/A1 and D/A2 and adder add1 and add2 modules.
Further, the accelerometer sensitive structure is used for converting an external acceleration signal into a change of capacitance; the switch capacitor integrator is used for integrating the input difference signal; the carrier signal generating circuit is used for generating square wave signals to charge and discharge the accelerometer sensitive structure capacitance; the basic capacitance compensation array is used for compensating the basic capacitance of the accelerometer sensitive structure; the output common mode detection is used for detecting the output common modulus of the switched capacitor integrator; D/A1 and D/A2 are used to feed back the output common modulus of the switched capacitor integrator to the input of the switched capacitor integrator; add1 and add2 are used for adding and subtracting the electric charge by the adder and sending the result obtained by summation to the switched capacitor integrator.
Further, the compensation circuit specifically includes: a module (1), a module (2) and a module (3); the module (1) comprises: operational amplifier AMP1, switches S1, …, S6, reference voltage Vref input, accelerometer sensitive structure capacitances Cs1, cs2, integrator capacitances Cf1, cf2; the module (2) comprises: compensating capacitor arrays Cc1, cc2, switches S7, S8; the module (3) comprises: operational amplifier AMP2, switches S9, …, S18, feedback capacitances Cfb1, cfb2 and charge adder capacitances C1, C2, C3.
Further, the operational amplifier AMP1, the switches S1, …, S6, and the capacitors Cs1, cs2, cf1 form a switched capacitor integrator; the switches S7 and S8 and the capacitors Cc1 and Cc2 form a basic capacitance compensation circuit; the op AMP2 and the switches S9, …, S18 and the capacitors C1, C2, C3, cfb1, cfb2 constitute an input common mode compensation circuit.
Further, the detection port Vst of the accelerometer sensitive structure module is connected to the input positive port of the adder add1, and Vsb is connected to the input negative port of the adder add2; the carrier signal generating circuit is connected with the Vctr end of the accelerometer sensitive structure; the basic capacitance compensation array is connected between the detection ends Vst and Vsb of the accelerometer sensitive structure; the input of the output common mode detection is connected with the positive and negative output ends of the switch capacitor integrator; the output of the output common mode detection is connected with one-bit D/A1 and D/A2, the output of the D/A1 is connected with the input negative port of the adder add1, and the output of the D/A2 is connected with the input negative port of the adder add2; the output of the adder add1 is connected with the positive input port of the switched capacitor integrator, and the output of the adder add2 is connected with the negative input port of the switched capacitor integrator.
Further, one end of the switch S1 is connected with a reference voltage Vref end, and the other end is connected to the node C; switch S2 has one end linked to node C and one end connected to the common mode ground or ground of the circuit; capacitor Cs1 is connected between node C and node a, capacitor Cs2 is connected between node C and node B, switch S4 is connected between node a and common mode ground, and switch S3 is connected between node B and common mode ground; the switch S5 is connected between the node A and the negative input end of the operational amplifier AMP1, and the switch S6 is connected between the node B and the positive input end of the operational amplifier AMP 1; the integrating capacitor Cf1 is connected between the positive input terminal and the negative output terminal of the operational amplifier AMP1, and Cf2 is connected between the negative input terminal and the positive output terminal of the operational amplifier AMP 1.
Further, the switch S7 is connected between the reference voltage Vref terminal and the node N1; switch S8 is connected between node N1 and common mode ground or ground; capacitance compensation array Cc1 is connected between node N1 and node a, and Cc2 is connected between node N1 and node B.
Further, the switch S11 is connected between the node N4 and the common mode ground, the capacitor C1 is connected between the node N4 and the node N2, the capacitor C2 is connected between the node N4 and the node N3, and the switch S12 is connected to the node N4 and the negative input terminal of the op AMP 2; the switch S15 is connected between the negative input end of the operational amplifier AMP4 and the node N5, and the switch S16 is connected between the node N5 and the positive input end of the operational amplifier AMP 2; the capacitor C3 is connected with the output ends of the node N5 and the operational amplifier N6; switch S17 is connected between node N3 and node N6, and switch S18 is connected between node N2 and node N6; switch S13 is connected between node N2 and node E, and switch S14 is connected between node N3 and node F; switch S9 is connected between node N6 and node N7, and switch S10 is connected between node N7 and common mode ground; capacitor Cfb1 is connected between nodes N7 and a, and capacitor Cfb2 is connected between node N7 and node B.
The technical scheme in the application is characterized in that: the accelerometer sensitive structure capacitor is directly used as a sampling capacitor of the switch capacitor integrator to form a first-stage switch capacitor integrator; the output voltage of the switch capacitor is detected by a charge adder to obtain the output common-mode voltage of the switch capacitor and is fed back to the input of the integrator; the accelerometer base capacitance is compensated by a capacitance array at the front end of the switched capacitor.
One or more technical schemes provided by the application have at least the following technical effects or advantages:
according to the integrated accelerometer basic capacitance compensation circuit, compensation work is completed through two parts of circuits, namely a compensation capacitance array at two ends of an accelerometer and an input common mode feedback unit taking output of a first-stage integrator as feedback input are connected; because in actual production the base capacitance of the accelerometer may vary within a certain range, there may be a deviation if the compensation is done solely by the compensation capacitor array, and in practice this deviation is not very large, but affects the final result if accumulated continuously over the integrator; the local input common-mode negative feedback module can well dynamically adjust the feedback voltage, ensures the stability of the input common-mode voltage and has better compensation effect.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention;
FIG. 1 is a block diagram of an accelerometer base capacitance compensation circuit;
FIG. 2 is a schematic diagram of an acceleration based capacitance compensation circuit of the present invention;
FIG. 3 is a conventional accelerometer base capacitance compensation circuit;
FIG. 4 is a timing diagram of Non-Overlapping Clock requirements;
fig. 5 is a schematic diagram of an example application of the inventive circuit herein.
Detailed Description
The invention provides a basic capacitance compensation circuit for a digital accelerometer, which solves the problems of unreasonable design and large deviation of MEMS processing technology of the existing basic capacitance compensation circuit for the accelerometer, and realizes the technical effects of allowing the basic capacitance of a sensitive structure and a capacitance compensation array to be offset to a certain extent and having better fault tolerance compared with the traditional detection mode.
In order that the above-recited objects, features and advantages of the present invention will be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. In addition, the embodiments of the present application and the features in the embodiments may be combined with each other without conflicting with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than within the scope of the description, and the scope of the invention is therefore not limited to the specific embodiments disclosed below.
A system block diagram of the accelerometer basic capacitance input common mode compensation circuit of the invention is shown in fig. 1. The modules of the circuit in the figure are provided with an accelerometer sensitive structure, a switch capacitor integrator taking an accelerometer capacitor as a sampling capacitor, a base capacitor compensation array compensating the base capacitor in the accelerometer capacitor, a carrier signal generating circuit converting a reference voltage into a square wave signal, an output common mode detection detecting the output common mode voltage of the switch capacitor integrator, a digital-to-analog converter D/A1 and D/A2, an adder add1 and add 2. The circuit design of each module is as shown in fig. 2, and can be divided into three modules: a module (1) for compensating the base capacitance of the accelerometer; a module (2) of accelerometer capacitance as sampling capacitance of the switched capacitor integrator; and a module (3) for detecting the output of the switched capacitor integrator and feeding back the output to the input of the switched capacitor integrator. The device comprises an operational amplifier [ AMP1 ] [ AMP2 ], a switch [ S1 ] … [ S18 ], a reference voltage [ Vref ], an accelerometer sensitive structure capacitor [ Cs1 ] [ Cs2 ], an integrator capacitor [ Cf1 ] [ Cf2 ], a compensation capacitor array [ Cc1 ] [ Cc2 ], and a feedback capacitor [ Cfb1 ] [ Cfb2 ] and a capacitor of a charge adder [ C1 ] [ C2 ] [ C3 ].
The method comprises the steps of (an accelerometer sensitive structure) converting an external acceleration signal into a change quantity of capacitance, (a switch capacitance integrator) integrating an input difference signal, (a carrier signal generating circuit) generating square wave signals to charge and discharge the capacitance of the accelerometer sensitive structure, (a base capacitance compensation array) compensating the base capacitance of the accelerometer sensitive structure, (an output common mode detection) detecting the output common modulus of the switch capacitance integrator, (D/A1) and (D/A2) feeding the output common modulus of the switch capacitance integrator back to the input of the switch capacitance integrator, (add 1) and (add 2) completing addition and subtraction of charges by an adder and feeding the result obtained by summation into the switch capacitance integrator.
The operational amplifier [ AMP1 ] and the switch [ S1 ] … [ S6 ], the capacitor [ Cs1 ] and the capacitor [ Cs2 ] and the capacitor [ Cf1 ] form a switched capacitor integrator; the switch (S7) and the capacitor (Cc 1) form a basic capacitor compensation circuit; the operational amplifier [ AMP2 ] and the switch [ S9 ] … [ S18 ] form an input common mode compensation circuit, and the capacitor [ C1 ] C2 [ C3 ] Cfb1 ] Cfb 2.
The detection port of the accelerometer sensitive structure is linked to the input positive port of the adder add1, and the detection port is connected to the input negative port of the adder add 2. The carrier signal generating circuit is connected with the Vctr end of the accelerometer sensitive structure, and the basic capacitance compensation array is connected with the detection ends Vst and Vsb of the accelerometer sensitive structure. The input of the output common mode detection is connected with the positive and negative output ends of the switch capacitor integrator. The output of the output common mode detection module is connected with one bit (D/A1) and (D/A2), the output of the D/A1 is connected with the input negative port of the adder (add 1), and the output of the D/A2 is connected with the input negative port of the adder (add 2). The output of the adder [ add1 ] is connected with the positive input port of the switched capacitor integrator, and the output of the adder [ add2 ] is connected with the negative input port of the switched capacitor integrator.
In the circuit connection diagram, in the circuit module (1), one end of a switch [ S1 ] is connected with a reference voltage [ Vref ], and the other end is connected with a node [ C ]. The switch [ S2 ] is linked at one end to the node [ C ], and at one end to the common mode ground or ground of the circuit. The capacitor [ Cs1 ] is connected between the node [ C ] and the node [ A ], the capacitor [ Cs2 ] is connected between the node [ C ] and the node [ B ], the switch [ S4 ] is connected between the node [ A ] and the common mode ground, and the switch [ S3 ] is connected between the node [ B ] and the common mode ground. The switch (S5) is connected between the node (A) and the negative input end of the operational amplifier (AMP 1), and the switch (S6) is connected between the node (B) and the positive input end of the operational amplifier (AMP 1). The integrating capacitor (Cf 1) is connected between the positive input end and the negative output end of the operational amplifier (AMP 1), and the integrating capacitor (Cf 2) is connected between the negative input end and the positive output end of the operational amplifier (AMP 1).
In the circuit module (2), a switch [ S7 ] is connected between a reference voltage [ Vref ] and a node [ N1 ]. The switch [ S8 ] is connected between the node [ N1 ] and common mode ground or ground. The capacitance compensation array (Cc 1) is connected between the node (N1) and the node (A), and the capacitance compensation array (Cc 2) is connected between the node (N1) and the node (B).
In the circuit module (3), a switch [ S11 ] is connected between a node [ N4 ] and a common mode ground, a capacitor [ C1 ] is connected between the node [ N4 ] and the node [ N2 ], the capacitor [ C2 ] is connected between the node [ N4 ] and the node [ N3 ], and the switch [ S12 ] is connected with negative input ends of the node [ N4 ] and the operational amplifier [ AMP2 ]. The switch [ S15 ] is connected between the negative input end of the operational amplifier [ AMP4 ] and the node [ N5 ], and the switch [ S16 ] is connected between the node [ N5 ] and the positive input end of the operational amplifier [ AMP2 ]. The capacitor [ C3 ] is connected with the output ends of the node [ N5 ] and the operational amplifier [ N6 ]. The switch [ S17 ] is connected between the node [ N3 ] and the node [ N6 ], and the switch [ S18 ] is connected between the node [ N2 ] and the node [ N6 ]. The switch [ S13 ] is connected between the node [ N2 ] and the node [ E ], and the switch [ S14 ] is connected between the node [ N3 ] and the node [ F ]. The switch [ S9 ] is connected between the node [ N6 ] and the node [ N7 ], and the switch [ S10 ] is connected between the node [ N7 ] and the common mode ground. The capacitor (Cfb 1) is connected between the nodes (N7) and (a), and the capacitor (Cfb 2) is connected between the nodes (N7) and (B).
FIG. 5 shows an example of an application of the present invention, which is a third order charge Sigma Delta accelerometer capacitance detection circuit. In this circuit the switched capacitor integrator with the accelerometer sensitive structure as the sampling capacitor is the first stage integrator of the SigmaDelta modulator in the invention. The second and third integrator are traditional switch capacitor integrator, and the whole circuit is in the form of forward summation Sigma Delta modulator circuit, such as module (1). The front end of the first-stage integrator is provided with a basic capacitance compensation circuit module (2) formed by a capacitance array, the module (3) is a feedback circuit from the output of the modulator to the first-stage integrator, the feedback coefficient of the first-stage integrator is controlled, and the module (4) is an input common-mode feedback circuit module. The clocking scheme employed by the system is shown in fig. 4. The circuit can realize the capacitance detection function of the low-power-consumption accelerometer.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages:
according to the integrated accelerometer basic capacitance compensation circuit, compensation work is completed through two parts of circuits, namely a compensation capacitance array at two ends of an accelerometer and an input common mode feedback unit taking output of a first-stage integrator as feedback input are connected; because in actual production the base capacitance of the accelerometer may vary within a certain range, there may be a deviation if the compensation is done solely by the compensation capacitor array, and in practice this deviation is not very large, but affects the final result if accumulated continuously over the integrator; the local input common-mode negative feedback module can well dynamically adjust the feedback voltage, ensures the stability of the input common-mode voltage and has better compensation effect.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (8)
1. A compensation circuit for a digital accelerometer base capacitance, the compensation circuit comprising:
the accelerometer sensing structure, the switched capacitor integrator, the basic capacitor compensation array, the carrier signal generating circuit, the output common mode detection module, the D/A1 and D/A2 digital-to-analog converters, and the adders add1 and add2; the detection port Vst of the accelerometer sensitive structure is connected to the input positive port of the adder add1, and the detection port Vsb is connected to the input negative port of the adder add2; the carrier signal generating circuit is connected with the Vctr end of the accelerometer sensitive structure, and the basic capacitance compensation array is connected with the detection ends Vst and Vsb of the accelerometer sensitive structure; the input of the output common mode detection module is connected with the positive and negative output ends of the switched capacitor integrator, the output of the output common mode detection module is connected with D/A1 and D/A2, the output of the D/A1 is connected with the input negative port of the adder add1, and the output of the D/A2 is connected with the input negative port of the adder add2; the output of the adder add1 is connected with the positive input port of the switched capacitor integrator, and the output of the adder add2 is connected with the negative input port of the switched capacitor integrator.
2. The base capacitance compensation circuit for a digital accelerometer according to claim 1, wherein the accelerometer sensitive structure is configured to convert an external acceleration signal into a change in capacitance; the switch capacitor integrator is used for integrating the input difference signal; the carrier signal generating circuit is used for generating square wave signals to charge and discharge the accelerometer sensitive structure capacitance; the basic capacitance compensation array is used for compensating the basic capacitance of the accelerometer sensitive structure; the output common mode detection is used for detecting the output common modulus of the switched capacitor integrator; D/A1 and D/A2 are used to feed back the output common modulus of the switched capacitor integrator to the input of the switched capacitor integrator; add1 and add2 are used for adding and subtracting the electric charge by the adder and sending the result obtained by summation to the switched capacitor integrator.
3. The base capacitance compensation circuit for a digital accelerometer of claim 1, wherein the compensation circuit specifically comprises: a module (1), a module (2) and a module (3);
the module (1) comprises an accelerometer sensitive structure, a switched capacitor integrator and a carrier signal generating circuit, and specifically comprises: operational amplifier AMP1, switches S1, …, S6, reference voltage Vref input, accelerometer sensitive structure capacitances Cs1, cs2, integrator capacitances Cf1, cf2;
the module (2) comprises a basic capacitance compensation array and a carrier signal generation circuit, and specifically comprises: compensating capacitor arrays Cc1, cc2, switches S7, S8;
the module (3) comprises output common mode detection, digital-to-analog converters D/A1 and D/A2 and adders add1 and add2, and specifically comprises: operational amplifier AMP2, switches S9, …, S18, feedback capacitances Cfb1, cfb2 and charge adder capacitances C1, C2, C3.
4. A basic capacitance compensation circuit for a digital accelerometer according to claim 3, wherein the op-AMP 1 and the switches S1, …, S6 and the capacitances Cs1, cs2, cf1 constitute a switched capacitor integrator; the switches S7 and S8 and the compensating capacitor arrays Cc1 and Cc2 form a basic capacitor compensating array; the op AMP2 and the switches S9, …, S18 and the capacitors C1, C2, C3, cfb1, cfb2 constitute an input common mode compensation circuit.
5. A base capacitance compensation circuit for a digital accelerometer according to claim 3 wherein the sense port Vst of the accelerometer sensitive structure module is connected to the input positive port of adder add1 and Vsb is connected to the adder add2 input negative port; the carrier signal generating circuit is connected with the Vctr end of the accelerometer sensitive structure; the basic capacitance compensation array is connected between the detection ends Vst and Vsb of the accelerometer sensitive structure; the input of the output common mode detection is connected with the positive and negative output ends of the switch capacitor integrator; the output of the output common mode detection is connected with one-bit D/A1 and D/A2, the output of the D/A1 is connected with the input negative port of the adder add1, and the output of the D/A2 is connected with the input negative port of the adder add2; the output of the adder add1 is connected with the positive input port of the switched capacitor integrator, and the output of the adder add2 is connected with the negative input port of the switched capacitor integrator.
6. A basic capacitance compensation circuit for a digital accelerometer according to claim 3, wherein the switch S1 has one end connected to the reference voltage Vref terminal and the other end connected to node C; switch S2 has one end linked to node C and one end connected to the common mode ground or ground of the circuit; capacitor Cs1 is connected between node C and node a, capacitor Cs2 is connected between node C and node B, switch S4 is connected between node a and common mode ground, and switch S3 is connected between node B and common mode ground; the switch S5 is connected between the node A and the negative input end of the operational amplifier AMP1, and the switch S6 is connected between the node B and the positive input end of the operational amplifier AMP 1; the integrating capacitor Cf1 is connected between the positive input terminal and the negative output terminal of the operational amplifier AMP1, and Cf2 is connected between the negative input terminal and the positive output terminal of the operational amplifier AMP 1.
7. A base capacitance compensation circuit for a digital accelerometer according to claim 3, wherein switch S7 is connected between the reference voltage Vref terminal and node N1; switch S8 is connected between node N1 and common mode ground or ground; the compensation capacitor array Cc1 is connected between the node N1 and the node a, and the compensation capacitor array Cc2 is connected between the node N1 and the node B.
8. A basic capacitance compensation circuit for a digital accelerometer according to claim 3, wherein switch S11 is connected between node N4 and common mode ground, capacitance C1 is connected between node N4 and node N2, capacitance C2 is connected between node N4 and node N3, and switch S12 is connected to node N4 and the negative input of op AMP 2; the switch S15 is connected between the negative input end of the operational amplifier AMP4 and the node N5, and the switch S16 is connected between the node N5 and the positive input end of the operational amplifier AMP 2; the capacitor C3 is connected with the output ends of the node N5 and the operational amplifier N6; switch S17 is connected between node N3 and node N6, and switch S18 is connected between node N2 and node N6; switch S13 is connected between node N2 and node E, and switch S14 is connected between node N3 and node F; switch S9 is connected between node N6 and node N7, and switch S10 is connected between node N7 and common mode ground; capacitor Cfb1 is connected between nodes N7 and a, and capacitor Cfb2 is connected between node N7 and node B.
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| CN111510143A (en) * | 2020-04-03 | 2020-08-07 | 四川知微传感技术有限公司 | Front-end circuit for direct conversion from capacitance to digital quantity |
| CN116380135B (en) * | 2023-06-06 | 2023-08-11 | 成都市晶蓉微电子有限公司 | Charge transfer balance type capacitor-to-voltage conversion circuit |
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