CN107192850B - Accelerometer capacitance detection circuit - Google Patents
Accelerometer capacitance detection circuit Download PDFInfo
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- CN107192850B CN107192850B CN201710581214.6A CN201710581214A CN107192850B CN 107192850 B CN107192850 B CN 107192850B CN 201710581214 A CN201710581214 A CN 201710581214A CN 107192850 B CN107192850 B CN 107192850B
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- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P15/125—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values by capacitive pick-up
Abstract
The invention discloses an accelerometer capacitance detection circuit, which comprises: a modulator architecture module; a capacitance compensation array module; a digital-to-analog conversion circuit module; the input common mode compensation circuit module is characterized in that the capacitance compensation array is connected to the front end of the first-stage switched capacitor integrator of the modulator module, the digital-to-analog conversion circuit is connected to the first-stage switched capacitor integrator under the control of one-bit digital output, the input common mode compensation circuit samples the output of the first-stage switched capacitor integrator, and the input common mode voltage deviation of the input common mode voltage is eliminated by feeding back the common mode voltage to the input of the first-stage switched capacitor integrator after the common mode voltage is obtained, so that the technical problems that the existing accelerometer capacitance detection circuit is easily influenced by environmental factors and self factors, has higher power consumption and is inconvenient to process are solved, the circuit design is reasonable, the influence of the environment and the self is not easy to realize, the detection result is accurate, and the power consumption is lower are solved.
Description
Technical Field
The invention relates to the field of accelerometer research, in particular to an accelerometer capacitance detection circuit.
Background
Accelerometers are currently used in a wide variety of automotive, industrial automation, aerospace, and other applications. Capacitive accelerometers are popular because of their low temperature sensitivity compared to piezoresistive accelerometers. In addition, the advantage of digital accelerometers over analog accelerometers in that they can be used directly for error correction and compensation without the need for an additional ADC is a dominant option.
Fig. 2 is a diagram of a conventional open loop accelerometer capacitance detection circuit in which there are two important modules, a capacitance-to-voltage converter (C/V) and a voltage-to-digital converter (V/D) at the subsequent stage. However, this combination has three main disadvantages: first, the conversion to voltage is easily affected by environmental factors (such as temperature), as well as noise of the circuit itself; second, in most capacitance detection circuits, the C/V module consumes considerable power consumption, as it requires a large bandwidth and high gain to achieve low noise output, which is highly undesirable in low power designs. Third, the base capacitance of the sensor sensitive structure may vary greatly due to large process variations in the MEMS manufacturing process, which can present a significant challenge for front-end C/V design.
In summary, in the process of implementing the technical solution of the present invention, the present inventors have found that at least the following technical problems exist in the above technology:
in the prior art, the existing accelerometer capacitance detection circuit has the technical problems of being easily influenced by environmental factors and self factors and having higher power consumption.
Disclosure of Invention
The invention provides an accelerometer capacitance detection circuit, which solves the technical effects that the existing accelerometer capacitance detection circuit is easily influenced by environmental and self factors, has higher power consumption, and has reasonable circuit design, is not easily influenced by the environmental and self factors, accurate detection result and lower power consumption.
To solve the above technical problem, the present application provides an accelerometer capacitance detection circuit, the circuit includes:
a modulator architecture module; a capacitance compensation array module; a digital-to-analog conversion circuit module; the input common mode compensation circuit module is used for converting the change of the capacitance of the accelerometer into digital output, the capacitance compensation array module is used for counteracting basic capacitance imbalance and errors in the sensitive structure of the accelerometer, the digital-to-analog conversion circuit module is used for realizing feedback from one-bit digital output to the first-stage switched capacitor integrator, and the input common mode compensation circuit is used for eliminating input common mode voltage deviation of the first-stage switched capacitor integrator; the capacitance compensation array is connected to the front end of the first-stage switch capacitance integrator of the modulator module, the digital-to-analog conversion circuit is connected to the first-stage switch capacitance integrator under the control of one-bit digital output, the input common-mode compensation circuit samples the output of the first-stage switch capacitance integrator, and after the common-mode voltage is obtained, the input common-mode voltage is fed back to the input of the first-stage switch capacitance integrator to eliminate the input common-mode voltage deviation.
Further, the modulator architecture module includes: equivalent capacitors Cs1, cs2 of the accelerometer sensitive structure, operational amplifiers AMP1, AMP2, AMP3, a comparator CMP, switches S1, …, S30, capacitors C1, …, C14, correlated double sampling capacitors Ch1, ch2, first-stage integrator capacitors Cf1, cf2;
further, the capacitance compensation array module includes: switches S31, S32 and capacitances Cc1, cc2.
Further, the digital-to-analog conversion circuit module includes: switches S33, …, S40 and capacitances Cb1, cb2.
Further, the input common mode compensation circuit module includes: single-ended operational amplifier AMP4, switches S41, …, S50, capacitors C15, C16, cfb1, cfb2.
Further, the operational amplifier AMP1 and the switches S1, …, S8 and the capacitors Cs1, cs2, ch1, ch2, cf1, cf2 form a first stage switched capacitor integrator; the operational amplifier AMP2, the switches S9, …, S16 and the capacitors C1, C2, C11, C12 form a second stage switched capacitor integrator; the operational amplifier AMP3, the switches S17 and … S24 and the capacitors C3, C4, C13 and C14 form a third-stage switched capacitor integrator; the switches S25, … and S30 and the capacitors C5, … and C10 form a summation circuit; the comparator CMP serves as a one-bit quantizer; the switches S31 and S32 and the capacitors Cc1 and Cc2 form a basic capacitance compensation circuit; the switches S33, …, S40 and the capacitors Cb1, cb2 form a negative feedback of the modulator output to the first switched capacitor; the operational amplifier AMP4 and the switches S41, …, S50 and the capacitors C15, C16, C17, cfb1, cfb2 constitute an input common mode negative feedback circuit.
Further, in the modulator structure module, one end of the switch S1 is connected to the reference voltage Vref, and the other end is linked to the node C; switch S2 has one end linked to node C and the other end connected to the common mode ground or ground of the circuit; switch S4 is connected between node A and common mode ground, and switch S3 is connected between node B and common mode ground; a capacitor Cs1 is connected between the node C and the node a, a capacitor Cs2 is connected between the node C and the node B, a capacitor Ch1 is connected between the node a and the negative input terminal of the operational amplifier AMP1, and a capacitor Ch2 is connected between the node B and the positive input terminal of the operational amplifier AMP 1; switch S5 is connected between node B and node N1, and switch S6 is connected between node A and node N2; switch S7 is connected between node N1 and the positive input of operational amplifier AMP1, and switch S8 is connected between the negative input of operational amplifier AMP1 and node N2; the integrating capacitor Cf1 is connected between the positive input end and the negative output end of the operational amplifier AMP1, and Cf2 is connected between the negative input end and the positive output end of the operational amplifier AMP 1; switch S11 is connected between node F and node addp1, and switch S12 is connected between node E and addn 1; the switch S9 is connected between the node addn1 and the common mode ground, and the switch S10 is respectively connected between the node addp1 and the common mode ground; switch S13 is connected between node N3 and common mode ground, and switch S14 is connected between node N4 and common mode ground; switch S15 is connected between node N3 and the positive input of operational amplifier AMP2, and switch S16 is connected between node N4 and the negative input of operational amplifier AMP2, respectively; the capacitor C11 is connected between the negative input end and the positive output end of the operational amplifier AMP2 in a bridging mode, and the capacitor C12 is connected between the positive input output end and the negative output end of the operational amplifier AMP2 in a bridging mode; the switch S17 is connected between the negative output end of the operational amplifier AMP2 and the node adn 2, and the switch S18 is connected between the positive output end of the operational amplifier AMP2 and the node adn 2; the capacitor C3 is connected between the node addp2 and the node N6, and the capacitor C4 is connected between the node addn2 connection point and the node N5; switch S19 is connected between node add 2 and common mode ground, and switch S20 is connected between the point of attachment of add 2 and common mode ground; switch S21 is connected between node N5 and common mode ground, and switch S22 is connected between node N6 and common mode ground; switch S23 is connected between node N5 and the positive input of operational amplifier AMP3, and switch S24 is connected between node N6 and the negative input of operational amplifier AMP 3; the capacitor C13 is connected across the negative input end and the positive output end of the operational amplifier AMP3, and the capacitor C14 is connected across the positive input end and the negative output end of the operational amplifier AMP 3; the switch S25 is connected between the node N7 and the negative output terminal of the operational amplifier AMP3, and the switch S26 is connected between the positive output terminal of the operational amplifier AMP3 and the node N8; switch S27 is connected between node N7 and common mode ground, and switch S28 is connected between node N8 and common mode ground; the capacitor C6 is connected between the node N7 and the node N9, and the capacitor C5 is connected between the node N8 and the node N10; switch S29 is connected between node N9 and common mode ground, and switch S30 is connected between node N10 and common mode ground; the capacitor C7 is connected between the node addp1 and the node N10, and the capacitor C8 is connected between the node addn1 and the node N9; the capacitor C9 is connected between the node addp2 and the node N10, and C10 is connected between the node addn2 and the node N9.
Further, in the capacitance compensation array module, the switch S31 is connected between the reference voltage Vref terminal and the node N11; switch S32 is connected between node N11 and common mode ground or ground; capacitance compensation array Cc1 is connected between node N11 and node a, and Cc2 is connected between node N11 and node B.
Further, in the digital-to-analog conversion circuit module, a switch S33 is connected between the reference voltage Vref1 end and the node N12, and is controlled by the output Y2, and a switch S34 is connected between the reference voltage Vref2 end and the node N12, and is controlled by the output Y1; switch S37 connects between node N12 and node N14, and switch S39 connects between node N14 and common mode ground; capacitor Cb2 is connected between node N14 and node B; the switch S35 is connected between the reference voltage Vref2 end and the node N13 and is controlled by the output Y2; the switch S36 is connected between the reference voltage Vref1 end and the node N13 and is controlled by an output signal Y1; switch S38 is connected between node N13 and node N15, and switch S40 is connected between node N15 and common mode ground; capacitor Cb1 is connected between node N15 and node a.
Further, in the input common mode compensation circuit module, the switch S47 is connected to the node N16 and the common mode ground, the capacitor C15 is connected between the node N16 and the node N19, the capacitor C16 is connected between the node N16 and the node N18, and the switch S48 is connected to the node N16 and the negative input terminal of the operational amplifier AMP 4; switch S49 is connected between the negative input terminal of operational amplifier AMP4 and node N17, and switch S50 is connected between node N17 and the positive input terminal of operational amplifier AMP 4; the capacitor C17 is connected to the node N17 and the output terminal of the operational amplifier AMP 4; switch S41 is connected between node N20 and node N18, and switch S42 is connected between node N19 and node N20; switch S45 is connected between node N18 and node F, and switch S46 is connected between node N19 and node E; switch S43 is connected between node N20 and node N21, and switch S44 is connected between node N21 and common mode ground; capacitor Cfb1 is connected between nodes N21 and a, and capacitor Cfb2 is connected between node N21 and node B.
One or more technical schemes provided by the application have at least the following technical effects or advantages:
the new integrated detection circuit in this application solves the above-mentioned problems by combining a sensitive structure with a Sigma-Delta modulator, the differential capacitance of the sensitive structure being used as the sampling capacitance of the Sigma-Delta modulator; the change in differential capacitance directly translates into an error signal in the Sigma-Delta loop, thus eliminating the need to use voltage as a conversion intermediary; the structure has another advantage that the front-end operational amplifier is only a simple integrated operational amplifier, and is not C/V which needs to consume a large amount of power consumption, so that the power consumption of the system is effectively reduced; meanwhile, in order to solve the problem of obtaining the front-end input common mode, the application also provides a proper input common mode compensation feedback circuit; therefore, the technical problems that the existing accelerometer capacitance detection circuit is easily influenced by environmental factors and self factors, has higher power consumption and is inconvenient to process are solved, and the technical effects that the circuit design is reasonable, the circuit is not easily influenced by the environmental factors and the self factors, the detection result is accurate and the power consumption is lower are further realized.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention;
FIG. 1 is a schematic diagram of an integrated third order charge Sigma Delta capacitance detection circuit connection;
FIG. 2 is a schematic diagram of a conventional Sigma Delta accelerometer capacitance detection circuit;
FIG. 3 is a schematic diagram of an example application of a digital accelerometer capacitance detection circuit;
FIG. 4 is a timing diagram of Non-Overlapping Clock (Non-overlapping clock) requirements.
Detailed Description
The invention provides an accelerometer capacitance detection circuit, which solves the technical effects that the existing accelerometer capacitance detection circuit is easily influenced by environmental and self factors, has higher power consumption, and has reasonable circuit design, is not easily influenced by the environmental and self factors, accurate detection result and lower power consumption.
In order that the above-recited objects, features and advantages of the present invention will be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. In addition, the embodiments of the present application and the features in the embodiments may be combined with each other without conflicting with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than within the scope of the description, and the scope of the invention is therefore not limited to the specific embodiments disclosed below.
Referring to fig. 1, the present application provides an integrated accelerometer capacitance detection circuit of the present invention, wherein a differential capacitance of an accelerometer sensitive structure is used as a sampling capacitance of a Sigma-Delta modulator by combining the sensitive structure with the Sigma-Delta modulator, and specific circuit connection is shown in fig. 1. FIG. 1 can be divided into four modules, module (1) of Sigma-Delta modulator architecture employing third order feed forward summation; a capacitance compensation array module (2); the digital output is fed back to a digital-to-analog conversion circuit module (3) of the first-stage integrator; and inputting the common mode compensation circuit module (4). The module (1) comprises an equivalent capacitor (Cs 1, cs 2), an operational amplifier (AMP 1, AMP2, AMP3, a Comparator (CMP) and a switch (S1, S30), a capacitor (C1, C …, C14), a correlated double sampling capacitor (Ch 1, ch 2), a first-stage integrator capacitor (Cf 1, cf 2), the module (2) comprises a switch (S31) and a capacitor (Cc 1) and a capacitor (Cc 2), the module (3) comprises a switch (S33) … (S40) and a capacitor (Cb 1) and a capacitor (Cb 2), and the module (4) comprises a single-ended operational amplifier (AMP 4), a switch (S41) … (S50) and a capacitor (C15) C16 (Cfb 1) and Cfb2. Two-phase non-overlapping clock signal [ phi ] 1 】【φ 2 】。
The operational amplifier [ AMP1 ] and the switch [ S1 ] … [ S8 ], the capacitor [ Cs1 ] Cs2 [ Ch1 ] Ch2 [ Cf1 ] and Cf2 ] form a first-stage switched capacitor integrator; the operational amplifier [ AMP2 ] and the switch [ S9 ] … [ S16 ] and the capacitor [ C1 ] C2 ] C11 ] C12 ] form a second-stage switched capacitor integrator; an operational amplifier [ AMP3 ] and a switch [ S17 ] … [ S24 ], a capacitor [ C3 ] and a capacitor [ C4 ] [ C13 ] [ C14 ] form a ground three-stage switched capacitor integrator; the switch [ S25 ] … [ S30 ] and the capacitor [ C5 ] … [ C10 ] form a summation circuit; a comparator [ CMP ] acts as a one-bit quantizer; the switch (S31) and the capacitor (Cc 1) form a basic capacitor compensation circuit; the switch [ S33 ] … [ S40 ] and the capacitor [ Cb1 ] form negative feedback output by the modulator to the first switch capacitor; the operational amplifier [ AMP4 ] and the switch [ S41 ] … [ S50 ] and the capacitor [ C15 ] C16 [ C17 ] Cfb1 ] Cfb2 ] form an input common-mode negative feedback circuit.
In the circuit module (1), one end of a switch [ S1 ] is connected with a reference voltage [ Vref ], and the other end of the switch is connected to a node [ C ]. The switch [ S2 ] is linked at one end to the node [ C ], and at one end to the common mode ground or ground of the circuit. The switch [ S4 ] is connected between the node [ A ] and the common mode ground, and the switch [ S3 ] is connected between the node [ B ] and the common mode ground. The capacitor [ Cs1 ] is connected between the node [ C ] and the node [ A ], the capacitor [ Cs2 ] is connected between the node [ C ] and the node [ B ], the capacitor [ Ch1 ] is connected between the node [ A ] and the negative input end of the operational amplifier [ AMP1 ], and the capacitor [ Ch2 ] is connected between the node [ B ] and the positive input end of the operational amplifier [ AMP1 ]. The switch [ S5 ] is connected between the node [ B ] and the node [ N1 ], and the switch [ S6 ] is connected between the node [ A ] and the node [ N2 ]. The switch [ S7 ] is connected between the node [ N1 ] and the positive input end of the operational amplifier [ AMP1 ], and the switch [ S8 ] is connected between the negative input end of the operational amplifier [ AMP1 ] and the node [ N2 ]. The integrating capacitor (Cf 1) is connected between the positive input end and the negative output end of the operational amplifier (AMP 1), and the integrating capacitor (Cf 2) is connected between the negative input end and the positive output end of the operational amplifier (AMP 1). The switch [ S11 ] is connected between the node [ F ] and the node [ addp1 ], and the switch [ S12 ] is connected between the node [ E ] and the node [ addn1 ]. The switch [ S9 ] is connected between the node [ addn1 ] and the common mode ground, and the switch [ S10 ] is respectively connected between the node [ addp1 ] and the common mode ground. The switch [ S13 ] is connected between the node [ N3 ] and the common mode ground, and the switch [ S14 ] is connected between the node [ N4 ] and the common mode ground. The switch [ S15 ] is connected between the positive input ends of the node [ N3 ] and the operational amplifier [ AMP2 ], and the switch [ S16 ] is respectively connected between the negative input ends of the node [ N4 ] and the operational amplifier [ AMP2 ]. The capacitor (C11) is connected between the negative input end and the positive output end of the operational amplifier (AMP 2) in a bridging mode, and the capacitor (C12) is connected between the positive input output end and the negative output end of the operational amplifier (AMP 2) in a bridging mode. The switch [ S17 ] is connected between the negative output end of the operational amplifier [ AMP2 ] and the node [ addn2 ], and the switch [ S18 ] is connected between the positive output end of the operational amplifier [ AMP2 ] and the node [ addn2 ]. The capacitor [ C3 ] is connected between the node [ addp2 ] and the node [ N6 ], and the capacitor [ C4 ] is connected between the node [ addn2 ] connecting point and the node [ N5 ]. The switch [ S19 ] is connected between the node [ addn2 ] and the common mode ground, and the switch [ S20 ] is connected between the junction of the node [ addp2 ] and the common mode ground. The switch [ S21 ] is connected between the node [ N5 ] and the common mode ground, and the switch [ S22 ] is connected between the node [ N6 ] and the common mode ground. The switch [ S23 ] is connected between the positive input ends of the node [ N5 ] and the operational amplifier [ AMP3 ], and the switch [ S24 ] is connected between the negative input ends of the node [ N6 ] and the operational amplifier [ AMP3 ]. The capacitor (C13) is connected across the negative input end and the positive output end of the operational amplifier (AMP 3), and the capacitor (C14) is connected across the positive input output end and the negative output end of the operational amplifier (AMP 3). The switch [ S25 ] is connected between the negative output end of the node [ N7 ] and the operational amplifier [ AMP3 ], and the switch [ S26 ] is connected between the positive output end of the operational amplifier [ AMP3 ] and the node [ N8 ]. The switch [ S27 ] is connected between the node [ N7 ] and the common mode ground, and the switch [ S28 ] is connected between the node [ N8 ] and the common mode ground. The capacitor [ C6 ] is connected between the node [ N7 ] and the node [ N9 ], and the capacitor [ C5 ] is connected between the open node [ N8 ] and the node [ N10 ]. The switch [ S29 ] is connected between the node [ N9 ] and the common mode ground, and the switch [ S30 ] is connected between the node [ N10 ] and the common mode ground. The capacitor [ C7 ] is connected between the node [ addp1 ] and the node [ N10 ], and the capacitor [ C8 ] is connected between the node [ addn1 ] and the node [ N9 ]. The capacitor [ C9 ] is connected between the node [ addp2 ] and the node [ N10 ], and the capacitor [ C10 ] is connected between the node [ addn2 ] and the node [ N9 ].
In the circuit module (2), a switch [ S31 ] is connected between a reference voltage [ Vref ] and a node [ N11 ]. The switch [ S32 ] is connected between the node [ N11 ] and common mode ground or ground. The capacitance compensation array (Cc 1) is connected between the node (N11) and the node (A), and the capacitance compensation array (Cc 2) is connected between the node (N11) and the node (B).
In the circuit module (3), a switch (S33) is connected between a reference voltage (Vref 1) and a node (N12), controlled by an output (Y2), and a switch (S34) is connected between the reference voltage (Vref 2) and the node (N12), controlled by the output (Y1). The switch [ S37 ] is connected between the node [ N12 ] and the node [ N14 ], and the switch [ S39 ] is connected between the node [ N14 ] and the common mode ground. The capacitor [ Cb2 ] is connected between the node [ N14 ] and the node [ B ]. The switch [ S35 ] is connected between the reference voltage [ Vref2 ] and the node [ N13 ], and is controlled by the output [ Y2 ]. The switch [ S36 ] is connected between the reference voltage [ Vref1 ] and the node [ N13 ], and is controlled by the output signal [ Y1 ]. The switch [ S38 ] is connected between the node [ N13 ] and the node [ N15 ], and the switch [ S40 ] is connected between the node [ N15 ] and the common mode ground. The capacitor [ Cb1 ] is connected between the node [ N15 ] and the node [ A ].
In the circuit module (4), the switch [ S47 ] is connected with the node [ N16 ] and the common mode ground, the capacitor [ C15 ] is connected between the node [ N16 ] and the node [ N19 ], the capacitor [ C16 ] is connected between the node [ N16 ] and the node [ N18 ], and the switch [ S48 ] is connected with the negative input ends of the node [ N16 ] and the operational amplifier [ AMP4 ]. The switch [ S49 ] is connected between the negative input end of the operational amplifier [ AMP4 ] and the node [ N17 ], and the switch [ S50 ] is connected between the node [ N17 ] and the positive input end of the operational amplifier [ AMP4 ]. The capacitor [ C17 ] is connected to the output ends of the node [ N17 ] and the operational amplifier [ AMP4 ]. The switch [ S41 ] is connected between the node [ N20 ] and the node [ N18 ], and the switch [ S42 ] is connected between the node [ N19 ] and the node [ N20 ]. The switch [ S45 ] is connected between the node [ N18 ] and the node [ F ], and the switch [ S46 ] is connected between the node [ N19 ] and the node [ E ]. The switch [ S43 ] is connected between the node [ N20 ] and the node [ N21 ], and the switch [ S44 ] is connected between the node [ N21 ] and the common mode ground. The capacitor (Cfb 1) is connected between the nodes (N21) and (a), and the capacitor (Cfb 2) is connected between the nodes (N21) and (B).
The digital accelerometer capacitance detection circuit of the invention needs to generate stable direct current supply voltage and clock signals from outside, after the digital accelerometer capacitance detection circuit processes, acceleration signals are directly converted into digital serial signals to be output, down sampling and digital filtering can be completed in a digital circuit at a later stage, digital compensation can be performed on the result, and after the digital accelerometer capacitance detection circuit processes and compensates, the rear side can be directly connected to a singlechip or an upper computer, and the digital signals can be read out by the singlechip or the upper computer. As a data source for their acceleration signals. The circuit block diagram shown in fig. 3 uses two non-overlapping clocks with the timing relationship shown in fig. 4.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages:
the new integrated detection circuit in this application solves the above-mentioned problems by combining a sensitive structure with a Sigma-Delta modulator, the differential capacitance of the sensitive structure being used as the sampling capacitance of the Sigma-Delta modulator; the change in differential capacitance directly translates into an error signal in the Sigma-Delta loop, thus eliminating the need to use voltage as a conversion intermediary; the structure has another advantage that the front-end operational amplifier is only a simple integrated operational amplifier, and is not C/V which needs to consume a large amount of power consumption, so that the power consumption of the system is effectively reduced; meanwhile, in order to solve the problem of obtaining the front-end input common mode, the application also provides a proper input common mode compensation feedback circuit; therefore, the technical problems that the existing accelerometer capacitance detection circuit is easily influenced by environmental factors and self factors, has higher power consumption and is inconvenient to process are solved, and the technical effects that the circuit design is reasonable, the circuit is not easily influenced by the environmental factors and the self factors, the detection result is accurate and the power consumption is lower are further realized.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (8)
1. An accelerometer capacitance detection circuit, the circuit comprising:
the device comprises a modulator structure module, a capacitance compensation array module, a digital-to-analog conversion circuit module and an input common mode compensation circuit module; wherein the modulator architecture module comprises: equivalent capacitors Cs1, cs2 of the accelerometer sensitive structure, operational amplifiers AMP1, AMP2, AMP3, a comparator CMP, switches S1, …, S30, capacitors C1, …, C14, correlated double sampling capacitors Ch1, ch2, first-stage integrator capacitors Cf1, cf2;
the operational amplifier AMP1, the switches S1, … and S8 and the equivalent capacitor Cs1 of the accelerometer sensitive structure, the equivalent capacitor Cs2 of the accelerometer sensitive structure, the correlated double sampling capacitor Ch1, the correlated double sampling capacitor Ch2, the first-stage integrator capacitor Cf1 and the first-stage integrator capacitor Cf2 form a first-stage switch capacitor integrator; the operational amplifier AMP2, the switches S9, …, S16 and the capacitors C1, C2, C11, C12 form a second stage switched capacitor integrator; the operational amplifier AMP3, the switches S17 and … S24 and the capacitors C3, C4, C13 and C14 form a third-stage switched capacitor integrator; the switches S25, … and S30 and the capacitors C5, … and C10 form a summation circuit; the comparator CMP serves as a one-bit quantizer;
in the modulator structure module, one end of a switch S1 is connected with a reference voltage Vref, and the other end is connected to a node C; switch S2 has one end linked to node C and the other end connected to the common mode ground or ground of the circuit; switch S4 is connected between node A and common mode ground, and switch S3 is connected between node B and common mode ground; an equivalent capacitor Cs1 of the accelerometer sensitive structure is connected between the node C and the node A, an equivalent capacitor Cs2 of the accelerometer sensitive structure is connected between the node C and the node B, a correlated double sampling capacitor Ch1 is connected between the node A and a negative input end of the operational amplifier AMP1, and a correlated double sampling capacitor Ch2 is connected between the node B and a positive input end of the operational amplifier AMP 1; switch S5 is connected between node B and node N1, and switch S6 is connected between node A and node N2; switch S7 is connected between node N1 and the positive input of operational amplifier AMP1, and switch S8 is connected between the negative input of operational amplifier AMP1 and node N2; the first-stage integrator capacitor Cf1 is connected between the positive input end and the negative output end of the operational amplifier AMP1, and the first-stage integrator capacitor Cf2 is connected between the negative input end and the positive output end of the operational amplifier AMP 1; switch S11 is connected between node F and node addp1, and switch S12 is connected between node E and addn 1; the switch S9 is connected between the node addn1 and the common mode ground, and the switch S10 is respectively connected between the node addp1 and the common mode ground; switch S13 is connected between node N3 and common mode ground, and switch S14 is connected between node N4 and common mode ground; switch S15 is connected between node N3 and the positive input of operational amplifier AMP2, and switch S16 is connected between node N4 and the negative input of operational amplifier AMP2, respectively; the capacitor C11 is connected between the negative input end and the positive output end of the operational amplifier AMP2 in a bridging mode, and the capacitor C12 is connected between the positive input output end and the negative output end of the operational amplifier AMP2 in a bridging mode; the switch S17 is connected between the negative output end of the operational amplifier AMP2 and the node adn 2, and the switch S18 is connected between the positive output end of the operational amplifier AMP2 and the node adn 2; the capacitor C3 is connected between the node addp2 and the node N6, and the capacitor C4 is connected between the node addn2 connection point and the node N5; switch S19 is connected between node add 2 and common mode ground, and switch S20 is connected between the point of attachment of add 2 and common mode ground; switch S21 is connected between node N5 and common mode ground, and switch S22 is connected between node N6 and common mode ground; switch S23 is connected between node N5 and the positive input of operational amplifier AMP3, and switch S24 is connected between node N6 and the negative input of operational amplifier AMP 3; the capacitor C13 is connected across the negative input end and the positive output end of the operational amplifier AMP3, and the capacitor C14 is connected across the positive input end and the negative output end of the operational amplifier AMP 3; the switch S25 is connected between the node N7 and the negative output terminal of the operational amplifier AMP3, and the switch S26 is connected between the positive output terminal of the operational amplifier AMP3 and the node N8; switch S27 is connected between node N7 and common mode ground, and switch S28 is connected between node N8 and common mode ground; the capacitor C6 is connected between the node N7 and the node N9, and the capacitor C5 is connected between the node N8 and the node N10; switch S29 is connected between node N9 and common mode ground, and switch S30 is connected between node N10 and common mode ground; the capacitor C7 is connected between the node addp1 and the node N10, and the capacitor C8 is connected between the node addn1 and the node N9; the capacitor C9 is connected between the node addp2 and the node N10, and the capacitor C10 is connected between the node addn2 and the node N9;
the modulator structure module is used for converting the change of the capacitance of the accelerometer into digital output, the capacitance compensation array module is used for counteracting basic capacitance imbalance and errors in the sensitive structure of the accelerometer, the digital-to-analog conversion circuit module is used for realizing feedback from one-bit digital output to the first-stage switched capacitor integrator, and the input common-mode compensation circuit module is used for eliminating input common-mode voltage deviation of the first-stage switched capacitor integrator; the capacitance compensation array module is connected to the front end of a first-stage switched capacitor integrator of the modulator structure module, the capacitance compensation array module is connected with the modulator structure module through a node A and a node B, the digital-to-analog conversion circuit module is connected to the first-stage switched capacitor integrator under the control of one-bit digital output, the digital-to-analog conversion circuit module is also connected with the modulator structure module through the node A and the node B, the input common-mode compensation circuit samples the output of the first-stage switched capacitor integrator, the input common-mode voltage deviation of the input common-mode voltage deviation is eliminated after the common-mode voltage is obtained, the input common-mode voltage deviation is fed back to the input of the first-stage switched capacitor integrator, and the input common-mode compensation circuit is connected with the modulator structure module through the node A, the node B, the node E and the node F.
2. The accelerometer capacitance detection circuit according to claim 1, wherein the capacitance compensation array module comprises: switches S31, S32 and capacitances Cc1, cc2.
3. The accelerometer capacitance detection circuit according to claim 1, wherein the digital-to-analog conversion circuit module comprises: switches S33, …, S40 and capacitances Cb1, cb2.
4. The accelerometer capacitance detection circuit according to claim 1, wherein the input common mode compensation circuit module comprises: single-ended operational amplifier AMP4, switches S41, …, S50, capacitors C15, C16, cfb1, cfb2.
5. The accelerometer capacitance detection circuit of claim 1 wherein,
the capacitance compensation array module includes: switches S31 and S32 and capacitors Cc1 and Cc2, and the switches S31 and S32 and the capacitors Cc1 and Cc2 form a basic capacitance compensation circuit;
the digital-to-analog conversion circuit module includes: switches S33, …, S40 and capacitors Cb1, cb2, and switches S33, …, S40 and capacitors Cb1, cb2 form a negative feedback output from the modulator to the first stage switched capacitor integrator;
the input common mode compensation circuit module includes: the single-ended operational amplifier AMP4, the switches S41, …, S50, the capacitors C15, C16, cfb1, cfb2, and the single-ended operational amplifier AMP4 and the switches S41, …, S50 and the capacitors C15, C16, C17, cfb1, cfb2 constitute an input common-mode negative feedback circuit.
6. The accelerometer capacitance detection circuit according to claim 2, wherein in the capacitance compensation array module, the switch S31 is connected between the reference voltage Vref terminal and the node N11; switch S32 is connected between node N11 and common mode ground or ground; capacitance compensation array Cc1 is connected between node N11 and node a, and Cc2 is connected between node N11 and node B.
7. The accelerometer capacitance detection circuit according to claim 3 wherein in the digital-to-analog conversion circuit module, a switch S33 is connected between the reference voltage Vref1 terminal and the node N12, controlled by the output Y2, and a switch S34 is connected between the reference voltage Vref2 terminal and the node N12, controlled by the output Y1; switch S37 connects between node N12 and node N14, and switch S39 connects between node N14 and common mode ground; capacitor Cb2 is connected between node N14 and node B; the switch S35 is connected between the reference voltage Vref2 end and the node N13 and is controlled by the output Y2; the switch S36 is connected between the reference voltage Vref1 end and the node N13 and is controlled by an output signal Y1; switch S38 is connected between node N13 and node N15, and switch S40 is connected between node N15 and common mode ground; capacitor Cb1 is connected between node N15 and node a.
8. The accelerometer capacitance detection circuit according to claim 4 wherein in the input common mode compensation circuit module, switch S47 is connected to node N16 and common mode ground, capacitor C15 is connected between node N16 and node N19, capacitor C16 is connected between node N16 and node N18, and switch S48 is connected to node N16 and the negative input of operational amplifier AMP 4; switch S49 is connected between the negative input terminal of operational amplifier AMP4 and node N17, and switch S50 is connected between node N17 and the positive input terminal of operational amplifier AMP 4; the capacitor C17 is connected to the node N17 and the output terminal of the operational amplifier AMP 4; switch S41 is connected between node N20 and node N18, and switch S42 is connected between node N19 and node N20; switch S45 is connected between node N18 and node F, and switch S46 is connected between node N19 and node E; switch S43 is connected between node N20 and node N21, and switch S44 is connected between node N21 and common mode ground; capacitor Cfb1 is connected between nodes N21 and a, and capacitor Cfb2 is connected between node N21 and node B.
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| CN108362910B (en) * | 2018-02-10 | 2020-02-07 | 中国工程物理研究院电子工程研究所 | Open-loop micro-accelerometer |
| CN108475155B (en) * | 2018-03-30 | 2020-10-27 | 深圳市为通博科技有限责任公司 | Capacitance detection circuit, touch detection device and terminal equipment |
| CN114487615B (en) * | 2022-04-06 | 2022-08-30 | 基合半导体（宁波）有限公司 | Capacitance measuring circuit and capacitance measuring method |
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