CN111510143A - Front-end circuit for direct conversion from capacitance to digital quantity - Google Patents
Front-end circuit for direct conversion from capacitance to digital quantity Download PDFInfo
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- CN111510143A CN111510143A CN202010259477.7A CN202010259477A CN111510143A CN 111510143 A CN111510143 A CN 111510143A CN 202010259477 A CN202010259477 A CN 202010259477A CN 111510143 A CN111510143 A CN 111510143A
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- switch
- capacitance
- sensitive structure
- operational amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1235—Non-linear conversion not otherwise provided for in subgroups of H03M1/12
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P15/125—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values by capacitive pick-up
Abstract
The invention discloses a front-end circuit for direct conversion from capacitance to digital quantity, which comprises an accelerometer sensitive structure, a reference voltage Vref, 2-phase non-overlapped clock control signals phi 1 and phi 2, an operational amplifier and a switch component, wherein the accelerometer sensitive structure is connected with the switch component through a power supply; controlling a switch component through a clock control signal phi 1, and generating charges in direct proportion to a variable capacitor by utilizing the action of a reference voltage applied to a sensitive structure on the variable capacitor; and then, controlling the switch component through a clock control signal phi 2, so that the obtained charges are amplified through an operational amplifier, and the variable quantity which is in direct proportion to the sensitive structure can be obtained. The invention has simple structure, needs no special analog-to-digital conversion circuit and can also achieve the conversion from direct capacitance to digital quantity.
Description
Technical Field
The invention relates to the technical field of sensors, in particular to a front-end circuit for direct conversion from capacitance to digital quantity, which is applied to an accelerometer.
Background
With the development of MEMS technology, inertial sensors have become one of the most widely used MEMS devices in the past few years, in which micro-accelerometers have been widely used in inertial devices for measuring acceleration of objects, automobiles, industrial automation, aerospace and other fields. However, the traditional accelerometer has large power consumption and complex circuit, and needs a special analog-to-digital conversion module to complete the conversion from the capacitance to the digital quantity, which is one of the most important reasons for influencing the power consumption and the circuit complexity of the MEMS accelerometer.
The conventional analog accelerometer and the digital accelerometer circuit (see fig. 2(a) and 2(b)) formed by the analog-to-digital conversion module employ CV (capacitance-to-voltage conversion) and VD (voltage-to-digital conversion). Because the CV module which is easily influenced by noise and temperature is adopted, the influence of environmental factors on voltage cannot be avoided, and the power consumption of the system is larger.
Disclosure of Invention
The invention provides a front-end circuit for direct conversion from capacitance to digital quantity, aiming at solving the technical problems that a traditional digital accelerometer circuit is easily influenced by environmental factors such as noise, temperature and the like on voltage and has high power consumption. The invention realizes the direct conversion from the capacitor to the digital quantity by taking the capacitor with the sensitive structure as the sampling capacitor of the sigma-delta modulator without adopting a capacitor voltage conversion module, thereby reducing the influence of environmental factors on the voltage, improving the measurement reliability and reducing the power consumption.
The invention is realized by the following technical scheme:
a front-end circuit for direct conversion from capacitance to digital quantity comprises an accelerometer sensitive structure, a reference voltage Vref, 2-phase non-overlapped clock control signals phi 1 and phi 2, an operational amplifier and a switch component; controlling a switch component through a clock control signal phi 1, and generating charges in direct proportion to a variable capacitor by utilizing the action of a reference voltage applied to a sensitive structure on the variable capacitor; and then, controlling the switch component through a clock control signal phi 2, so that the obtained charges are amplified through an operational amplifier, and the variable quantity which is in direct proportion to the sensitive structure can be obtained.
The working principle of the invention is as follows: the charge-discharge characteristic of the capacitor is utilized, the switch component is controlled through two-phase non-overlapping clock signals, and in the control stage of a clock control signal phi 1, the reference voltage applied to the sensitive structure is utilized to act on the changed capacitor to generate charges in direct proportion to the changed capacitor; and then, controlling the phase by a clock control signal phi 2, and amplifying and outputting the electric charge sampled in the control phase by the clock control signal phi 1 through an operational amplifier to obtain the variable quantity which is in direct proportion to the capacitance of the sensitive structure. In the whole stage, the signal output has one period of delay.
In order to further improve the stability of the output of the front-end circuit, the invention is also provided with a compensation capacitor for compensating the sensitive structure. The front-end circuit of the invention further comprises a compensation capacitor Cc1 and a compensation capacitor Cc2, wherein 2 compensation capacitors are used for compensating the basic capacitance of the sensitive structure.
The front-end circuit of the invention further comprises an integrating capacitor Cf1 and an integrating capacitor Cf2, wherein the integrating capacitor Cf1 is connected between the negative output end and the positive input end of the operational amplifier; the integrating capacitor Cf2 is connected between the positive output terminal and the negative input terminal of the operational amplifier.
The switch assembly comprises a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6, a switch S7 and a switch S8, wherein one end of the switch S1 is connected with a reference voltage Vref, the other end of the switch S1 is connected with a middle node of a sensitive structure and one end of the switch S2, and the other end of the switch S2 is grounded; the compensation capacitor Cc1 and the compensation capacitor Cc2 are connected in series and then connected in parallel with the upper end and the lower end of the sensitive structure, one end of a switch S7 is connected with a reference voltage Vref, a switch S7 is connected with one end of a switch S8, the other end of a switch S7 is also connected with the common connection end of the compensation capacitor Cc1 and the compensation capacitor Cc2, and the other end of the switch S8 is grounded; the upper end of the sensitive structure is also connected with one end of a switch S3 and one end of a switch S5, the other end of the switch S3 is grounded, and the other end of the switch S5 is connected with the negative input end of the operational amplifier; the lower end of the sensitive structure is also connected with one end of a switch S4 and one end of a switch S6, the other end of the switch S4 is grounded, and the other end of the switch S6 is connected with the positive input end of the operational amplifier.
The front-end circuit controls the switch S1, the switch S8, the switch S3 and the switch S4 to be closed through inputting a clock control signal phi 1, and the switch S2, the switch S5, the switch S6 and the switch S7 are kept to be opened, so that the reference voltage Vref acts on the changed capacitor of the sensitive structure at the stage, and the charge which is in direct proportion to the changed capacitor is generated; then, the clock control signal Φ 2 is input to control the switch S2, the switch S5, the switch S6, and the switch S7 to be closed, and the switch S1, the switch S8, the switch S3, and the switch S4 to be opened, and at this stage, the electric charges obtained at the previous stage are amplified and output through the operational amplifier.
The output of the front-end circuit of the present invention is represented as follows:
wherein YP is the positive output end of the operational amplifier, YN is the negative output end of the operational amplifier, Cs is the basic capacitance of the sensitive structure,ΔCthe capacitance variation quantity is equal and opposite to that of the upper and lower electrode plates of the sensitive structure of the accelerometer.
The invention has the following advantages and beneficial effects:
1. compared with the traditional digital accelerometer circuit, the invention can directly correct and compensate errors without an additional ADC module.
2. The invention has simple structure, needs no special analog-to-digital conversion circuit and can also achieve the conversion from direct capacitance to digital quantity.
3. The invention has no CV module which is easy to be influenced by noise and temperature, thereby reducing the influence of environmental factors on voltage and saving the power consumption of the module.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
fig. 1 is a schematic diagram of a front-end circuit of the present invention.
Fig. 2 is a block diagram of a conventional digital accelerometer. (a) Is a traditional digital accelerometer structure; (b) is another conventional digital accelerometer structure.
Detailed Description
Hereinafter, the term "comprising" or "may include" used in various embodiments of the present invention indicates the presence of the invented function, operation or element, and does not limit the addition of one or more functions, operations or elements. Furthermore, as used in various embodiments of the present invention, the terms "comprises," "comprising," "includes," "including," "has," "having" and their derivatives are intended to mean that the specified features, numbers, steps, operations, elements, components, or combinations of the foregoing, are only meant to indicate that a particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as first excluding the existence of, or adding to the possibility of, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
In various embodiments of the invention, the expression "or" at least one of a or/and B "includes any or all combinations of the words listed simultaneously. For example, the expression "a or B" or "at least one of a or/and B" may include a, may include B, or may include both a and B.
Expressions (such as "first", "second", and the like) used in various embodiments of the present invention may modify various constituent elements in various embodiments, but may not limit the respective constituent elements. For example, the above description does not limit the order and/or importance of the elements described. The foregoing description is for the purpose of distinguishing one element from another. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of various embodiments of the present invention.
It should be noted that: if it is described that one constituent element is "connected" to another constituent element, the first constituent element may be directly connected to the second constituent element, and a third constituent element may be "connected" between the first constituent element and the second constituent element. In contrast, when one constituent element is "directly connected" to another constituent element, it is understood that there is no third constituent element between the first constituent element and the second constituent element.
The terminology used in the various embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the invention. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Examples
The embodiment provides a front-end circuit for direct conversion from capacitance to digital quantity, which is applied to a digital acceleration circuit.
Specifically, as shown in fig. 1, the front-end circuit structure of this embodiment mainly includes a capacitance change sensitive structure, 2 capacitors Cc1 for compensating a basic capacitance of the sensitive structure, a capacitor Cc2, 2-phase non-overlapping clock control signals Φ 1 and Φ 2, 8 switches S1 to S8, 1 reference voltage Vref, 1 operational amplifier AMP1, 2 integrating capacitors Cf1, and an integrating capacitor Cf 2.
The front-end circuit of this embodiment utilizes the charge-discharge characteristic of the capacitor, and utilizes the reference voltage applied to the capacitor of the sensitive structure to act on the changed capacitor at the control stage of the clock control signal Φ 1, so as to generate a charge proportional to the changed capacitor (i.e. the capacitor of the sensitive structure is used as a sampling capacitor); in the control phase of the clock control signal phi 2, the charge sampled in the previous phase is amplified by the operational amplifier AMP1, and the signal output is delayed by one period in the whole phase.
The front-end circuit connection method of this embodiment is: the input reference voltage Vref is connected to one end of the switch S1; the other end of the switch S1 is connected with one end of the switch S2 and a sensitive structure middle node (node 1); the other end of the switch S2 is connected with a power ground; the other end of the capacitor Cc1 is connected to the other end of the capacitor Cc2, one end of the switch S7, and one end of the switch S8 (node 2); the other end of the switch S7 is connected with a reference voltage Vref; the other end of the switch S8 is connected with a power ground; the upper end of the sensitive structure is connected with one end of the capacitor Cc1, one end of the switch S3 and one end (node 3) of the switch S5; the other end of the switch S3 is connected with a power ground; the lower end of the sensitive structure is connected with one end of the capacitor Cc2, one end of the switch S4 and one end (node 4) of the switch S6; the other end of the switch S4 is connected with a power ground; the other end of the switch S5 is connected with one end of the capacitor Cf2 and the negative input end (node 5) of the operational amplifier AMP 1; the other end of the switch S6 is connected to one end of the capacitor Cf1 and the positive input end (node 6) of the operational amplifier AMP 1; the other end of the capacitor Cf2 is connected with the positive output end of the operational amplifier AMP1 to be YP (node 7); the other end of the capacitor Cf1 is connected to the negative output terminal YN (node 8) of the operational amplifier AMP 1.
That is, the front-end circuit of the present embodiment controls the switch S1, the switch S8, the switch S3 and the switch S4 to be closed by inputting the clock control signal Φ 1, while the switch S2, the switch S5, the switch S6 and the switch S7 remain open, and at this stage, the reference voltage Vref acts on the changed capacitance of the sensitive structure, and generates a charge proportional to the changed capacitance; then, the clock control signal Φ 2 is input to control the switch S2, the switch S5, the switch S6, and the switch S7 to be closed, and the switch S1, the switch S8, the switch S3, and the switch S4 to be opened, and at this stage, the electric charges obtained at the previous stage are amplified and output through the operational amplifier.
The front-end circuit structure applied to direct capacitance-to-digital conversion of the digital accelerometer circuit of the embodiment is obtained by analyzing a discrete-time circuit, and the output expression of the circuit structure is as follows:
where Cs is the base capacitance of the sensitive structure of the accelerometer,ΔCequal and opposite for upper and lower polar plates of accelerometer sensitive structureThe amount of capacitance change.
The front-end circuit of the embodiment has a simple structure, does not need a special analog-to-digital conversion circuit, and can also achieve the conversion from direct capacitance to digital quantity. Meanwhile, the circuit is not influenced by noise and temperature, the influence of environmental factors on voltage is reduced, and the power consumption of the module is saved.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (6)
1. A front-end circuit for direct conversion from capacitance to digital quantity is characterized by comprising an accelerometer sensitive structure, a reference voltage Vref, 2-phase non-overlapped clock control signals phi 1 and phi 2, an operational amplifier and a switch component; controlling a switch component through a clock control signal phi 1, and generating charges in direct proportion to a variable capacitor by utilizing the action of a reference voltage applied to a sensitive structure on the variable capacitor; and then, controlling the switch component through a clock control signal phi 2, so that the obtained charges are amplified through an operational amplifier, and the variable quantity which is in direct proportion to the sensitive structure can be obtained.
2. The front-end circuit for direct conversion of capacitance to digital quantity according to claim 1, further comprising a compensation capacitor Cc1 and a compensation capacitor Cc2, wherein 2 compensation capacitors are used for compensating the basic capacitance of the sensitive structure.
3. The front-end circuit for direct conversion of capacitance to digital quantity according to claim 2, further comprising an integrating capacitor Cf1 and an integrating capacitor Cf2, wherein the integrating capacitor Cf1 is connected between the negative output terminal and the positive input terminal of the operational amplifier; the integrating capacitor Cf2 is connected between the positive output terminal and the negative input terminal of the operational amplifier.
4. A capacitance-to-digital direct conversion front-end circuit according to claim 3, wherein the switch assembly comprises a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6, a switch S7 and a switch S8, wherein one end of the switch S1 is connected to the reference voltage Vref, the other end of the switch S1 is connected to the middle node of the sensitive structure and one end of the switch S2, and the other end of the switch S2 is grounded; the compensation capacitor Cc1 and the compensation capacitor Cc2 are connected in series and then connected in parallel with the upper end and the lower end of the sensitive structure, one end of a switch S7 is connected with a reference voltage Vref, a switch S7 is connected with one end of a switch S8, the other end of a switch S7 is also connected with the common connection end of the compensation capacitor Cc1 and the compensation capacitor Cc2, and the other end of the switch S8 is grounded; the upper end of the sensitive structure is also connected with one end of a switch S3 and one end of a switch S5, the other end of the switch S3 is grounded, and the other end of the switch S5 is connected with the negative input end of the operational amplifier; the lower end of the sensitive structure is also connected with one end of a switch S4 and one end of a switch S6, the other end of the switch S4 is grounded, and the other end of the switch S6 is connected with the positive input end of the operational amplifier.
5. A front-end circuit for direct conversion of capacitance to digital quantity according to claim 4, characterized in that the switch S1, the switch S8, the switch S3 and the switch S4 are controlled to be closed by the input clock control signal Φ 1, while the switch S2, the switch S5, the switch S6 and the switch S7 are kept open, at which stage the reference voltage Vref acts on the varying capacitance of the sensitive structure, generating a charge proportional to the varying capacitance; then, the clock control signal Φ 2 is input to control the switch S2, the switch S5, the switch S6, and the switch S7 to be closed, and the switch S1, the switch S8, the switch S3, and the switch S4 to be opened, and at this stage, the electric charges obtained at the previous stage are amplified and output through the operational amplifier.
6. A capacitance-to-digital direct conversion front-end circuit according to any one of claims 1 to 5, wherein the output of the front-end circuit is represented as follows:
YP is a positive output end of the operational amplifier, YN is a negative output end of the operational amplifier, Cs is a basic capacitance of the sensitive structure, and deltaC is capacitance variation quantity of an upper electrode plate and a lower electrode plate of the sensitive structure of the accelerometer, which is equal and opposite.
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| CN202010259477.7A CN111510143A (en) | 2020-04-03 | 2020-04-03 | Front-end circuit for direct conversion from capacitance to digital quantity |
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| CN202010259477.7A CN111510143A (en) | 2020-04-03 | 2020-04-03 | Front-end circuit for direct conversion from capacitance to digital quantity |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116380135A (en) * | 2023-06-06 | 2023-07-04 | 成都市晶蓉微电子有限公司 | Charge transfer balance type capacitor-to-voltage conversion circuit |
Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101924557A (en) * | 2010-08-09 | 2010-12-22 | 重庆邮电大学 | A/D converter and A/D converting method thereof based on single amplifier chaos circuit |
| CN201766574U (en) * | 2010-08-18 | 2011-03-16 | 中国电子科技集团公司第五十八研究所 | High-speed common mode insensitive charge comparator circuit |
| CN102291149A (en) * | 2011-08-25 | 2011-12-21 | 中国电子科技集团公司第二十四研究所 | Multiplicative digital-analog converter with two-stage segmental sharing operation amplifier |
| CN103219989A (en) * | 2013-04-17 | 2013-07-24 | 哈尔滨工业大学 | High-linearity sigma-delta closed loop accelerometer interface circuit |
| CN104197922A (en) * | 2014-07-31 | 2014-12-10 | 嘉兴市纳杰微电子技术有限公司 | Gyroscope two-phase sampling front-end amplifier and gyroscope signal sampling control method |
| CN104539257A (en) * | 2015-01-09 | 2015-04-22 | 杭州士兰微电子股份有限公司 | Band-pass filtering circuit, control method thereof and MEMS gyroscope drive circuit |
| CN104731425A (en) * | 2013-12-23 | 2015-06-24 | 联阳半导体股份有限公司 | Capacitor Sensor Circuit |
| CN104779959A (en) * | 2014-01-09 | 2015-07-15 | 瑞昱半导体股份有限公司 | Conversion device with offset value added and method |
| CN106330189A (en) * | 2016-08-24 | 2017-01-11 | 黄山学院 | Charge domain capacitance digital conversion circuit |
| CN107290566A (en) * | 2017-07-17 | 2017-10-24 | 四川知微传感技术有限公司 | One kind is used for the basic capacitor compensating circuit of digital accelerometer |
| US9838029B1 (en) * | 2016-12-05 | 2017-12-05 | Analog Devices Global | Adaptively controlled duty cycle clock generation circuit |
| CN108233933A (en) * | 2018-02-02 | 2018-06-29 | 中国科学院微电子研究所 | Fully differential CMOS switched-capacitor integrator |
| US20180259364A1 (en) * | 2016-08-31 | 2018-09-13 | Hitachi, Ltd. | Capacitive Sensor |
| CN109633207A (en) * | 2018-12-19 | 2019-04-16 | 哈尔滨工业大学 | A kind of digital closed loop accelerometer on piece On-line self-diagnosis examining system and method |
| CN109787563A (en) * | 2019-01-16 | 2019-05-21 | 电子科技大学 | A kind of correlated double sampling circuit based on amplifier offset compensation |
| JPWO2019092805A1 (en) * | 2017-11-08 | 2020-04-02 | 三菱電機株式会社 | Amplifier circuit and analog-to-digital conversion system including the same |
-
2020
- 2020-04-03 CN CN202010259477.7A patent/CN111510143A/en active Pending
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101924557A (en) * | 2010-08-09 | 2010-12-22 | 重庆邮电大学 | A/D converter and A/D converting method thereof based on single amplifier chaos circuit |
| CN201766574U (en) * | 2010-08-18 | 2011-03-16 | 中国电子科技集团公司第五十八研究所 | High-speed common mode insensitive charge comparator circuit |
| CN102291149A (en) * | 2011-08-25 | 2011-12-21 | 中国电子科技集团公司第二十四研究所 | Multiplicative digital-analog converter with two-stage segmental sharing operation amplifier |
| CN103219989A (en) * | 2013-04-17 | 2013-07-24 | 哈尔滨工业大学 | High-linearity sigma-delta closed loop accelerometer interface circuit |
| CN104731425A (en) * | 2013-12-23 | 2015-06-24 | 联阳半导体股份有限公司 | Capacitor Sensor Circuit |
| CN104779959A (en) * | 2014-01-09 | 2015-07-15 | 瑞昱半导体股份有限公司 | Conversion device with offset value added and method |
| CN104197922A (en) * | 2014-07-31 | 2014-12-10 | 嘉兴市纳杰微电子技术有限公司 | Gyroscope two-phase sampling front-end amplifier and gyroscope signal sampling control method |
| CN104539257A (en) * | 2015-01-09 | 2015-04-22 | 杭州士兰微电子股份有限公司 | Band-pass filtering circuit, control method thereof and MEMS gyroscope drive circuit |
| CN106330189A (en) * | 2016-08-24 | 2017-01-11 | 黄山学院 | Charge domain capacitance digital conversion circuit |
| US20180259364A1 (en) * | 2016-08-31 | 2018-09-13 | Hitachi, Ltd. | Capacitive Sensor |
| US9838029B1 (en) * | 2016-12-05 | 2017-12-05 | Analog Devices Global | Adaptively controlled duty cycle clock generation circuit |
| CN107290566A (en) * | 2017-07-17 | 2017-10-24 | 四川知微传感技术有限公司 | One kind is used for the basic capacitor compensating circuit of digital accelerometer |
| JPWO2019092805A1 (en) * | 2017-11-08 | 2020-04-02 | 三菱電機株式会社 | Amplifier circuit and analog-to-digital conversion system including the same |
| CN108233933A (en) * | 2018-02-02 | 2018-06-29 | 中国科学院微电子研究所 | Fully differential CMOS switched-capacitor integrator |
| CN109633207A (en) * | 2018-12-19 | 2019-04-16 | 哈尔滨工业大学 | A kind of digital closed loop accelerometer on piece On-line self-diagnosis examining system and method |
| CN109787563A (en) * | 2019-01-16 | 2019-05-21 | 电子科技大学 | A kind of correlated double sampling circuit based on amplifier offset compensation |
Non-Patent Citations (1)
| Title |
|---|
| 张云福: "电容式微机械陀螺仪信号检测电路" * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116380135A (en) * | 2023-06-06 | 2023-07-04 | 成都市晶蓉微电子有限公司 | Charge transfer balance type capacitor-to-voltage conversion circuit |
| CN116380135B (en) * | 2023-06-06 | 2023-08-11 | 成都市晶蓉微电子有限公司 | Charge transfer balance type capacitor-to-voltage conversion circuit |
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