CN102545901B - Second-order feedforward Sigma-Delta modulator based on successive comparison quantizer - Google Patents

Abstract

The invention discloses a second-order feedforward Sigma-Delta modulator based on a successive comparison quantizer. The Sigma-Delta modulator comprises two integrators (1) based on a switched capacitor structure in the prior art, one multi-bit successive comparison quantizer (2), one digital circuit (3) transforming into a temperature code from a binary code based on the data weighed average algorithm, one feedback digital to analog converter (4) based on a capacitor, a first adder unit (5) for computing difference between an input signal and an output signal of the feedback digital to analog converter, and a second adder unit (6) which is directly formed by a multi-input sampling switched capacitor array of the successive comparator on a feedforward path, wherein the adder unit replaces the existing extra analog adder functional circuit or a digital adder functional circuit. The obtained Sigma-Delta modulator of the invention has the advantages of ultra-low power consumption and high resolution ratio.

Description

Based on the second-order feedforward Sigma-Delta modulator successively comparing quantizer

Technical field

The present invention relates to a kind of quadrature Sigma-Delta analog-digital converter, belong to integrated circuit fields.

Background technology

Along with the professional application of consumer hand-hold electronic equipments widespread demand and medical human induction detection system, day by day extensive to high accuracy, low-power consumption, low-cost analog demand.But along with integrated circuit technology continuous renewal and along with the decline of the reduction of supply voltage and the intrinsic gain of transistor, cause Analog Circuit Design difficulty to strengthen.So need us to adopt the low power dissipation design thinking of novelty to meet the requirement in system at lower voltages.Design for low-power consumption, high accuracy, low-cost analog adopts the analog to digital converter of feedforward Sigma-Delta structure to become a trend.Wherein key component is just Sigma-Delta modulator.

Adopt feed forward architecture can make input signal not by operation method amplifier, thus the modulator performance avoiding the nonlinear distortion of operational amplifier to cause decline, and can obtain high performance analog to digital converter at low supply voltages.Traditional second-order feedforward Sigma-Delta modulator structure as shown in Figure 1, primarily of two integrators, adder before a quantizer, a quantizer, a feedback coefficient weighted-voltage D/A converter, one outputs signal the amplifier of amplification 2 times the first rank integrator, and an adder calculating difference between input signal and feedback coefficient weighted-voltage D/A converter output signal is formed.Input signal X and the first rank integrator output signal the signal after amplifying twice and second-order integrator output signal be added after be input to quantizer, after quantizing, quantizer output signal Y to subtract each other with input signal and obtains U after DAC conversion, and U is input to the first rank integrator.For ensureing high precision performance, quantizer adopts the quantizer of many bits bit wide usually.Adopt the advantage of many bits bit wide quantizer to be under the condition not increasing Sigma-Delta modulator over-sampling rate, the noise harmonics restraint ratio of modulator to be improved, the stability of system can be improved simultaneously.

Adder circuit before quantizer is made up of extra active or passive analog circuit usually, even adder functions is put into numeric field and realizes in the design that some are new.The increase of additional circuit inevitably brings the loss of power consumption.

Summary of the invention

In view of this, the object of the embodiment of the present invention is to provide a kind of new circuit structure, for removing extra adder circuit, thus reduces circuit power consumption further.

The present invention realizes by the following technical solutions:

It comprises second adder unit 6 that the multi input sampling capacitance array for successively comparing quantification of the present invention forms and two switched-capacitor integrators 1 of prior art, many bits successively compare quantizer 2, based on data weighting average algorithm convert the digital circuit 3 of thermometer code function to by binary code, second-order feedforward Sigma-Delta modulator that feedback capacity formula digital to analog converter 4, the first adder unit 5 that outputs signal difference for calculating input signal and condenser type digital to analog converter are formed, structure is as shown in Figure 2.

The first structure of second adder unit: second adder unit is by 2 ⁿindividual specific capacitance is formed, and the span of N is 2 to 8.The top crown of all electric capacity is connected with one end of a K switch, and this switch other end is connected with a voltage driver B3 output.2 ^n-1the bottom crown of individual electric capacity is by three K switch _n-1,1, K _n-1,2, K _n-1,3with the first rank integrator output terminal, voltage driver B1 output, voltage driver B2 output is connected; 2 ^n-2the bottom crown of individual electric capacity is by three K switch _n-2,1, K _n-2,2, K _n-2,3with second-order integrator output terminal, voltage driver B1 output, voltage driver B2 output is connected; 2 ^n-3individual, 2 ^n-4it is individual ... 2 ^n-(N-1)individual, 2 ^n-Nthe bottom crown of individual electric capacity is by K corresponding with it _n-3,1, K _n-3,2, K _n-3,3, K _n-4,1, K _n-4,2, K _n-4,3..., K _{n-(N-1), 1}, K _{n-(N-1), 2}, K _{n-(N-1), 3}, K _{n-N, 1}, K _{n-N, 2}, K _{n-N, 3}with signal input part, voltage driver B1 output, voltage driver B2 exports and is connected; The bottom crown of last electric capacity is by two K switch _{l, 1}, K _{l, 2}with signal input part, voltage driver B2 output is connected.

Second adder unit the second structure: second adder unit is by 2 ⁿindividual specific capacitance is formed, and the span of N is 2 to 8.The top crown of all electric capacity is connected with one end of a K switch, and this switch other end is connected with a voltage driver B3 output.2 ^n-1the bottom crown of individual electric capacity is by three K switch _n-1,1, K _n-1,2, K _n-1,3with the first rank integrator output terminal, voltage driver B1 output, voltage driver B2 output is connected; 2 ^n-2the bottom crown of individual electric capacity is by three K switch _n-2,1, K _n-2,2, K _n-2,3with signal input part, voltage driver B1 output, voltage driver B2 output is connected; 2 ^n-3individual, 2 ^n-4it is individual ... 2 ^n-(N-1)individual, 2 ^n-Nthe bottom crown of individual electric capacity is by K corresponding with it _n-3,1, K _n-3,2, K _n-3,3, K _n-4,1, K _n-4,2, K _n-4,3..., K _{n-(N-1), 1}, K _{n-(N-1), 2}, K _{n-(N-1), 3}, K _{n-N, 1}, K _{n-N, 2}, K _{n-N, 3}with second-order integrator output terminal, voltage driver B1 output, voltage driver B2 exports and is connected; The bottom crown of last electric capacity is by two K switch _{l, 1}, K _{l, 2}with second-order integrator output terminal, voltage driver B2 output is connected.

Modulator input is connected with second adder unit with first adder unit respectively;

First adder unit output is connected with the first rank integrator input;

First rank integrator output terminal is connected with second-order integrator input with second adder unit respectively;

Second-order integrator output terminal is connected with second adder unit;

Second adder unit output and many bits successively compare quantizer and are connected, and simultaneously many bits are successively compared quantizer and are connected with second adder unit by feedback signal line;

Many bits successively compare quantizer output and are connected with the digital circuit based on data weighting average algorithm;

Digital circuit output based on data weighting average algorithm is connected with the feedback coefficient weighted-voltage D/A converter based on specific capacitance structure;

Feedback coefficient weighted-voltage D/A converter output is connected with first adder unit.

This modulator input signal is directly inputted to first adder unit and second adder unit;

First adder element output signal is input to the first rank integrator input;

First rank integrator is input to second-order integrator and this signal is input to second adder unit simultaneously;

Second-order integrator is input to second adder unit;

Second adder unit is to above-mentioned three signals, and namely input signal, the first rank integrator output signal, second-order integrator output signal carry out signal sampling.In the signal sampling moment, input signal, the first rank integrator output signal, second-order integrator output signal are input on the different electric capacity in second adder unit respectively, and the ratio of the signal sampling capacitor's capacity that input signal, the first rank integrator output signal, second-order integrator output signal are corresponding is 1:2:1.When second adder unit adopts the first structure, in the signal sampling moment, K switch _n-1,1, K _n-2,1, K _n-3,1, K _n-4,1..., K _{n-(N-1), 1}, K _{n-N, 1}, K _{l, 1}, K close, other switches disconnect.First rank integrator output signal passes through K switch _n-1,1be input to 2 ^n-1the bottom crown of individual electric capacity; Second-order integrator output signal passes through K switch _n-2,1be input to 2 ^n-2the bottom crown of individual electric capacity; Input signal passes through K switch _n-3,1, K _n-4,1..., K _{n-(N-1), 1}, K _{n-N, 1}, K _{l, 1}be input to 2 ^n-3individual, 2 ^n-4it is individual ... 2 ^n-(N-1)individual, 2 ^n-Nindividual with on last electric capacity.The top crown of all electric capacity was connected with voltage driver B3 output by K switch in the signal sampling moment.When second adder unit adopts the second structure, in the signal sampling moment, K switch _n-1,1, K _n-2,1, K _n-3,1, K _n-4,1..., K _{n-(N-1), 1}, K _{n-N, 1}, K _{l, 1}, K close, other switches disconnect.First rank integrator output signal passes through K switch _n-1,1be input to 2 ^n-1the bottom crown of individual electric capacity; Input signal passes through K switch _n-2,1be input to 2 ^n-2the bottom crown of individual electric capacity; Second-order integrator output signal passes through K switch _n-3,1, K _n-4,1..., K _{n-(N-1), 1}, K _{n-N, 1}, K _{l, 1}be input to 2 ^n-3individual, 2 ^n-4it is individual ... 2 ^n-(N-1)individual, 2 ^n-Nindividual with on last electric capacity.The top crown of all electric capacity is connected with voltage driver B3 output by K switch.

After sampling, many bits successively compare quantizer and sampled signal are carried out to N time successively compare, quantized.During comparing for N time, quantizing, K switch _n-1,1, K _n-2,1, K _n-3,1, K _n-4,1..., K _{n-(N-1), 1}, K _{n-N, 1}, K _{l, 1}, K disconnect, K _{l, 2}closed, the lower step of last electric capacity is connected with voltage driver B2 output, the top crown of all electric capacity with compare quantizer input and be connected.Carry out first time compare, quantize time, K switch _n-1,2first closed, K _n-1,3disconnect, K switch _n-2,2, K _n-3,2..., K _{n-(N-1), 2}, K _{n-N, 2}disconnect, K switch _n-2,3, K _n-3,3..., K _{n-(N-1), 3}, K _{n-N, 3}closed.2 ^n-1the bottom crown of individual electric capacity passes through K switch _n-1,2be connected with voltage driver B1 output, 2 ^n-2individual, 2 ^n-3individual ..., 2 ^n-(N-1)individual, 2 ^n-Nthe bottom crown of individual electric capacity passes through K switch _n-2,3, K _n-3,3..., K _{n-(N-1), 3}, K _{n-N, 3}be connected with voltage driver B2 output.Many bits successively compare quantizer and once compare, quantize, and obtain a binary code, if this value is 1, then and K _n-1,2disconnect, K _n-1,3closed, 2 ^n-1the bottom crown of individual electric capacity passes through K switch _n-1,3be connected with voltage driver B2 output; If this value is 0, then K _n-1,2remain closed, K _n-1,3disconnect, 2 ^n-1the bottom crown of individual electric capacity passes through K switch _n-1,2be connected with voltage driver B1 output, completing first time compares to this, quantizes.First time compares, quantizes to terminate after, start to compare for the second time, quantize.Second time compare, quantize during K switch _n-1,2, K _n-1,3state with first time compare, quantize at the end of state be consistent.Carry out second time compare, quantize time, K switch _n-2,2first closed, K _n-2,3disconnect, K switch _n-3,2..., K _{n-(N-1), 2}, K _{n-N, 2}disconnect, K switch _n-3,3..., K _{n-(N-1), 3}, K _{n-N, 3}closed, 2 ^n-2the bottom crown of individual electric capacity passes through K switch _n-2,2be connected with voltage driver B1 output, 2 ^n-3individual ..., 2 ^n-(N-1)individual, 2 ^n-Nthe bottom crown of individual electric capacity passes through K switch _n-3,3..., K _{n-(N-1), 3}, K _{n-N, 3}be connected with voltage driver B2 output.Many bits successively compare quantizer and once compare, quantize, and obtain a binary code, if this value is 1, then and K _n-2,2disconnect, K _n-2,3closed, 2 ^n-2the bottom crown of individual electric capacity passes through K switch _n-2,3be connected with voltage driver B2 output, if this value is 0, then K _n-2,2remain closed, K _n-2,3disconnect, 2 ^n-2the bottom crown of individual electric capacity passes through K switch _n-2,2be connected with voltage driver B1 output, complete second time to this and compare, quantize.Second time compares, quantizes to terminate after, start to compare for the third time, quantize.During third time compares, quantizes, K switch _n-1,2, K _n-1,3state with first time compare, quantize at the end of state be consistent, K switch _n-2,2, K _n-2,3state with second time compare, quantize at the end of state be consistent.Carry out third time compare, quantize time, K switch _n-3,2first closed, K _n-3,3disconnect, K switch _n-4,2..., K _{n-(N-1), 2}, K _{n-N, 2}disconnect, K switch _n-4,3..., K _{n-(N-1), 3}, K _{n-N, 3}closed.2 ^n-3the bottom crown of individual electric capacity passes through K switch _n-3,2be connected with voltage driver B1 output, 2 ^n-4individual ..., 2 ^n-(N-1)individual, 2 ^n-Nthe bottom crown of individual electric capacity passes through K switch _n-4,3..., K _{n-(N-1), 3}, K _{n-N, 3}be connected with voltage driver B2 output.Many bits successively compare quantizer and once compare, quantize, and obtain a binary code, if this value is 1, then and K _n-3,2disconnect, K _n-3,3closed, 2 ^n-3the bottom crown of individual electric capacity passes through K switch _n-3,3be connected with voltage driver B2 output, if this value is 0, then K _n-3,2remain closed, K _n-3,3disconnect, 2 ^n-3the bottom crown of individual electric capacity passes through K switch _n-3,2be connected with voltage driver B1 output, completing third time compares to this, quantizes.The like, during comparing for the N time, quantizing, K switch _n-1,2, K _n-1,3state with first time compare, quantize at the end of state be consistent, K switch _n-2,2, K _n-2,3state with second time compare, quantize at the end of state be consistent ..., K switch _{n-(N-1), 2}, K _{n-(N-1), 3}state with comparing for the N-1 time, quantize at the end of state be consistent.When carrying out comparing for the N time, quantizing, K switch _{n-N, 2}first closed, K _{n-N, 3}disconnect, 2 ^n-Nthe bottom crown of individual electric capacity passes through K switch _{n-N, 2}be connected with voltage driver B1 output, many bits successively compare quantizer and once compare, quantize, and obtain a binary code, if this value is 1, then and K _{n-N, 2}disconnect, K _{n-N, 3}closed, 2 ^n-Nthe bottom crown of individual electric capacity passes through K switch _{n-N, 3}be connected with voltage driver B2 output, if this value is 0, then K _{n-N, 2}remain closed, K _{n-N, 3}disconnect, 2 ^n-Nthe bottom crown of individual electric capacity passes through K switch _{n-N, 2}be connected with voltage driver B1 output, complete to this N time to compare, quantize.

Many bits successively compare quantizer and complete the rear many bit binary code exported of quantification by converting thermometer code to based on the digital circuit of data weighting average algorithm;

The thermometer code exported controls to obtain digital to analog converter output signal based on the feedback coefficient weighted-voltage D/A converter of capacitance structure; The output signal of digital to analog converter is input to first adder unit and input signal poor, the signal done after difference is input to the input of the first rank integrator.

In the present invention, analog signal V is inputted _in, the first rank integrators output signal V _in1, second-order integrator output signal V _in2electric capacity in the second adder unit that sampling instant is formed by multi input capacitor array respectively carries out bottom crown sampling, and Fig. 3 is the sampling instant schematic diagram of a kind of structure of second adder unit.Be different from traditional quantizer sampling array electric capacity that successively compares at sampling instant second adder unit only to sample to single input signal.In relatively moment, what second adder cell capacitance array reverted to prior art successively compares quantizer class binary weights sampling capacitance array, and Fig. 4 is that a kind of structure of second adder unit is at first time relatively moment circuit structure diagram.Utilize law of conservation of charge, can obtain:

$V_X=\frac{(V_{\mathrm{ref}1}+V_{\mathrm{ref}2}+{2V}_{\mathrm{ref}3})}{2}-\frac{1}{4}({2V}_{\mathrm{in}1}+V_{\mathrm{in}2}+V_{\mathrm{in}})---\left(1\right)$

Wherein V _ref3for input common-mode signal, V _ref2, V _ref1for comparator reference voltage.Can find out that from formula (1) multi input capacitor array of the present invention achieves the first rank integrator output signal V in sampling, the one-period that compares _in1amplify 2 times, achieve input analog signal V _in, amplify 2 times of first rank integrators output signal V _in1, second-order integrator output signal V _in2addition function, simultaneously 2V _in1+ V _in2+ V _inadditive quantity done the computing reducing 4 times.Right side Section 2 constant coefficient in formula (1) the attenuation coefficient introduced due to system configuration, can by increasing input signal V _inor reduce quantizer reference voltage V _rcompensate.

Adopt prior art to realize two rank integrators based on the integrating circuit of Switch capacitor structure in Sigma-Delta modulator of the present invention, for accumulate input signal and feedback coefficient weighted-voltage D/A converter output between difference.

What the many bits in Sigma-Delta modulator of the present invention successively compared that quantizer adopts prior art successively compares quantizer, successively compares in quantizer and adopts dynamical comparator, for reducing power consumption.

Binary code in Sigma-Delta modulator of the present invention converts thermometer code Digital Logic to and realizes based on the design of prior art data weighting average algorithm, is used for reducing being changed the line of production raw non-linear mistake by multi-bit mould.

Feedback coefficient weighted-voltage D/A converter in Sigma-Delta modulator of the present invention adopts prior art to realize based on specific capacitance element design.

The first adder unit outputing signal difference for calculating input signal and condenser type digital to analog converter in Sigma-Delta modulator of the present invention is realized by the sampling capacitance in the first rank integrator.

The present invention compared with prior art, has following advantage and beneficial effect:

In Sigma-Delta modulator of the present invention, addition function realizes by successively comparing the multi input sampling capacitance array before quantizer, eliminates extra analog or digital adder circuit, whole circuit power consumption is reduced, save circuit area, reduce production cost.

Accompanying drawing explanation

Fig. 1 is traditional second-order feedforward Sigma-Delta modulator structured flowchart;

Fig. 2 is second-order feedforward Sigma-Delta modulator structured flowchart of the present invention;

Fig. 3 is a kind of structure capacitive array of second adder unit sampling instant schematic diagram;

Fig. 4 is a kind of structure capacitive array of second adder unit first time relatively moment schematic diagram;

The Sigma-Delta modulator circuit structure diagram that Fig. 5 provides for the embodiment of the present invention;

The Sigma-Delta modulator circuit timing diagram that Fig. 6 provides for the embodiment of the present invention;

The chopper stabilized amplifier structured flowchart that Fig. 7 provides for the embodiment of the present invention;

The circuit structure diagram of telescopic operational amplifier on a large scale that Fig. 8 provides for the embodiment of the present invention;

The low-power consumption comparison circuit structure chart that Fig. 9 provides for the embodiment of the present invention;

The asynchronous clock control circuit that Figure 10 A provides for the embodiment of the present invention;

The asynchronous clock timing diagram that Figure 10 B provides for the embodiment of the present invention;

The data weighting average algorithm schematic diagram that Figure 11 provides for the embodiment of the present invention;

Wherein 1 represents two integrators based on Switch capacitor structure, 2 expressions successively compare quantizer, 3 represent the digital circuit being converted to thermometer code based on data weighting average algorithm by binary code, 4 represent feedback coefficient weighted-voltage D/A converter, 5 represent first adder unit, 6 represent second adder unit, 50 represent chopper stabilized operational amplifier, 51 represent that 4 bit asynchronous successively compare quantizer, 52 represent that 4 bit binary code convert 15 bits of temperature code digital logic module to, 53 represent 4 bit feedback digital to analog converters, 70 represent pMOS switch, 71 represent bootstrapped switch, 101 represent asynchronous clock unit.

Embodiment

The embodiment of the present invention proposes a kind of feedforward step low-pass Sigma-Delta modulator successively comparing quantizer based on 4 bit asynchronous adopting multi input sampled, switched capacitor array addi device, and Fig. 5 is the modulator realized with this differential configuration that single-end circuit structural representation describes.Circuit contains two Switch capacitor structure integrating circuit based on prior art, and the operational amplifier wherein in the first rank integrator adopts chopper stabilized operational amplifier 50 structure to realize; Second adder unit 6,4 bit asynchronous based on prior art successively compare quantizer 51, the 4 bit feedback digital to analog converters 53 4 bit binary code being converted to 15 bits of temperature code digital logic module, 52, specific capacitance structure based on prior art based on prior art.Its sequential as shown in Figure 6.Feed forward architecture can reduce system to the nonlinear requirement of operational amplifier in integrator, reduces Analog Circuit Design difficulty.Multi-bit quantizer can improve the signal of system to noise distortion ratio not increasing under system over-sampling rate sum-product intergrator exponent number condition.

In low pass Sigma-Delta modulator, the analog circuit that contribution low-frequency noise is maximum is the operational amplifier being arranged in the first rank integrator.In order to suppress low-frequency noise, the operational amplifier in the first rank integrator adopts chopped wave stabilizing (chopper stabilization) amplifier of prior art, as shown in Figure 7.The input switch of this amplifier adopts pMOS switch 70; Output switch adopts the bootstrapped switch 71 of prior art, and its effect ensures the linearity of signal transmission.Switch control clock adopts the Clock Design of the two-phase non-overlapping of prior art, and sequential as shown in Figure 6.

Adopt the second adder unit in the present invention, the output valve of adder is inevitably along with system attenuation, and its coefficient is this system attenuation can be offset by increasing input signal or reducing quantizer reference voltage.The present embodiment adopts and input signal is increased 1 times of method simultaneously quantizer reference voltage being reduced by 1 times to offset this system attenuation.Input signal increase causes operational amplifier needs in integrator to process the signal of more great dynamic range.The operational amplifier of the telescoping structure on a large scale of prior art is adopted, as shown in Figure 8 in the present embodiment.The large-scale dynamic property of amplifier input and output is by allowing the tail current source transistor of tube-in-tube structure be operated in linear zone to realize.This circuit designs under SMIC 65nm technique, and supply voltage is 1V, known by circuit simulation, is that under the condition of 10pF, the gain of operational amplifier reaches 54dB, and gain bandwidth product reaches 14MHz in load capacitance.

In the present embodiment, many bits successively compare quantizer and adopt 4 bit asynchronous of prior art successively to compare quantizer.Traditional multi-bit quantizer adopts the analog to digital converter of Flash structure usually.This circuit structure area is large, and power consumption is high, is unsuitable for low-power consumption application.Employing is successively compared quantizer and can be solved the problem, and this Structure Quantification device only comprises a comparator, can eliminate the problem of the comparator imbalance voltage mismatch brought by multiple comparator.Comparator in the present embodiment quantizer adopts the low power consumption comparator of prior art, and as shown in Figure 9, this structure does not have DC bias circuit, can reach ultralow quiescent dissipation, and average power consumption is only relevant to sample frequency.

Asynchronous clock control circuit is used for the comparison clock CLK of comparator in generation homogenizer and the integration clock Φ of the first rank integration period _f, as shown in Figure 10 A.Asynchronous clock unit 101 adopts existing techniques in realizing, the circuit of this technology is adopted to be published in " A 30fJ/Conversion-Step 8b 0-to10MS/s Asynchronous SAR ADC in 90nm CMOS " 2010 IEEE ISSCC Dig.Tech.Papers first, pp388-389, in this example, asynchronous sequencing control as shown in Figure 10 B.

In the present embodiment, second adder unit adopts the second adder unit of the first structure.In the signal sampling moment, K switch in second adder unit _3,1, K _2,1, K _1,1, K _0,1, K _{l, 1}, K close, other switches disconnect.First rank integrator output signal passes through K switch _3,1be input to 2 ³the bottom crown of individual electric capacity; Second-order integrator output signal passes through K switch _2,1be input to 2 ²the bottom crown of individual electric capacity; Input signal passes through K switch _1,1, K _{, 1}, K _{l, 1}be input to 2 ¹individual, 2 with on last electric capacity.The top crown of all electric capacity is connected with voltage driver B3 output by K switch.As shown in figure 11.

After sampling, 4 bits successively compare quantizer and sampled signal are carried out to 4 times successively compare, quantized.During comparing, quantizing, K switch _3,1, K _2,1, K _1,1, K _{, 1}, K _{l, 1}, K disconnect, K _{l, 2}closed, the lower step of last electric capacity is connected with voltage driver B2 output, the top crown of all electric capacity with compare quantizer input and be connected.Carry out first time compare, quantize time, K switch _3,2first closed, K _3,3disconnect, K switch _2,2, K _1,2, K _{, 2}disconnect, K switch _2,3, K _1,3, K _0,3closed.2 ³the bottom crown of individual electric capacity passes through K switch _3,2be connected with voltage driver B1 output, 2 ²individual, 2 ¹individual, 2 ⁰the bottom crown of individual electric capacity passes through K switch _2,3, K _1,3, K _{, 3}be connected with voltage driver B2 output, as shown in figure 12.4 bits successively compare quantizer and once compare, quantize, and obtain a binary code, if this value is 1, then and K _3,2disconnect, K _3,3closed, 2 ³the bottom crown of individual electric capacity passes through K switch _3,3be connected with voltage driver B2 output, if this value is 0, then K _3,2remain closed, K _3,3disconnect, 2 ³the bottom crown of individual electric capacity passes through K switch _3,2be connected with voltage driver B1 output, completing first time compares to this, quantizes.First time compares, quantizes to terminate after, start to compare for the second time, quantize.Second time compare, quantize during K switch _3,2, K _3,3state with first time compare, quantize at the end of state be consistent.Carry out second time compare, quantize time, K switch _2,2first closed, K _2,3disconnect, K switch _1,2, K _{, 2}disconnect, K switch _1,3, K _{, 3}closed.2 ²the bottom crown of individual electric capacity passes through K switch _2,2be connected with voltage driver B1 output, 2 ¹individual, 2 ⁰the bottom crown of individual electric capacity passes through K switch _1,3, K _0,3be connected with voltage driver B2 output.4 bits successively compare quantizer and once compare, quantize, and obtain a binary code, if this value is 1, then and K _2,2disconnect, K _2,3closed, 2 ²the bottom crown of individual electric capacity passes through K switch _2,3be connected with voltage driver B2 output, if this value is 0, then K _2,2remain closed, K _2,3disconnect, 2 ²the bottom crown of individual electric capacity passes through K switch _2,2be connected with voltage driver B1 output, complete second time to this and compare, quantize.Second time compares, quantizes to terminate after, start to compare for the third time, quantize.During third time compares, quantizes, K switch _3,2, K _3,3state with first time compare, quantize at the end of state be consistent, K switch _2,2, K _2,3state with second time compare, quantize at the end of state be consistent.Carry out third time compare, quantize time, K switch _1,2first closed, K _1,3disconnect, K switch _{, 2}disconnect, K switch _{, 3}closed.2 ¹the bottom crown of individual electric capacity passes through K switch _1,2be connected with voltage driver B1 output, the bottom crown of 2 electric capacity passes through K switch _0,3be connected with voltage driver B2 output.4 bits successively compare quantizer and once compare, quantize, and obtain a binary code, if this value is 1, then and K _1,2disconnect, K _1,3closed, 2 ¹the bottom crown of individual electric capacity passes through K switch _1,3be connected with voltage driver B2 output, if this value is 0, then K _1,2remain closed, K _1,3disconnect, 2 ¹the bottom crown of individual electric capacity passes through K switch _1,2be connected with voltage driver B1 output, completing third time compares to this, quantizes.The 4th compares, quantize during, K switch _3,2, K _3,3state with first time compare, quantize at the end of state be consistent, K switch _2,2, K _2,3state with second time compare, quantize at the end of state be consistent, K switch _1,2, K _1,3state with third time compare, quantize at the end of state be consistent.When carrying out the 4th time to compare, quantizing, K switch _{, 2}first closed, K _0,3disconnect, 2 ⁰the bottom crown of individual electric capacity passes through K switch _{, 2}be connected with voltage driver B1 output, 4 bits successively compare quantizer and once compare, quantize, and obtain a binary code, if this value is 1, then and K _0,2disconnect, K _{, 3}closed, the bottom crown of 2 electric capacity passes through K switch _{, 3}be connected with voltage driver B2 output, if this value is 0, then K _{, 2}remain closed, K _0,3disconnect, 2 ⁰the bottom crown of individual electric capacity passes through K switch _{, 2}be connected with voltage driver B1 output, complete to this 4th time to compare, quantize.Wherein V _ref3for input common-mode signal, V _ref2, V _ref1for comparator reference voltage.In the present embodiment, V _ref3=0.6V, V _ref2=0.35V, V _ref1=0V.

4 bit binary code realize based on the design of prior art data weighting average algorithm when converting 15 bits of temperature code logic digital circuits to, while converting binary code to thermometer code also with based on the operation that this output temperature code is shifted of the result of once output temperature code, algorithm schematic diagram is as shown in figure 13.

4 bit feedback digital to analog converters 53 realize according to the cell capacitance structural design based on prior art.The thermometer code exported is sent to digital to analog converter, controls the switch in 15 tunnel circuit branch.Such as, when the input control signal of first via capacitive branch is high level, thermometer code signal corresponding to Ji Gai road is 1, and the control switch logic on this road is at clock Φ _f1for time high, Φ _p1for height, Φ _p1the switch controlled closes, Φ _n1for low, Φ _n1the switch controlled disconnects, electric capacity C _f1'slower step and V _refpconnect; When the input control signal of first via capacitive branch is low level, thermometer code signal corresponding to Ji Gai road is 0, and the control switch logic on this road is at clock Φ _f1for time high, Φ _n1for height, Φ _n1the switch controlled closes, Φ _p1for low, Φ _p1the switch controlled disconnects, electric capacity C _f1lower step and V _refnconnect; Wherein V _refpfor high feedback reference voltage, V _refnfor low feedback reference voltage, i.e. V _refp>V _refn.In the present embodiment, V _refp=0.7V, V _refn=0V.

For calculating input signal and condenser type digital to analog converter outputs signal the adder of difference by sampling capacitance in the rank integrator on the first rank _s1realize.

The present embodiment designs under SMIC 65nm CMOS technology, known by circuit simulation, be the sinusoidal signal of 5kHz at input signal, its peak-to-peak value is 600mV, when sample frequency is 1MHz, Sigma-Delta modulator peak signal noise harmonic ratio can reach 94 decibels, and circuit integrity power consumption is 340uW.

The above, be only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention, and all any amendments done within the spirit and principles in the present invention, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (1)

1. a Sigma-Delta modulator, it is characterized in that: it comprises two integrators based on switched-capacitor circuit, more than one, bit successively compares quantizer, a digital circuit being converted to thermometer code function by binary code based on data weighting average algorithm, a feedback coefficient weighted-voltage D/A converter based on specific capacitance structure; A first adder unit; A second adder unit;

The first structure of second adder unit: second adder unit comprises 2 ⁿindividual specific capacitance, the span of N is 2 to 8; The top crown of all electric capacity is connected with one end of a K switch, and this switch other end is connected with a voltage driver B3 output; 2 ^n-1the bottom crown of individual electric capacity is by three K switch _n-1,1, K _n-1,2, K _n-1,3with the first rank integrator output terminal, voltage driver B1 output, voltage driver B2 output is connected; 2 ^n-2the bottom crown of individual electric capacity is respectively by three K switch _n-2,1, K _n-2,2, K _n-2,3with second-order integrator output terminal, voltage driver B1 output, voltage driver B2 output is connected; 2 ^n-3individual, 2 ^n-4individual, 2 ^n-(N-1)individual, 2 ^n-Nthe bottom crown of individual electric capacity is by K corresponding with it _n-3,1, K _n-3,2, K _n-3,3, K _n-4,1, K _n-4,2, K _n-4,3, K _{n-(N-1), 1}, K _{n-(N-1), 2}, K _{n-(N-1), 3}, K _{n-N, 1}, K _{n-N, 2}, K _{n-N, 3}with signal input part, voltage driver B1 output, voltage driver B2 exports and is connected; The bottom crown of last electric capacity is by two K switch _{l, 1}, K _{l, 2}with signal input part, voltage driver B2 output is connected;

Second adder unit the second structure: second adder unit comprises 2 ⁿindividual specific capacitance, the span of N is 2 to 8; The top crown of all electric capacity is connected with one end of a K switch, and this switch other end is connected with a voltage driver B3 output; 2 ^n-1the bottom crown of individual electric capacity is by three K switch _n-1,1, K _n-1,2, K _n-1,3with the first rank integrator output terminal, voltage driver B1 output, voltage driver B2 output is connected; 2 ^n-2the bottom crown of individual electric capacity is respectively by three K switch _n-2,1, K _n-2,2, K _n-2,3with signal input part, voltage driver B1 output, voltage driver B2 output is connected; 2 ^n-3individual, 2 ^n-4individual, 2 ^n-(N-1)individual, 2 ^n-Nthe bottom crown of individual electric capacity is by K corresponding with it _n-3,1, K _n-3,2, K _n-3,3, K _n-4,1, K _n-4,2, K _n-4,3, K _{n-(N-1), 1}, K _{n-(N-1), 2}, K _{n-(N-1), 3}, K _{n-N, 1}, K _{n-N, 2}, K _{n-N, 3}with second-order integrator output terminal, voltage driver B1 output, voltage driver B2 exports and is connected; The bottom crown of last electric capacity is by two K switch _{l, 1}, K _{l, 2}with second-order integrator output terminal, voltage driver B2 output is connected;

Modulator input is connected with second adder unit with first adder unit respectively;

First adder unit output is connected with the first rank integrator input;

First rank integrator output terminal is connected with second-order integrator input with second adder unit respectively;

Second-order integrator output terminal is connected with second adder unit;

Second adder unit output and many bits successively compare quantizer and are connected, and simultaneously many bits are successively compared quantizer and are connected with second adder unit by feedback signal line;

Many bits successively compare quantizer output and are connected with the digital circuit based on data weighting average algorithm;

Digital circuit output based on data weighting average algorithm is connected with the feedback coefficient weighted-voltage D/A converter based on specific capacitance structure;

Feedback coefficient weighted-voltage D/A converter output is connected with first adder unit.