CN102545901B - Second-order feedforward Sigma-Delta modulator based on successive comparison quantizer - Google Patents

Abstract

The invention discloses a feed-forward second-order Sigma-Delta modulator based on successive comparison and quantization. The Sigma-Delta modulator of the present invention comprises two integrators (1) based on the switched capacitor structure of the prior art, a multi-bit successive comparison quantizer (2), a data weight average algorithm based on binary codes converted into A digital circuit (3) for the temperature code, a capacitance-based feedback DAC (4), a first adder unit (5) that calculates the difference between the input signal and the output signal of the feedback DAC. A second adder unit (6) on the feed-forward path directly formed by a multi-input sampling switched capacitor array of successive comparators, which replaces the current circuit through an additional analog adder function or a digital adder function circuit. The Sigma-Delta modulator obtained by the invention has the characteristics of ultra-low power consumption and high resolution.

Description

Second-Order Feedforward Sigma-Delta Modulator Based on Successive Comparison Quantizer

technical field

The invention relates to a Sigma-Delta analog-to-digital converter, which belongs to the field of integrated circuits.

Background technique

With the widespread demand for consumer handheld electronic devices and the professional application of medical human body sensing detection systems, the demand for high-precision, low-power, and low-cost analog-to-digital converters has become increasingly widespread. However, with the continuous update of the integrated circuit technology and the decrease of the power supply voltage and the decrease of the intrinsic gain of the transistor, the difficulty of analog circuit design is increased. Therefore, we need to adopt innovative low-power design ideas at low voltage to meet the requirements of the system. For the design of low power consumption, high precision, low-cost analog-to-digital converters, it has become a trend to adopt feed-forward Sigma-Delta structured analog-to-digital converters. The key part is the Sigma-Delta modulator.

The feed-forward structure can prevent the input signal from passing through the operational amplifier, thereby avoiding the performance degradation of the modulator caused by the nonlinear distortion of the operational amplifier, and obtaining a high-performance analog-to-digital converter at a low power supply voltage. The structure of the traditional second-order feedforward Sigma-Delta modulator is shown in Figure 1. It mainly consists of two integrators, an adder before the quantizer, a quantizer, a feedback digital-to-analog converter, and a first-order integral An amplifier that doubles the output signal of the converter, and an adder that calculates the difference between the input signal and the output signal of the feedback digital-to-analog converter. The input signal X and the output signal of the first-order integrator twice amplified are added to the output signal of the second-order integrator and then input to the quantizer. After quantization, the output signal Y of the quantizer is converted by DAC and compared with the input signal. Subtract to get U, and U is input to the first-order integrator. In order to ensure high-precision performance, the quantizer usually adopts a quantizer with a multi-bit bit width. The advantage of using a multi-bit bit width quantizer is that the noise harmonic rejection ratio of the modulator can be improved without increasing the oversampling rate of the Sigma-Delta modulator, and the stability of the system can be improved at the same time.

The adder circuit before the quantizer usually consists of additional active or passive analog circuits, and in some new designs, the adder function is even implemented in the digital domain. The increase of additional circuits inevitably brings about the loss of power consumption.

Contents of the invention

In view of this, the purpose of the embodiments of the present invention is to provide a new circuit structure for removing an extra adder circuit, thereby further reducing circuit power consumption.

The present invention is realized by adopting the following technical solutions:

It comprises the second adder unit 6 that is used for the multi-input sampling capacitor array of the present invention to compare quantization successively and two switched capacitor integrators 1 of the prior art, multi-bit successive comparison quantizer 2, based on data weight average algorithm A second-order second-order circuit composed of a digital circuit 3 with a function of converting binary code into temperature code, a feedback capacitive digital-to-analog converter 4, and a first adder unit 5 for calculating the difference between the input signal and the output signal of the capacitive digital-to-analog converter Feedforward Sigma-Delta modulator, the structure shown in Figure 2.

The first structure of the second adder unit: the second adder unit is composed of 2 ^N unit capacitors, and the value of N ranges from 2 to 8. The upper plates of all capacitors are connected to one end of a switch K, and the other end of the switch is connected to the output end of a voltage driver B3. The lower plate _of 2 ^N-1 _capacitors is connected to the output terminal of the first-order integrator, the output terminal of the voltage driver _B1 , and the voltage The output terminals of the driver B2 are connected; the lower plates of 2 ^N-2 capacitors are connected to the output terminals of the second-order integrator through three switches K _N-2,1 , K _N-2,2 , K _N-2,3 , and the voltage The output terminal of the driver B1 is connected to the output terminal of the voltage driver B2; 2 ^N-3 , 2 ^N-4 , ... 2 ^N-(N-1) , the lower plates of the 2 ^NN capacitors pass through the corresponding K _{N -3,1} 、K _N-3,2 、K _N-3,3 ，K _N-4,1 、K _N-4,2 、K _N-4,3 ，…，K _{N-(N-1) ,1} , K _N-(N-1),2 , K _N-(N-1),3 , K _NN,1 , K _NN,2 , K _NN,3 and signal input terminal, voltage driver B1 output terminal, The output of the voltage driver B2 is connected; the lower plate of the last capacitor is connected to the signal input terminal and the output terminal of the voltage driver B2 through two switches K _L,1 and K _L, 2.

The second structure of the second adder unit: the second adder unit is composed of 2 ^N unit capacitors, and the value of N ranges from 2 to 8. The upper plates of all capacitors are connected to one end of a switch K, and the other end of the switch is connected to the output end of a voltage driver B3. The lower plate _of 2 ^N-1 _capacitors is connected to the output terminal of the first-order integrator, the output terminal of the voltage driver _B1 , and the voltage The output terminal of the driver B2 is connected; the lower plates of 2 ^N-2 capacitors are connected to the signal input terminal and the output terminal of the voltage driver B1 through three switches K _N-2,1 , K _N-2,2 , K _N-2,3 , the output terminal of the voltage driver B2 is connected; 2 ^N-3 , 2 ^N-4 , ... 2 ^N-(N-1) , the lower plates of the 2 ^NN capacitors pass through the corresponding K _N-3,1 , K _N-3,2 , K _N-3,3 , K _N-4,1 , K _N-4,2 , K _N-4,3 ,…, K _N-(N-1),1 , K _N-(N-1),2 , K _N-(N-1),3 , K _NN,1 , K _NN,2 , K _NN,3 and the output terminal of the second-order integrator, the output terminal of the voltage driver B1, The output of the voltage driver B2 is connected; the lower plate of the last capacitor is connected to the output terminal of the second-order integrator and the output terminal of the voltage driver B2 through two switches K _L,1 and K _L,2 .

The modulator input terminal is respectively connected with the first adder unit and the second adder unit;

The output end of the first adder unit is connected to the input end of the first-order integrator;

The output terminal of the first-order integrator is respectively connected with the second adder unit and the input terminal of the second-order integrator;

The output end of the second-order integrator is connected to the second adder unit;

The output end of the second adder unit is connected to the multi-bit successive comparison quantizer, and the multi-bit successive comparison quantizer is connected to the second adder unit through the feedback signal line;

The output terminal of the multi-bit successive comparison quantizer is connected with a digital circuit based on a data weight averaging algorithm;

The output terminal of the digital circuit based on the data weight average algorithm is connected with the feedback digital-to-analog converter based on the unit capacitance structure;

The output terminal of the feedback digital-to-analog converter is connected with the first adder unit.

The modulator input signal is directly input to the first adder unit and the second adder unit;

The output signal of the first adder unit is input to the input terminal of the first-order integrator;

The output signal of the first-order integrator is input to the second-order integrator while the signal is input to the second adder unit;

The output signal of the second-order integrator is input to the second adder unit;

The second adder unit performs signal sampling on the above three signals, namely the input signal, the output signal of the first-order integrator, and the output signal of the second-order integrator. At the moment of signal sampling, the input signal, the output signal of the first-order integrator, and the output signal of the second-order integrator are respectively input to different capacitors in the second adder unit, and the input signal, the output signal of the first-order integrator, and the output signal of the second The ratio of the signal sampling capacitor value corresponding to the output signal of the order integrator is 1:2:1. When the second adder unit adopts the first structure, at the moment of signal sampling, switches K _N-1,1 , K _N-2,1 , K _N-3,1 , K _N-4,1 ,..., K _{N -(N-1),1} , K _NN,1 , K _L,1 , K are closed, and the other switches are opened. The output signal of the first-order integrator is input to the lower plates of 2 ^N-1 capacitors through the switch K _N-1,1 ; the output signal of the second-order integrator is input to the 2 ^N-2 capacitors through the switch K _N-2,1 The lower plate of the capacitor; the input signal is input to 2 ^N through switches K _N-3,1 , K _N-4,1 ,…, K _N-(N-1),1 , K _NN,1 , K _L,1 ^-3 , 2 ^N-4 , ... 2 ^N-(N-1) , 2 ^NN and the last capacitor. The upper plates of all capacitors are connected to the output terminal of the voltage driver B3 through the switch K at the moment of signal sampling. When the second adder unit adopts the second structure, at the moment of signal sampling, switches K _N-1,1 , K _N-2,1 , K _N-3,1 , K _N-4,1 ,..., K _{N -(N-1),1} , K _NN,1 , K _L,1 , K are closed, and the other switches are opened. The output signal of the first-order integrator is input to the lower plate of 2 ^N-1 capacitors through switch K _N-1,1 ; the input signal is input to the lower plate of 2 ^N-2 capacitors through switch K _N-2,1 ;The output signal of the second-order integrator is input to 2 ^N through switches K _N-3,1 , K _N-4,1 ,..., K _N-(N-1),1 , K _NN,1 , K _L,1 ^-3 , 2 ^N-4 , ... 2 ^N-(N-1) , 2 ^NN and the last capacitor. The upper plates of all capacitors are connected to the output terminal of the voltage driver B3 through the switch K.

After sampling, the multi-bit successive comparison quantizer performs N times successive comparison and quantization on the sampled signal. During N times of comparison and quantization, switches K _N-1,1 , K _N-2,1 , K _N-3,1 , K _N-4,1 , ..., K _N-(N-1),1 , K _NN,1 , K _L,1 , and K are disconnected, K _L,2 is closed, the lower plate of the last capacitor is connected to the output terminal of the voltage driver B2, and the upper plates of all capacitors are connected to the input terminals of the comparison quantizer. When performing the first comparison and quantization, the switch K _N-1,2 is first closed, K _N-1,3 is opened, and the switches K _N-2,2 , K _N-3,2 , ..., K _{N-( N-1),2} , K _NN,2 are turned off, switches K _N-2,3 , K _N-3,3 , . . . , K _N-(N-1),3 , K _NN,3 are closed. The lower plates of 2 ^N-1 capacitors are connected to the output terminal of the voltage driver B1 through switches K _N-1 , 2 ^{, 2 N-2} , 2 ^N-3 , ..., 2 ^N-(N-1) , The lower plates of the 2 ^NN capacitors are connected to the output terminal of the voltage driver B2 through switches K _N-2,3 , K _N-3,3 , . . . , K _N-(N-1),3 , K _NN,3 . The multi-bit sequential comparison quantizer performs a comparison and quantization to obtain a one-bit binary code. If the value is 1, K _{N-1, 2} will be disconnected, K _{N-1, 3} will be closed, and the next capacitors of 2 ^N-1 The plate is connected to the output terminal of the voltage driver B2 through the switch K _{N-1, 3} ; if the value is 0, K _{N-1, 2} remains closed, K _{N-1, 3} is disconnected, and 2 ^N-1 capacitors The lower plate is connected to the output terminal of the voltage driver B1 through the switch K _N-1,2 , and the first comparison and quantification are completed here. After the first comparison and quantification is completed, the second comparison and quantification starts. The state of the switches K _N-1,2 and K _N-1,3 during the second comparison and quantization is consistent with the state at the end of the first comparison and quantization. When performing the second comparison and quantization, the switch K _N-2,2 is first closed, K _N-2,3 is opened, and the switches K _N-3,2 , ..., K _N-(N-1),2 , K _NN,2 is disconnected, switches K _N-3,3 ,..., K _N-(N-1),3 , K _NN,3 are closed, and the lower plates of 2 ^N-2 capacitors pass through switches K _{N-2 ,2} is connected to the output terminal of the voltage driver B1, and the lower plates of 2 ^N-3 , ..., 2 ^N-(N-1) , and 2 ^NN capacitors pass through switches K _N-3,3 , ..., K _{N- (N-1),3} and K _NN,3 are connected to the output terminal of the voltage driver B2. The multi-bit sequential comparison quantizer performs a comparison and quantization to obtain a one-bit binary code. If the value is 1, K _{N-2, 2} is disconnected, K _{N-2, 3} is closed, and the next capacitors of 2 ^N-2 The plate is connected to the output terminal of the voltage driver B2 through the switch K _N-2,3 . If the value is 0, K _N-2,2 remains closed, K _N-2,3 is disconnected, and the 2 ^N-2 capacitors The lower plate is connected to the output terminal of the voltage driver B1 through the switch K _N-2,2 , and the second comparison and quantification are completed here. After the second comparison and quantification is completed, the third comparison and quantification starts. During the third comparison and quantization, the states of the switches K _N-1,2 and K _N-1,3 are consistent with those at the end of the first comparison and quantization, and the states of the switches K _N-2,2 and K _N-2,3 The state remains the same as the state at the end of the second comparison and quantization. When performing the third comparison and quantization, the switch K _N-3,2 is first closed, K _N-3,3 is opened, and the switches K _N-4,2 , ..., K _N-(N-1),2 , K _NN,2 is open, switches K _N-4,3 , . . . , K _N-(N-1),3 , K _NN,3 are closed. The lower plates of 2 ^N-3 capacitors are connected to the output terminal of the voltage driver B1 through the switch K _N-3,2 , and the lower plates of 2 ^N-4 , ..., 2 ^N-(N-1) , 2 ^NN capacitors The plates are connected to the output terminal of the voltage driver B2 through switches K _N-4,3 , . . . , K _N-(N-1),3 , K _NN,3 . The multi-bit sequential comparison quantizer performs a comparison and quantization to obtain a one-bit binary code. If the value is 1, K _{N-3, 2} is disconnected, K _{N-3, 3} is closed, and 2 ^N-3 capacitors are connected The plate is connected to the output terminal of the voltage driver B2 through the switch K _N-3,3 . If the value is 0, K _N-3,2 remains closed, K _N-3,3 is disconnected, and the 2 ^N-3 capacitors The lower plate is connected to the output terminal of the voltage driver B1 through the switch K _N-3,2 , and the third comparison and quantification are completed here. By analogy, during the Nth comparison and quantization period, the state of the switches K _N-1,2 , K _N-1,3 is consistent with the state at the end of the first comparison and quantization, and the switches K _N-2,2 , K _{N- 2, 3} state is consistent with the second comparison and the state at the end of quantization, ..., switch K _{N-(N-1), 2} , K _{N-(N-1), 3} state is the same as the N-1th comparison, The state remains consistent at the end of quantization. When performing the Nth comparison and quantization, the switch K _{NN, 2} is first closed, K _{NN, 3} is disconnected, and the lower plates of the 2 ^NN capacitors are connected to the output terminal of the voltage driver B1 through the switch K _{NN, 2,} and the multi-bit The comparison quantizer performs a comparison and quantization to obtain a one-bit binary code. If the value is 1, then K _{NN, 2} is disconnected, K _{NN, 3} is closed, and the lower plates of 2 ^NN capacitors pass through switches K _{NN, 3} and The output terminal of the voltage driver B2 is connected, if the value is 0, K _NN,2 remains closed, K _NN,3 is disconnected, and the lower plates of the 2 ^NN capacitors are connected to the output terminal of the voltage driver B1 through the switch K _NN,2 , So far, the Nth comparison and quantification have been completed.

The multi-bit binary code output by the multi-bit successive comparison quantizer after quantization is converted into a temperature code through a digital circuit based on the data weight averaging algorithm;

The output temperature code control is based on the feedback digital-analog converter of the capacitor structure to obtain the output signal of the digital-analog converter; the output signal of the digital-analog converter is input to the first adder unit to make a difference with the input signal, and the signal after making the difference is input to Input to the first-order integrator.

In the present invention, the input analog signal V _in , the output signal V _in1 of the first-order integrator, and the output signal V _in2 of the second-order integrator are respectively carried out by the capacitors in the second adder unit composed of a multi-input capacitor array at the sampling time. For sampling on the lower plate, FIG. 3 is a schematic diagram of the sampling time of a structure of the second adder unit. At the time of sampling, the second adder unit is different from the traditional sequential quantizer, and the sampling array capacitance only samples a single input signal. At the moment of comparison, the capacitor array of the second adder unit is restored to the sequential comparison quantizer-like binary weight sampling capacitor array of the prior art. FIG. 4 is a circuit diagram of a structure of the second adder unit at the moment of the first comparison. Using the law of conservation of charge, we can get:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}}<span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ref</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ref</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ref</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Among them, V _ref3 is the input common-mode signal, and V _ref2 and V _ref1 are the reference voltages of the comparators. It can be seen from formula (1) that the multi-input capacitor array of the present invention realizes the amplification of the output signal V _in1 of the first-order integrator by 2 times in one cycle of sampling and comparison, and realizes the amplification of the input analog signal V _in by 2 The addition function of the output signal V _in1 of the first-order integrator and the output signal V _in2 of the second-order integrator is doubled, and the addition of 2V _in1 +V _in2 +V _in is reduced by 4 times. The constant coefficient of the second item on the right side in formula (1) It is due to the attenuation coefficient introduced by the system structure, which can be compensated by increasing the input signal V _in or reducing the reference voltage _VR of the quantizer.

In the Sigma-Delta modulator of the present invention, an integrating circuit based on a switched capacitor structure in the prior art is used to implement a two-order integrator for accumulating the difference between the input signal and the output of the feedback digital-to-analog converter.

The multi-bit successive comparison quantizer in the Sigma-Delta modulator of the present invention adopts the prior art successive comparison quantizer, and a high-efficiency comparator is used in the successive comparison quantizer to reduce power consumption.

The digital logic for converting binary codes into temperature codes in the Sigma-Delta modulator of the present invention is designed and implemented based on the data weight averaging algorithm in the prior art, and is used to reduce nonlinear errors generated by multi-bit digital-to-analog conversion.

The feedback digital-to-analog converter in the Sigma-Delta modulator of the present invention is designed and realized based on the unit capacitance element in the prior art.

In the Sigma-Delta modulator of the present invention, the first adder unit for calculating the difference between the input signal and the output signal of the capacitive digital-to-analog converter is realized by the sampling capacitor in the first-order integrator.

Compared with the prior art, the present invention has the following advantages and beneficial effects:

In the Sigma-Delta modulator described in the present invention, the addition function is realized by the multi-input sampling capacitor array before the quantizer, which removes an additional analog or digital adder circuit, reduces the power consumption of the entire circuit, and saves the circuit area , reducing production costs.

Description of drawings

Fig. 1 is a structural block diagram of a traditional second-order feedforward Sigma-Delta modulator;

Fig. 2 is the structural block diagram of second-order feedforward Sigma-Delta modulator of the present invention;

Fig. 3 is a schematic diagram of sampling moments of a structure capacitor array of the second adder unit;

Fig. 4 is a schematic diagram of the first comparison moment of a structure capacitance array of the second adder unit;

Fig. 5 is the Sigma-Delta modulator circuit structural diagram that the embodiment of the present invention provides;

FIG. 6 is a circuit timing diagram of a Sigma-Delta modulator provided by an embodiment of the present invention;

FIG. 7 is a structural block diagram of a chopper-stabilized amplifier provided by an embodiment of the present invention;

FIG. 8 is a circuit structure diagram of a large-range telescopic operational amplifier provided by an embodiment of the present invention;

FIG. 9 is a structural diagram of a low-power comparison circuit provided by an embodiment of the present invention;

FIG. 10A is an asynchronous clock control circuit provided by an embodiment of the present invention;

FIG. 10B is a timing block diagram of an asynchronous clock provided by an embodiment of the present invention;

FIG. 11 is a schematic diagram of a data weight averaging algorithm provided by an embodiment of the present invention;

Among them, 1 indicates two integrators based on switched capacitor structure, 2 indicates successive comparison quantizer, 3 indicates a digital circuit that converts binary code into temperature code based on data weight averaging algorithm, 4 indicates feedback digital-to-analog converter, and 5 indicates the first Adder unit, 6 represents the second adder unit, 50 represents a chopper-stabilized operational amplifier, 51 represents a 4-bit asynchronous successive comparison quantizer, 52 represents a 4-bit binary code into a 15-bit temperature code digital logic module, 53 represents a 4-bit Feedback digital-to-analog converter, 70 represents a pMOS switch, 71 represents a bootstrap switch, and 101 represents an asynchronous clock unit.

Detailed ways

The embodiment of the present invention proposes a feed-forward second-order low-pass Sigma-Delta modulator based on a 4-bit asynchronous successive comparison quantizer using a multi-input sampling switched capacitor array adder. FIG. 5 is a schematic diagram of a single-ended circuit structure. Modulator realized by this differential structure. The circuit includes two integrated circuits based on the switched capacitor structure of the prior art, wherein the operational amplifier in the first-order integrator adopts the chopper-stabilized operational amplifier 50 structure to realize; the second adder unit 6, one based on the prior art 4-bit asynchronous successive comparison quantizer 51, a 4-bit binary code is converted into 15-bit temperature code digital logic module 52 based on the prior art, a 4-bit feedback digital-to-analog converter 53 based on the unit capacitance structure of the prior art . Its timing is shown in Figure 6. The feed-forward structure can reduce the system's requirements on the nonlinearity of the operational amplifier in the integrator and reduce the difficulty of analog circuit design. The multi-bit quantizer can improve the signal-to-noise-distortion ratio of the system without increasing the system oversampling rate and the order of the integrator.

In a low-pass sigma-delta modulator, the analog circuit that contributes the most low-frequency noise is the op amp located in the first-order integrator. In order to suppress low-frequency noise, the operational amplifier in the first-order integrator uses a prior art chopper stabilization amplifier, as shown in Figure 7. The input switch of the amplifier adopts pMOS switch 70; the output switch adopts prior art bootstrap switch 71, and its function ensures the linearity of the transmission signal. The switch control clock adopts a two-phase non-overlapping clock design in the prior art, and the timing sequence is shown in FIG. 6 .

Adopt the second adder unit in the present invention, the output value of adder is inevitably accompanied by system attenuation, and its coefficient is This system attenuation can be counteracted by increasing the input signal or decreasing the quantizer reference voltage. In this embodiment, the system attenuation is counteracted by a method of increasing the input signal by 1 while reducing the reference voltage of the quantizer by 1. The increase in the input signal causes the operational amplifier in the integrator to handle a signal with a greater dynamic range. In this embodiment, an operational amplifier with a large-scale telescopic structure in the prior art is adopted, as shown in FIG. 8 . The large-range dynamic performance of the input and output of the op amp is realized by making the tail current source transistor of the sleeve structure work in the linear region. The circuit is designed under SMIC's 65nm process, and the power supply voltage is 1V. Through circuit simulation, it can be seen that under the condition of a load capacitance of 10pF, the gain of the operational amplifier reaches 54dB, and the gain-bandwidth product reaches 14MHz.

In this embodiment, the multi-bit successive comparison quantizer adopts the prior art 4-bit asynchronous successive comparison quantizer. Traditional multi-bit quantizers usually use Flash-structured analog-to-digital converters. This kind of circuit structure has a large area and high power consumption, and is not suitable for low power consumption applications. The above-mentioned problem can be solved by adopting a successive comparison quantizer, and the quantizer of this structure only includes one comparator, which can eliminate the problem of comparator offset voltage mismatch caused by multiple comparators. The comparator in the quantizer of this embodiment adopts the low-power comparator of the prior art, as shown in Figure 9, this structure has no DC bias circuit, can reach ultra-low static power consumption, and the average power consumption is only related to the sampling frequency relevant.

The asynchronous clock control circuit is used to generate the comparison clock CLK of the comparator in the quantizer and the integration clock Φ _F of the first-order integration period, as shown in FIG. 10A . The asynchronous clock unit 101 is implemented using the existing technology. The circuit using this technology was first published in "A 30fJ/Conversion-Step8b 0-to10MS/s Asynchronous SAR ADC in 90nm CMOS" 2010 IEEEISSCC Dig.Tech.Papers, pp388-389, this The asynchronous timing control in the example is shown in Figure 10B.

In this embodiment, the second adder unit adopts the second adder unit of the first structure. At the moment of signal sampling, the switches K _3,1 , K _2,1 , K _1,1 , K _0,1 , K _L,1 , K in the second adder unit are closed, and the other switches are opened. The output signal of the first-order integrator is input to the lower plate of 2 ³ capacitors through the switch K _3,1 ; the output signal of the second-order integrator is input to the lower plate of 2 ² capacitors through the switch K _2,1 ; the input signal Input to 2 ¹ , 2 and last capacitors via switches K _1,1 , K _,1 , K _L,1 . The upper plates of all capacitors are connected to the output terminal of the voltage driver B3 through the switch K. As shown in Figure 11.

After sampling, the 4-bit successive comparison quantizer performs four successive comparisons and quantization on the sampled signal. During comparison and quantization, switches K _3,1 , K _2,1 , K _1,1 , K _,1 , K _L,1 , K are open, K _L,2 is closed, and the lower plate of the last capacitor is connected to the voltage driver The output terminals of B2 are connected, and the upper plates of all capacitors are connected with the input of the comparative quantizer. When performing the first comparison and quantification, the switch K _3,2 is first closed, K _3,3 is open, the switches K _2,2 , K _1,2 , K _,2 are open, and the switches K _2,3 , K _{1 ,3} and K _0,3 are closed. The lower plates of 2 ³ capacitors are connected to the output terminal of the voltage driver B1 through switches K _3,2 , the lower plates of 2 ² , 2 ¹ , and 2 ⁰ capacitors are connected through switches K _2,3 , K _1,3 , K _,3 is connected to the output terminal of the voltage driver B2, as shown in FIG. 12 . The 4-bit sequential comparison quantizer performs a comparison and quantization to obtain a one-bit binary code. If the value is 1, then K _{3, 2} is disconnected, K _{3, 3} is closed, and the lower plates of the 2 ³ capacitors pass through the switch K _{3 ,3} is connected to the output terminal of the voltage driver B2, if the value is 0, then K _3,2 remains closed, K _3,3 is disconnected, and the lower plate of the 2 ³ capacitors is output through the switch K _3,2 and the voltage driver B1 The terminals are connected, and the first comparison and quantification have been completed. After the first comparison and quantification is completed, the second comparison and quantification starts. The state of the switches K _3,2 and K _3,3 during the second comparison and quantization is consistent with the state at the end of the first comparison and quantization. When performing the second comparison and quantization, the switch K _2,2 is first closed, K _2,3 is open, the switches K _1,2 and K _,2 are open, and the switches K _1,3 and K _,3 are closed. The lower plates of 2 ² capacitors are connected to the output terminal of voltage driver B1 through switches K _2,2 , and the lower plates of 2 ¹ and 2 ⁰ capacitors are output with voltage driver B2 through switches K _1,3 and K _0,3 end connected. The 4-bit sequential comparison quantizer performs a comparison and quantization to obtain a one-bit binary code. If the value is 1, then K _{2, 2} is disconnected, K _{2, 3} is closed, and the lower plates of the ² capacitors pass through the switch K _{2 ,3} is connected to the output terminal of the voltage driver B2, if the value is 0, then K _2,2 remains closed, K _2,3 is disconnected, and the lower plate of ^{the 2} capacitors is output through the switch K _2,2 and the voltage driver B1 The terminals are connected, and the second comparison and quantification have been completed. After the second comparison and quantification is completed, the third comparison and quantification starts. During the third comparison and quantization, the states of switches K _3,2 and K _3,3 are consistent with those at the end of the first comparison and quantization, and the states of switches K _2,2 and K _2,3 are the same as those of the second comparison and quantization The state remains the same at the end. When performing the third comparison and quantization, the switch K _1,2 is closed first, the switch K _1,3 is open, the switch K ₂ is open, and the switch K ₃ is closed. 2. The lower plate of ^one capacitor is connected to the output terminal of the voltage driver B1 through the switch K _1,2 , and the lower plates of the two capacitors are connected to the output terminal of the voltage driver B2 through the switch K _0,3 . The 4-bit sequential comparison quantizer performs a comparison and quantization to obtain a one-bit binary code. If the value is 1, then K _{1, 2} is disconnected, K _{1, 3} is closed, and the lower plates of ²¹ capacitors pass through the switch K _{1 ,3} is connected to the output terminal of the voltage driver B2, if the value is 0, then K _1,2 will remain closed, K _1,3 will be disconnected, and the lower plate of ²¹ capacitors will output through the switch K _1,2 and the voltage driver B1 The terminals are connected, and the third comparison and quantification have been completed. During the fourth comparison and quantization, the states of switches K _3,2 and K _3,3 are consistent with those at the end of the first comparison and quantization, and the states of switches K _2,2 and K _2,3 are the same as those of the second comparison and quantization The states at the end are consistent, and the states of the switches K _1,2 and K _1,3 are consistent with those at the end of the third comparison and quantization. When performing the fourth comparison and quantization, the switch K _,2 is first closed, _K0,3 is disconnected, the lower plates of the ²⁰ capacitors are connected to the output terminal of the voltage driver B1 through the switch K _,2, and the 4 bits are compared and quantized successively Make a comparison and quantization to obtain a one-bit binary code. If the value is 1, K _0,2 will be disconnected, K _,3 will be closed, and the lower plates of the two capacitors will be connected to the output terminal of the voltage driver B2 through switches K _,3 If the value is 0, then K _{, 2} remains closed, K _{0, 3} is disconnected, and the lower plates of ²⁰ capacitors are connected to the output terminal of the voltage driver B1 through the switch K _{, 2} , thus completing the fourth Compare and quantify. Among them, V _ref3 is the input common-mode signal, and V _ref2 and V _ref1 are the reference voltages of the comparators. In this embodiment, V _ref3 =0.6V, V _ref2 =0.35V, and V _ref1 =0V.

When the 4-bit binary code is converted into a 15-bit temperature code logic digital circuit, it is designed and implemented based on the prior art data weight average algorithm. When the binary code is converted into a temperature code, it is also accompanied by the result of the last output temperature code. The code is shifted, and the schematic diagram of the algorithm is shown in Figure 13.

The 4-bit feedback digital-to-analog converter 53 is designed and implemented based on the prior art cell capacitor structure. The output temperature code is sent to the digital-to-analog converter to control the switches on the 15 circuit branches. For example, when the input control signal of the first capacitor branch is high level, that is, the temperature code signal corresponding to this road is 1, the control switch logic of this road is high when the clock Φ _F1 is high, Φ _P1 is high, and Φ _P1 The switch controlled by Φ _N1 is low, the switch controlled by Φ _N1 is turned off, and the lower plate _{of capacitor C F1} is connected to V _refp ; when the input control signal of the first capacitor branch is low, that is, the corresponding The temperature code signal is 0, the control switch logic of this circuit is high when the clock Φ _F1 is high, Φ _N1 is high, the switch controlled by Φ _N1 is closed, Φ _P1 is low, the switch controlled by Φ _P1 is opened, and the capacitor C _F1 The lower board is connected to V _refn ; where V _refp is a high feedback reference voltage, and V _refn is a low feedback reference voltage, that is, V _refp >V _refn . In this embodiment, V _refp =0.7V, V _refn =0V.

The adder used to calculate the difference between the input signal and the output signal of the capacitive digital-to-analog converter is implemented through the sampling capacitor _S1 in the first-order integrator.

This embodiment is designed under SMIC's 65nm CMOS process. Through circuit simulation, it can be seen that when the input signal is a 5kHz sinusoidal signal, its peak-to-peak value is 600mV, and the sampling frequency is 1MHz. The harmonic ratio can reach 94 decibels, and the overall power consumption of the circuit is 340uW.

The above is only a preferred embodiment of the present invention, and is not used to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present invention shall include Within the protection scope of the present invention.

Claims (1)

1. A kind of Sigma-Delta modulator, it is characterized in that: it comprises two integrators based on switched capacitor circuit, a multibit compares quantizer successively, one is converted into temperature code function by binary code based on data weight average algorithm A digital circuit, a feedback digital-to-analog converter based on a unit capacitor structure; a first adder unit; a second adder unit; The first structure of the second adder unit: the second adder unit includes 2 ^N unit capacitors, and the value range of N is 2 to 8; the upper plates of all capacitors are connected to one end of a switch K, and the other end of the switch It is connected to the output terminal of a voltage driver B3; the lower plate of 2 ^N-1 capacitors is output from the first-order integrator through three switches K _N-1,1 , K _N-1,2 , K _N-1,3 terminal, the output terminal of the voltage driver B1, and the output terminal of the voltage driver B2 are connected; the lower plates of the 2 ^N-2 capacitors respectively pass three switches K _N-2,1 , K _N-2,2 , K _N-2,3 Connected to the output terminal of the second-order integrator, the output terminal of the voltage driver B1, and the output terminal of the voltage driver B2; 2 ^N-3 , 2 ^N-4 , 2 ^N-(N-1) , 2 ^NN The lower plate of the capacitor passes through the corresponding K _N-3,1 , K _N-3,2 , K _N-3,3 , K _N-4,1 , K _N-4,2 , K _{N-4, 3} ,..., K _{N-(N-1), 1} , K _{N-(N-1), 2} , K _{N-(N-1), 3} , K _{NN, 1} , K _{NN, 2} , K _{NN, 3} are connected to the signal input terminal, the output terminal of the voltage driver B1, and the output terminal of the voltage driver B2; the lower plate of the last capacitor is connected to the signal input terminal and the output terminal of the voltage driver B2 through two switches K _{L, 1} , K _L, 2 connected; The second structure of the second adder unit: the second adder unit includes 2 ^N unit capacitors, and the value range of N is 2 to 8; the upper plates of all capacitors are connected with one end of a switch K, and the other end of the switch It is connected to the output terminal of a voltage driver B3; the lower plate of 2 ^N-1 capacitors is output from the first-order integrator through three switches K _N-1,1 , K _N-1,2 , K _N-1,3 terminal, the output terminal of the voltage driver B1, and the output terminal of the voltage driver B2 are connected; the lower plates of the 2 ^N-2 capacitors respectively pass three switches K _N-2,1 , K _N-2,2 , K _N-2,3 Connected to the signal input terminal, the output terminal of the voltage driver B1, and the output terminal of the voltage driver B2; 2 ^N-3 , 2 ^N-4 , ... 2 ^N-(N-1) , the lower poles of 2 ^NN capacitors The plate passes the corresponding K _N-3,1 , K _N-3,2 , K _N-3,3 , K _N-4,1 , K _N-4,2 , K _N-4,3 ,·· , K _{N-(N-1), 1} , K _{N-(N-1), 2} , K _{N-(N-1), 3} , K _{NN, 1} , K _{NN, 2} , K _{NN, 3} and The output terminal of the second-order integrator, the output terminal of the voltage driver B1, and the output terminal of the voltage driver B2 are connected; the lower plate of the last capacitor is connected to the output terminal of the second-order integrator through two switches K _{L, 1} , K _{L, 2} , and the voltage The output terminal of the driver B2 is connected; The modulator input terminal is respectively connected with the first adder unit and the second adder unit; The output end of the first adder unit is connected to the input end of the first-order integrator; The output terminal of the first-order integrator is respectively connected with the second adder unit and the input terminal of the second-order integrator; The output end of the second-order integrator is connected to the second adder unit; The output end of the second adder unit is connected to the multi-bit successive comparison quantizer, and the multi-bit successive comparison quantizer is connected to the second adder unit through the feedback signal line; The output terminal of the multi-bit successive comparison quantizer is connected with a digital circuit based on a data weight averaging algorithm; The output terminal of the digital circuit based on the data weight average algorithm is connected with the feedback digital-to-analog converter based on the unit capacitance structure; The output terminal of the feedback digital-to-analog converter is connected with the first adder unit.