CN113014254B - Phase-locked loop circuit - Google Patents
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- CN113014254B CN113014254B CN202110262042.2A CN202110262042A CN113014254B CN 113014254 B CN113014254 B CN 113014254B CN 202110262042 A CN202110262042 A CN 202110262042A CN 113014254 B CN113014254 B CN 113014254B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The application relates to a phase-locked loop circuit, wherein the phase-locked loop circuit comprises: a voltage controlled oscillator for generating a high frequency clock signal; the frequency divider is used for dividing the frequency of the high-frequency clock signal to obtain a low-frequency signal; the phase frequency discriminator is used for comparing the low-frequency signal with the reference signal in the time domain before or after the time domain to obtain a time domain fast and slow signal; the charge pump circuit is used for converting the time domain speed signal into a current amplitude signal; a loop filter for converting the current amplitude signal into a voltage signal to feedback control the voltage controlled oscillator; and the automatic frequency calibration circuit is connected with the voltage-controlled oscillator and used for determining a capacitor array control word of the voltage-controlled oscillator, wherein the capacitor array control word is used for adjusting the frequency of a high-frequency clock signal generated by the voltage-controlled oscillator. The application solves the problem of slow locking speed of the PLL in the related technology, and realizes the rapid frequency switching of the on-chip high-precision low-noise high-frequency clock signal generated by the PLL.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a phase locked loop circuit.
Background
The common crystal oscillator cannot achieve very high frequency due to the reasons of process and cost, and when the high frequency application is needed, the Voltage Controlled Oscillator (VCO) converts the high frequency, but the clock signal generated by the method is unstable, so that the phase-locked loop is used for realizing stable and high-frequency clock signal, and no residual frequency difference exists during locking. Phase Locked Loop (PLL) based frequency synthesizers are important circuit components in various applications, particularly in communication systems. The lock-in speed is also an important design requirement to remove good signal purity (i.e., low phase noise and low spurious). The fast lock function is particularly important for systems requiring frequency hopping operation, and the frequency hopping stability speed greatly limits the speed of system mode switching.
In order to realize the fast switching of the two operating frequencies, the PLL module needs to realize a fast frequency-cutting function. The cut-in time is the sum of an Automatic Frequency Calibration (AFC) and a fine lock time. The typical PLL lock time is around tens of microseconds, far exceeding the 2 microsecond cut time requirement here. It is therefore desirable to design PLL fast lock technology. The related art PLL focuses more on the performance of wide coverage, low power consumption, low jitter, etc., and the research on the PLL fast locking technology, especially for wide frequency hopping distances, is insufficient in fast locking. In the existing researches, few designs can achieve both high precision and extremely high locking speed.
At present, no effective solution has been proposed for the problem of slow PLL locking speed in the related art.
Disclosure of Invention
The embodiment of the application provides a phase-locked loop circuit, which at least solves the problem of low locking speed of a PLL in the related art.
In a first aspect, an embodiment of the present application provides a phase-locked loop circuit, including:
a voltage controlled oscillator for generating a high frequency clock signal;
the frequency divider is connected with the voltage-controlled oscillator and used for dividing the frequency of the high-frequency clock signal to obtain a low-frequency signal;
the phase frequency detector is connected with the frequency divider and is used for comparing the low-frequency signal with the reference signal in the time domain before or after the low-frequency signal is compared with the reference signal to obtain a time domain fast and slow signal;
the charge pump circuit is connected with the phase frequency detector and used for converting the time domain speed signal into a current amplitude signal;
a loop filter connected to the charge pump circuit for converting the current amplitude signal into a voltage signal for feedback control of the voltage controlled oscillator;
and the automatic frequency calibration circuit is connected with the voltage-controlled oscillator and used for determining a capacitor array control word of the voltage-controlled oscillator, wherein the capacitor array control word is used for adjusting the frequency of the high-frequency clock signal generated by the voltage-controlled oscillator.
In some of these embodiments, the automatic frequency calibration circuit comprises:
a main state machine and a process state sub-state machine;
the main state machine uses a reference clock, the first period enters an initial state, and when a start signal is detected, the main state machine enters a cyclic process of a counting state and a processing state.
In some of these embodiments, in the count state, rising edges of the high frequency clock signal output by the voltage controlled oscillator are counted.
In some embodiments, in the processing state, the count value in the count state is differenced from the frequency division ratio of the frequency divider to obtain an error value, and the capacitor array control word of the voltage-controlled oscillator is adjusted according to the error value.
In some of these embodiments, adjusting the capacitive array control word of the voltage controlled oscillator according to the error value includes:
judging whether the capacitor array control word selects a left subtree or a right subtree according to the polarity of the error value;
and judging whether the control word of the capacitor array control word selection subtree or the control word of the father node according to the magnitude of the error value.
In some of these embodiments, the phase-locked loop circuit further comprises:
and the phase error compensation module is used for compensating the phase difference between the reference signal and the clock signal output by the frequency divider.
In some of these embodiments, the phase error compensation module is configured to:
after the automatic frequency calibration circuit determines a capacitor array control word of the voltage-controlled oscillator, performing first phase error compensation on the reference signal and a clock signal output by the frequency divider by changing a frequency division ratio of the frequency divider;
and when the frequency of the reference signal is the same as that of the clock signal output by the frequency divider, performing second phase error compensation on the reference signal and the clock signal output by the frequency divider by changing the frequency division ratio of the frequency divider, so that the frequency and the phase of the reference signal and the clock signal output by the frequency divider are synchronous.
In some of these embodiments, the phase-locked loop circuit further comprises:
and the other charge pump circuit is connected with the loop filter and is used for synchronously charging and discharging one capacitor in the loop filter.
In some of these embodiments, the switching of the loop bandwidth of the phase-locked loop circuit is accomplished by current control word switching of the charge pump circuit and capacitive resistance control word switching of the loop filter.
In some of these embodiments, the phase-locked loop circuit further comprises:
and the locking detection circuit is respectively connected with the frequency divider and the phase frequency detector and is used for judging the locking condition through digital signals obtained by mutual acquisition of the triggers.
Compared with the related art, the phase-locked loop circuit provided by the embodiment of the application generates a high-frequency clock signal through the voltage-controlled oscillator; the frequency divider divides the frequency of the high-frequency clock signal to obtain a low-frequency signal; the phase frequency discriminator compares the low-frequency signal with the reference signal in the time domain before or after the time domain, and obtains a time domain fast and slow signal; the charge pump circuit converts the time domain speed signal into a current amplitude signal; a loop filter converts the current amplitude signal into a voltage signal to feedback control the voltage controlled oscillator; an automatic frequency calibration circuit determines a capacitor array control word of the voltage controlled oscillator; the phase error compensation module compensates the phase difference between the low-frequency signal and the reference signal at the key node twice, solves the problem of low locking speed of the PLL in the related art, and realizes the rapid frequency switching of the on-chip high-precision low-noise high-frequency clock signal generated by the PLL.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the other features, objects, and advantages of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
fig. 1 is a schematic diagram of a phase locked loop circuit according to an embodiment of the application;
FIG. 2a is a schematic diagram of a fast lock automatic frequency calibration circuit and a phase error compensation state machine according to a preferred embodiment of the present application;
fig. 2b is a schematic diagram of a 4-way quadrature-phase divided-by-4 VCO clock in accordance with a preferred embodiment of the present application;
FIG. 2c is a schematic diagram of a process flow for a process state in accordance with a preferred embodiment of the present application;
FIG. 3 is a schematic diagram of phase error compensation according to a preferred embodiment of the present application;
fig. 4 is a schematic diagram of a loop bandwidth switching technique in accordance with a preferred embodiment of the present application.
Detailed Description
The present application will be described and illustrated with reference to the accompanying drawings and examples in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. All other embodiments, which can be made by a person of ordinary skill in the art based on the embodiments provided by the present application without making any inventive effort, are intended to fall within the scope of the present application.
It is apparent that the drawings in the following description are only some examples or embodiments of the present application, and it is possible for those of ordinary skill in the art to apply the present application to other similar situations according to these drawings without inventive effort. Moreover, it should be appreciated that while such a development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as having the benefit of this disclosure.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by those of ordinary skill in the art that the described embodiments of the application can be combined with other embodiments without conflict.
Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," and similar referents in the context of the application are not to be construed as limiting the quantity, but rather as singular or plural. The terms "comprising," "including," "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to only those steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in connection with the present application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The terms "first," "second," "third," and the like, as used herein, are merely distinguishing between similar objects and not representing a particular ordering of objects.
Before the embodiments of the present application are described in detail, technical terms and abbreviations in the embodiments of the present application are described as follows:
PLL (Phase Locked Loop): phase locked loop
VCO (Voltage Controlled Oscillator): voltage controlled oscillator
AFC (Auto Frequency Calibration): automatic frequency calibration
PEC (Phase Error Compensation): phase error compensation
PFD (Phase-Frequency Detector): phase frequency detector
CP (Charge Pump): charge pump
LF (Loop Filter): loop filter
PDIV (Programmable Divider): programmable frequency divider
The embodiment of the application provides a phase-locked loop circuit.
Fig. 1 is a schematic diagram of a phase-locked loop circuit according to an embodiment of the present application, as shown in fig. 1, the phase-locked loop circuit includes:
a voltage controlled oscillator for generating a high frequency clock signal;
the frequency divider is connected with the voltage-controlled oscillator and used for dividing the frequency of the high-frequency clock signal to obtain a low-frequency signal;
the phase frequency detector is connected with the frequency divider and is used for comparing the low-frequency signal with the reference signal in the time domain before or after the low-frequency signal is compared with the reference signal to obtain a time domain fast and slow signal;
the charge pump circuit is connected with the phase frequency detector and used for converting the time domain speed signal into a current amplitude signal;
a loop filter connected to the charge pump circuit for converting the current amplitude signal into a voltage signal for feedback control of the voltage controlled oscillator;
and the automatic frequency calibration circuit is connected with the voltage-controlled oscillator and used for determining a capacitor array control word of the voltage-controlled oscillator, wherein the capacitor array control word is used for adjusting the frequency of the high-frequency clock signal generated by the voltage-controlled oscillator.
The PLL quick locking technology in the embodiment of the application mainly comprises two aspects: the fast AFC and PEC functions are integrated in the AFC module, implemented in cooperation with the PFD and CP. The block diagram of the designed PLL is shown in fig. 1. The PLL clock generator is a typical negative feedback system with a high feedforward gain and a high precision and high linearity digital feedback path. After the high-frequency clock signal of the voltage-controlled oscillator (VCO) is digitally divided to a low frequency by the Programmable Divider (PDIV), the high-frequency clock signal is advanced or lagged with the reference clock signal in the time domain by the Phase Frequency Detector (PFD), then the time domain speed signal is converted into a current amplitude signal by the charge pump Circuit (CP), and the current signal is averaged into a voltage signal by the Loop Filter (LF), so that the voltage-controlled oscillator is feedback controlled. Furthermore, in a serial communication link, the clock generator is very far from the transmitter and receiver on-chip, and the driver is also an essential module of the clock circuit.
The VCO used in the embodiments of the present application is an LC-VCO structure. To achieve coverage over a wide frequency band of 6.4GHz to 10GHz, the VCO capacitance needs to be designed as a 7bit array. The larger the control word value of the control array, the smaller the capacitance value, and the higher the output clock frequency of the VCO. The purpose of the AFC is to automatically generate an optimal VCO capacitance array control word according to the current system operating environment.
In some of these embodiments, the automatic frequency calibration circuit comprises:
a main state machine and a process state sub-state machine;
the main state machine uses a reference clock, the first period enters an initial state, and when a start signal is detected, the main state machine enters a cyclic process of a counting state and a processing state.
In some of these embodiments, in the count state, rising edges of the high frequency clock signal output by the voltage controlled oscillator are counted.
In some embodiments, in the processing state, the count value in the count state is differenced from the frequency division ratio of the frequency divider to obtain an error value, and the capacitor array control word of the voltage-controlled oscillator is adjusted according to the error value.
In some of these embodiments, adjusting the capacitive array control word of the voltage controlled oscillator according to the error value includes:
judging whether the capacitor array control word selects a left subtree or a right subtree according to the polarity of the error value;
and judging whether the control word of the capacitor array control word selection subtree or the control word of the father node according to the magnitude of the error value.
The fast AFC consists of a main state machine and a process state sub-state machine as shown in fig. 2 a. First, the AFC is operated, the VCO control voltage is forced to pull up to 400mV, which is a stable environment for the AFC process, and 400mV is a relatively ideal locking voltage, thus improving the accuracy of the final control word code. The AFC master state machine uses a reference clock, the first period entering the initial state IDLE. When the start signal afc _start is detected as high, a count-processing loop may be entered. The AFC _start signal is asserted here by the enable signal and can only be asserted once in case the AFC function is restarted out of control. One cycle of AFC includes a count phase and a processing phase.
The next state is the COUNT state afc_count, in which the VCO output clock rising edge is counted. Since the highest frequency here is 10GHz, there will be a high requirement for the circuitry. Thus a 4-way quadrature phase divided by 4 VCO clock is selected as the sampled signal, as shown in fig. 2 b. In such a period, four clocks are sampled by the reference clock, and the number of rising edges added together is the number of rising edges of the VCO output clock in a reference frequency, and in the case of correct frequency, the number is equal to a preset frequency division ratio.
The COUNT state is to cooperate with the processing state, and the next state of afc_count is the processing state afc_process. During this period, the last state count will be processed. The specific operation is that as shown in fig. 2c, the count value of the current period is differenced with the frequency division ratio to obtain an error value, and then the error value is larger and smaller than the error value obtained last time. At the same time, the polarity of the error value is also recorded. The polarity determines whether the next control word should select the left or right subtree. If the error value is positive, it indicates that the VCO output clock frequency is too high, the current control word is too large, the left sub-tree is selected for the next cycle, and the right sub-tree is selected otherwise. In the PROCESS state, the control word selection of the subtree and the parent node is determined by the magnitude of the error value under both control words. If the subtree error value is small, the subtree control word value is left, otherwise, the control word of the father node is returned finally. The AFC will look down from the middle control word until the odd control word appears, and finally return the control word with the lowest error value recorded, i.e. the optimal control word. This is the AFC technique that looks for the optimal control word in the dichotomy. The 7-bit AFC output control word requires 7 count-processing steps to complete AFC using dichotomy. So the total time is 2T (idle+start) +7 x 2T (count+process), for a total of 16 periods 832ns, which leaves enough time for the subsequent PLL fine lock.
In some of these embodiments, the phase-locked loop circuit further comprises:
and the phase error compensation module is used for compensating the phase difference between the reference signal and the clock signal output by the frequency divider.
In some of these embodiments, the phase error compensation module is configured to:
after the automatic frequency calibration circuit determines a capacitor array control word of the voltage-controlled oscillator, performing first phase error compensation on the reference signal and a clock signal output by the frequency divider by changing a frequency division ratio of the frequency divider;
and when the frequency of the reference signal is the same as that of the clock signal output by the frequency divider, performing second phase error compensation on the reference signal and the clock signal output by the frequency divider by changing the frequency division ratio of the frequency divider, so that the frequency and the phase of the reference signal and the clock signal output by the frequency divider are synchronous.
The phase error compensation section has a total of two phase compensations, as shown in fig. 3. First, at the end of AFC, there is a phase difference between the reference clock and the divider output clock. The PEC module detects the value of this phase difference and immediately changes the division ratio to compensate. However, at this time, the frequencies of the two clocks are not the same, so the phase difference is accumulated until the phase difference reaches the maximum value when the frequencies of the two clock signals are the same, that is, the second compensation point compensates the phase difference by changing the frequency division ratio, the two clock signals reach the frequency phase synchronization, and the locking is completed quickly under a certain margin. The detection of the phase difference is here achieved by slow clock sampling fast clock. The PEC starts counting the divide-by-4 VCO output clock rising edges when the PFD output UP signal rising edge comes. The count value multiplied by 4 is considered the current phase difference. Each cycle a phase error check is performed. If the phase error exceeds some threshold level, the appropriate compensating phase is provided accordingly to reduce the phase error. Phase compensation is accomplished by dynamically changing the division ratio such that the output edges of the divider are shifted accordingly to change the phase. This process is repeated until the frequency error (and thus the integrated phase error) falls sufficiently small to eventually reach a locked state.
In some of these embodiments, the phase-locked loop circuit further comprises:
and the other charge pump circuit is connected with the loop filter and is used for synchronously charging and discharging one capacitor in the loop filter.
As shown in fig. 1, the capacitance of C2 in LF is typically relatively large, several hundred picofarads, much larger than the values of C1 and C3, and the time constant is large, which results in a long charging process of C2, and longer AFC time. That is, when the AFC is finished, the VCO control voltage is disconnected from 400mV control, and then a charge back flow occurs, C1 discharges C2 to charge, which directly results in a VCO control voltage dip and a fast lock function loss. To avoid this, a proprietary CP is required to charge and discharge C2 synchronously. The current value is calculated by the capacitance value proportional relation and the two CP current values.
In some of these embodiments, the switching of the loop bandwidth of the phase-locked loop circuit is accomplished by current control word switching of the charge pump circuit and capacitive resistance control word switching of the loop filter.
A simple analysis can result in a shorter lock time the larger the loop bandwidth of the PLL. But the noise performance cannot withstand excessive bandwidth when the PLL is operating properly. Therefore, the embodiment of the application provides a loop bandwidth switching technology, and as shown in fig. 4, the switching process is completed by switching the CP current control word and the LF capacitor resistor array control word. The CP and LF cooperate to switch loop bandwidth to ensure that the switched small-bandwidth PLL is still stable.
In some of these embodiments, the phase-locked loop circuit further comprises:
and the locking detection circuit is respectively connected with the frequency divider and the phase frequency detector and is used for judging the locking condition through digital signals obtained by mutual acquisition of the triggers.
Generally, the output phase of the programmable frequency divider after the loop is locked is aligned with the reference clock, and according to the characteristic that the phase difference is smaller when the analog signal is locked, the embodiment of the application adopts the locking detection circuit based on judging the analog phase difference value, and judges the locking condition through the digital signals obtained by mutually acquiring the trigger. From the whole signal link, the front-end frequency divider is used for eliminating poor duty ratio, the next delay module is used for eliminating the problem of delay mismatch caused by different bilateral distances on the layout, and the delay modules on the mutual acquisition paths can control the threshold value of phase difference detection and the threshold value digital controllability can be used for immunizing errors caused by the process. The exclusive or gate (Xnor) will determine the digital level of the output of the flip-flop, and will give a high level when it is high at the same time, and it should be noted that due to the introduction of divide-by-two, it may cause the rising edge at the time of reference to be aligned with the falling edge of the divided signal when it is inverted for the first time, and therefore will give a high level when it is low at the same time, so as to supply the following up/down counter operation, and when it is accumulated to a certain value, i.e. a situation of multiple phase approaches occurs, the lock detection circuit will give a high level to indicate that the system completes the lock operation at this time.
The embodiment of the application comprises the following key technologies:
(1) A fast AFC technique: under the condition of fixed VCO control voltage, the reference clock is used for counting the 4-frequency-division VCO output clock, the obtained frequency division ratio is compared with the preset frequency division ratio, a binary tree is searched through the polarity and the absolute value of the error value, and finally the optimal VCO capacitor array control word under the current working environment is output.
(2) A phase error compensation technique: after the frequency is changed, the phase error is rapidly accumulated, the PEC detects the phase difference, the phase difference is added or subtracted to the real-time frequency division ratio by judging the polarity of the phase difference, and the next period frequency division ratio is restored to the default value. Phase error compensation is accomplished end-to-end by this process instead of the conventional settling process of the PLL.
(3) Loop bandwidth switching techniques: the switching process is completed by CP current control word switching and LF capacitance resistance array control word switching. The CP and LF cooperate to switch loop bandwidth to ensure that the switched small-bandwidth PLL is still stable.
(4) LF charge backward flow treatment technology: and designing a special CP to synchronously charge and discharge C2, wherein the current value is calculated by a capacitance value proportional relation and the current of the two CPs.
The embodiment of the application can ensure that the PLL can reach a locking state within 2us when the PLL needs to perform wide-range frequency hopping operation.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (5)
1. A phase locked loop circuit comprising:
a voltage controlled oscillator for generating a high frequency clock signal;
the frequency divider is connected with the voltage-controlled oscillator and used for dividing the frequency of the high-frequency clock signal to obtain a low-frequency signal;
the phase frequency detector is connected with the frequency divider and is used for comparing the low-frequency signal with the reference signal in the time domain before or after the low-frequency signal is compared with the reference signal to obtain a time domain fast and slow signal;
the charge pump circuit is connected with the phase frequency detector and used for converting the time domain speed signal into a current amplitude signal;
a loop filter connected to the charge pump circuit for converting the current amplitude signal into a voltage signal for feedback control of the voltage controlled oscillator;
the automatic frequency calibration circuit is connected with the voltage-controlled oscillator and used for determining a capacitor array control word of the voltage-controlled oscillator, wherein the capacitor array control word is used for adjusting the frequency of the high-frequency clock signal generated by the voltage-controlled oscillator;
a phase error compensation module for compensating a phase difference between the reference signal and a clock signal output by the frequency divider;
wherein the automatic calibration circuit comprises:
a main state machine and a process state sub-state machine; the main state machine uses a reference clock, the first period enters an initial state, and when a start signal is detected, the main state machine enters a cyclic process of a counting state and a processing state;
counting rising edges of the high-frequency clock signal output by the voltage-controlled oscillator in the counting state;
in the processing state, the count value in the counting state is differenced with the frequency division ratio of the frequency divider to obtain an error value, and the capacitor array control word of the voltage-controlled oscillator is adjusted according to the error value;
wherein, the phase error compensation module is used for:
after the automatic frequency calibration circuit determines a capacitor array control word of the voltage-controlled oscillator, performing first phase error compensation on the reference signal and a clock signal output by the frequency divider by changing a frequency division ratio of the frequency divider;
and when the frequency of the reference signal is the same as that of the clock signal output by the frequency divider, performing second phase error compensation on the reference signal and the clock signal output by the frequency divider by changing the frequency division ratio of the frequency divider, so that the frequency and the phase of the reference signal and the clock signal output by the frequency divider are synchronous.
2. The phase-locked loop circuit of claim 1, wherein adjusting the capacitor array control word of the voltage controlled oscillator based on the error value comprises:
judging whether the capacitor array control word selects a left subtree or a right subtree according to the polarity of the error value;
and judging whether the control word of the capacitor array control word selection subtree or the control word of the father node according to the magnitude of the error value.
3. The phase-locked loop circuit according to any one of claims 1 to 2, characterized in that the phase-locked loop circuit further comprises:
and the other charge pump circuit is connected with the loop filter and is used for synchronously charging and discharging one capacitor in the loop filter.
4. Phase locked loop circuit according to any of claims 1 to 2, characterized in that the switching process of the loop bandwidth of the phase locked loop circuit is done by the current control word switching of the charge pump circuit and the capacitive resistance control word switching of the loop filter.
5. The phase-locked loop circuit according to any one of claims 1 to 2, characterized in that the phase-locked loop circuit further comprises:
and the locking detection circuit is respectively connected with the frequency divider and the phase frequency detector and is used for judging the locking condition through digital signals obtained by mutual acquisition of the triggers.
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| CN113644912B (en) * | 2021-07-27 | 2024-04-16 | 矽力杰半导体技术(杭州)有限公司 | Phase-locked loop circuit and control method thereof |
| CN114142854B (en) * | 2021-11-16 | 2024-06-11 | 北京大学 | Frequency compensation circuit, phase-locked loop compensation circuit, method, apparatus and storage medium |
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