CN116505938B - Phase locked loop - Google Patents
Phase locked loop Download PDFInfo
- Publication number
- CN116505938B CN116505938B CN202310714237.5A CN202310714237A CN116505938B CN 116505938 B CN116505938 B CN 116505938B CN 202310714237 A CN202310714237 A CN 202310714237A CN 116505938 B CN116505938 B CN 116505938B
- Authority
- CN
- China
- Prior art keywords
- flag bit
- signal
- output
- input signal
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 claims abstract description 22
- 230000008569 process Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000007246 mechanism Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 230000009022 nonlinear effect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention relates to the technical field of integrated circuits, and discloses a phase-locked loop which is used for solving the problem that the existing charge pump phase-locked loop can not be automatically adjusted along with the changes of process, temperature, voltage and PLL parameters, and comprises the following components: the phase frequency detector is configured to compare jump edges of the first input signal and the second input signal and obtain a first output signal or a second output signal according to frequency comparison of the first input signal and the second input signal; a counter and finite state machine module configured to count the first output signal and the second output signal, and adjust the values of the first control signal and the second control signal if the difference exceeds a threshold; and a charge pump configured to output a charge according to values of the first control signal and the second control signal. When the working environment of the circuit changes, the calibration circuit is opened once at intervals by setting on the system, so that the influence of temperature, power supply voltage and PLL parameter changes is eliminated.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a phase locked loop.
Background
In a wireless communication transmitter/receiver, a Phase Locked Loop (PLL) is an important module that clocks the transmission and reception of data, as shown in fig. 1, where a charge pump PLL is the preferred choice of the PLL architecture due to its wide acquisition range. The existing charge pump phase-locked loop cannot be automatically adjusted along with the process, temperature, voltage and PLL parameter changes, and the circuit cannot be guaranteed to work in an optimal state.
Disclosure of Invention
The invention aims to provide a phase-locked loop so as to solve the problem that the existing charge pump phase-locked loop cannot be automatically adjusted along with the change of process temperature and voltage and PLL parameters.
In order to solve the above technical problems, the present invention provides a phase locked loop, including:
the phase frequency detector is configured to compare jump edges of the first input signal and the second input signal and obtain a first output signal or a second output signal according to frequency comparison of the first input signal and the second input signal;
a counter and finite state machine module configured to count the first output signal and the second output signal, and adjust the values of the first control signal and the second control signal if the difference exceeds a threshold;
and a charge pump configured to output a charge according to values of the first control signal and the second control signal.
Optionally, in the phase-locked loop, if the frequency of the first input signal is greater than the frequency of the second input signal, the first output signal is at a high level, the second output signal is at a low level, and if the frequency of the first input signal is less than the frequency of the second input signal, the first output signal is at a low level, and the second output signal is at a high level.
Optionally, in the phase-locked loop, the first output signal is high level and the first status flag bit is added with 1, and the second output signal is high level and the second status flag bit is added with 1.
Optionally, in the phase-locked loop, if the difference between the first status flag bit and the second status flag bit is greater than 2 and the first status flag bit is greater than the second status flag bit, the first control signal is added with 1, and if the difference between the first status flag bit and the second status flag bit is greater than 2 and the first status flag bit is less than the second status flag bit, the second control signal is added with 1.
Optionally, in the phase-locked loop, the charge pump includes:
a first current source connected between the power source and the output terminal, configured to turn on the first switch by a first control signal to sink current to the output terminal;
a second current source connected between the output terminal and ground is configured to turn on the second switch by a second control signal to draw current to the output terminal.
Optionally, in the phase-locked loop, the phase frequency detector includes:
the first D trigger is configured to input a first input signal to the D end, input a second input signal through the delay device to the clk end, and take the Q output end as a first output signal through the buffer;
and the second D trigger is configured that a second input signal is input to the D end, a first input signal passing through the delay device is input to the clk end, and a second output signal is taken as the Q output end through the buffer.
Optionally, in the phase-locked loop, the method further includes:
a loop filter configured to connect an output of the charge pump;
a voltage controlled oscillator configured to be connected to an output terminal of the loop filter and output a target frequency; and
and the frequency divider is configured to divide the frequency after inputting the target frequency so as to provide a second input signal to the phase frequency detector.
Optionally, in the phase-locked loop, the reference spurious power of the phase-locked loop is:
，
where Kvco represents the gain of the voltage controlled oscillator,，finrepresenting the frequency of the first input signal, +.>Is the current of the charge pump, ">Is the impedance of the loop filter.
The invention also provides a control method of the phase-locked loop, which comprises the following steps:
initializing, wherein a counter is forbidden to count, and the first control signal and the second control signal are cleared;
judging whether the phase-locked loop is locked, if so, enabling the counter, and resetting the first state flag bit and the second state flag bit; otherwise, returning to the previous step after waiting for the first time;
the first status flag bit is incremented by 1 if the first input end connected to the first output signal receives a high level, and the second status flag bit is incremented by 1 if the second input end connected to the second output signal receives a high level;
after waiting for the second time, judging whether the absolute value difference value of the first state flag bit and the second state flag bit is larger than 2;
if yes, judging whether the first state flag bit is larger than the second state flag bit; otherwise, ending;
if the first state flag bit is greater than the second state flag bit, adding 1 to the first control signal, otherwise adding 1 to the second control signal;
after waiting for the third time, returning to the initialized step.
The inventor of the invention finds that the reference strays originate from circuit mismatch and nonlinear effects, and more strict requirements are imposed on the reference strays in many application occasions, and the reference strays can be reduced from the phase frequency detector and the charge pump. For example, as shown in fig. 2, a fixed compensation current is introduced at the output of the charge pump, thereby reducing the reference spurious of the output. As further shown in fig. 3, a fixed compensation delay is introduced in the reset path of the phase frequency detector to reduce the output reference spurs. Although the method shown in fig. 3 is more effective for reducing the reference spurs, its controllability is less than the method shown in fig. 2 and thus more jitter may be introduced.
Based on the insight, the invention provides a phase-locked loop, which is added with an automatic calibration function on the basis of the method shown in fig. 2, so as to adapt to more application occasions and requirements. Based on the structure of the original charge pump and the phase frequency detector, the invention introduces an automatic calibration mechanism to automatically calibrate the phase-locked loop after power-on, thereby achieving the purpose of reducing reference spurious.
Drawings
Fig. 1 is a schematic diagram of a conventional phase-locked loop.
Fig. 2 is a schematic diagram of a charge pump.
Fig. 3 is a schematic diagram of a phase frequency detector.
Fig. 4 is a schematic diagram of a pll according to an embodiment of the invention.
Fig. 5 is a schematic diagram of a control method of a pll according to an embodiment of the invention.
Fig. 6 shows the output reference spurs without an auto-calibration mechanism and with a calibration mechanism.
Detailed Description
The phase locked loop according to the invention is described in further detail below with reference to the drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention aims to provide a phase-locked loop so as to solve the problem that the existing charge pump phase-locked loop cannot be automatically adjusted along with the change of process temperature and voltage and PLL parameters.
To achieve the above object, the present invention provides a phase locked loop comprising: the phase frequency detector is configured to compare jump edges of the first input signal and the second input signal and obtain a first output signal or a second output signal according to frequency comparison of the first input signal and the second input signal; a counter and finite state machine module configured to count the first output signal and the second output signal, and adjust the values of the first control signal and the second control signal if the difference exceeds a threshold; and a charge pump configured to output a charge according to values of the first control signal and the second control signal.
Fig. 4-5 provide schematic diagrams of the structure of the phase-locked loop and the control method thereof according to the embodiments of the present invention. As shown in fig. 4, the present invention provides a phase locked loop, comprising: the phase frequency detector is configured to compare the jump edges of the first input signal UP and the second input signal DN and obtain a first output signal SLOW101 or a second output signal FAST102 according to the frequency comparison of the first input signal UP and the second input signal DN; a counter and finite state machine module 10 configured to count a first output signal SLOW101 and a second output signal FAST102, and adjust values of a first control signal itrim_up < m:0>103 and a second control signal itrim_dn < m:0>104 if a difference exceeds a threshold; and a charge pump configured to output a charge according to values of the first control signal and the second control signal.
Specifically, in the phase-locked loop, if the first input signal frequency is greater than the second input signal frequency, the first output signal SLOW101 is at a high level, the second output signal FAST102 is at a low level, and if the first input signal frequency is less than the second input signal frequency, the first output signal SLOW101 is at a low level, and the second output signal FAST102 is at a high level. In the phase-locked loop, the first output signal SLOW101 is high and the first status flag is incremented by 1, and the second output signal FAST102 is high and the second status flag is incremented by 1. In the phase-locked loop, if the difference between the first status flag bit and the second status flag bit is greater than 2 and the first status flag bit is greater than the second status flag bit, the first control signal is added with 1, and if the difference between the first status flag bit and the second status flag bit is greater than 2 and the first status flag bit is less than the second status flag bit, the second control signal is added with 1.
Further, in the phase-locked loop, the charge pump includes: a first current source 404 connected between the power supply Vdd and the output 403, configured to turn on a first switch 405 by a first control signal to sink current to the output; a second current source 406 connected between the output 403 and ground is configured to switch on a second switch 407 by a second control signal to draw current to the output. As shown in fig. 4, the charge pump further comprises mirror units of a first current source 404, a first switch 405, a second current source 406 and a second switch 407, namely a third current source 408, a third switch 409, a fourth current source 410 and a fourth switch 411.
In the phase-locked loop, the phase frequency detector includes: a first D flip-flop 401 configured such that a D terminal inputs a first input signal, a clock clk terminal inputs a second input signal through a delay td, and a Q output terminal passes through a buffer buf as a first output signal SLOW 101; the second D flip-flop 402 is configured such that the D terminal inputs the second input signal, the clk terminal inputs the first input signal through the delay td, and the Q output terminal serves as the second output signal FAST102 through the buffer buf.
Optionally, in the phase-locked loop, the method further includes: a loop filter 412 configured to connect to the output 403 of the charge pump, comprising a resistor R1, a capacitor C1, and a capacitor C2; a voltage controlled oscillator 413 configured to be connected to an output terminal of the loop filter and output a target frequency; and a frequency divider (not shown) configured to divide the input target frequency to provide a second input signal to the phase frequency detector.
As shown in fig. 5, the present invention further provides a control method of the phase-locked loop, including: initializing (Initial), the counter prohibiting the counting (cnt_en=0), and the first control signal itrim_up < m:0> and the second control signal itrim_dn < m:0> are cleared; judging whether the phase-locked loop is locked (PLLLOCK), if so, enabling a counter (CNT_EN=1), and clearing a first state flag bit CNT_SLOW and a second state flag bit CNT_FAST; otherwise, returning to the previous step after waiting for the first time T1; a first status flag bit is incremented by 1 (If SLOW: cnt_slow=cnt_slow+1) If a first input terminal connected to the first output signal SLOW101 receives a high level, and a second status flag bit is incremented by 1 (If FAST: cnt_fast=cnt_fast+1) If a second input terminal connected to the second output signal FAST102 receives a high level; after waiting for a second time T2, judging whether the absolute value difference between the first state flag bit and the second state flag bit is more than 2 (|CNT_SLOW-CNT_FAST| > 2); if yes, judging whether the first state flag bit is larger than the second state flag bit; otherwise, ending; if the first status flag bit is greater than the second status flag bit, the first control signal is added by 1 (itrim_up < m:0> = itrim_up < m:0> + 1), otherwise the second control signal is added by 1 (itrim_dn < m:0> = itrim_dn < m:0> + 1); after waiting the third time T3, the process returns to the initialized process.
The inventor of the invention finds that the reference strays originate from circuit mismatch and nonlinear effects, and more strict requirements are imposed on the reference strays in many application occasions, and the reference strays can be reduced from the phase frequency detector and the charge pump. For example, as shown in fig. 2, a fixed compensation current is introduced at the output of the charge pump, thereby reducing the reference spurious of the output. As further shown in fig. 3, a fixed compensation delay is introduced in the reset path of the phase frequency detector to reduce the output reference spurs. Although the method shown in fig. 3 is more effective for reducing the reference spurs, its controllability is less than the method shown in fig. 2 and thus more jitter may be introduced.
Based on the insight, the invention provides a phase-locked loop, which is added with an automatic calibration function on the basis of the method shown in fig. 2, so as to adapt to more application occasions and requirements. Based on the structure of the original charge pump and the phase frequency detector, the invention introduces an automatic calibration mechanism to automatically calibrate the phase-locked loop after power-on, thereby achieving the purpose of reducing reference spurious.
When the magnitude control signals itrim_up < m:0>103 and itrim_dn < m:0>104 of the UP and down currents of the charge pump change, the reference spurious of the phase-locked loop also changes, the relation between the first input signal UP and the second input signal DN is detected through the phase frequency detector, and the proportion of the UP current Iup and the down current Idn of the charge pump which are optimal for the reference spurious can be found by combining a state machine circuit.
The reference spurious power of the phase-locked loop of the present invention is:
，
where Kvco represents the gain of the voltage controlled oscillator,，finrepresenting the frequency of the first input signal, +.>Is the current of the charge pump, ">Is the impedance of the loop filter.
Fig. 6 shows the output reference spurs without an auto-calibration mechanism and with a calibration mechanism. As shown in fig. 6, the first input fin=20 MHz, the gain kvco=50 MHz/V, n=223, r1=2kohm, c1=700 pF, c2=10 pF of the voltage controlled oscillator, and the reference spurious is reduced from around-95 to around-105 by calibration.
The calibration circuit is automatically calibrated once each time it is powered up, so that the circuit operates in an optimal state, which eliminates the effect of the process. When the working environment of the circuit changes, namely the power supply voltage, the temperature and the PLL parameters change, the calibration circuit is opened once at intervals by setting on the system, so that the influence of the temperature, the power supply voltage and the PLL parameters is eliminated.
In summary, the above embodiments describe different configurations of the pll in detail, and of course, the present invention includes but is not limited to the configurations listed in the above embodiments, and any configuration that is changed based on the configurations provided in the above embodiments falls within the scope of protection of the present invention. One skilled in the art can recognize that the above embodiments are illustrative.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, the description is relatively simple because of corresponding to the method disclosed in the embodiment, and the relevant points refer to the description of the method section.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (6)
1. A phase locked loop, comprising:
the phase frequency detector is configured to compare jump edges of the first input signal and the second input signal and obtain a first output signal or a second output signal according to frequency comparison of the first input signal and the second input signal;
a counter and finite state machine module configured to count the first output signal and the second output signal, and adjust the values of the first control signal and the second control signal if the difference exceeds a threshold; and
a charge pump configured to output a charge according to values of the first control signal and the second control signal;
if the first input signal frequency is greater than the second input signal frequency, the first output signal is high level, the second output signal is low level, and if the first input signal frequency is less than the second input signal frequency, the first output signal is low level, the second output signal is high level;
the first output signal is high level and the first state flag bit is added with 1, and the second output signal is high level and the second state flag bit is added with 1;
if the difference between the first status flag bit and the second status flag bit is greater than 2 and the first status flag bit is greater than the second status flag bit, the first control signal is added with 1, and if the difference between the first status flag bit and the second status flag bit is greater than 2 and the first status flag bit is less than the second status flag bit, the second control signal is added with 1.
2. The phase-locked loop of claim 1, wherein the charge pump comprises:
a first current source connected between the power source and the output terminal, configured to turn on the first switch by a first control signal to sink current to the output terminal;
a second current source connected between the output terminal and ground is configured to turn on the second switch by a second control signal to draw current to the output terminal.
3. The phase locked loop of claim 2, wherein the phase frequency detector comprises:
the first D trigger is configured to input a first input signal to the D end, input a second input signal through the delay device to the clk end, and take the Q output end as a first output signal through the buffer;
and the second D trigger is configured that a second input signal is input to the D end, a first input signal passing through the delay device is input to the clk end, and a second output signal is taken as the Q output end through the buffer.
4. A phase locked loop as claimed in claim 3, further comprising:
a loop filter configured to connect an output of the charge pump;
a voltage controlled oscillator configured to be connected to an output terminal of the loop filter and output a target frequency; and
and the frequency divider is configured to divide the frequency after inputting the target frequency so as to provide a second input signal to the phase frequency detector.
5. The phase locked loop of claim 4 wherein the reference spurious power of the phase locked loop is:
in the formula, kvco represents the gain, omega of the voltage-controlled oscillator in 2 elements f1infin denotes the frequency of the first input signal, |i (ω in ) I is the current of the charge pump, Z (jω) in ) Is the impedance of the loop filter.
6. A control method for the phase locked loop of claim 3, comprising:
initializing, wherein a counter is forbidden to count, and the first control signal and the second control signal are cleared;
judging whether the phase-locked loop is locked, if so, enabling the counter, and resetting the first state flag bit and the second state flag bit; otherwise, returning to the previous step after waiting for the first time;
the first status flag bit is incremented by 1 if the first input end connected to the first output signal receives a high level, and the second status flag bit is incremented by 1 if the second input end connected to the second output signal receives a high level;
after waiting for the second time, judging whether the absolute value difference value of the first state flag bit and the second state flag bit is larger than 2;
if yes, judging whether the first state flag bit is larger than the second state flag bit; otherwise, ending;
if the first state flag bit is greater than the second state flag bit, adding 1 to the first control signal, otherwise adding 1 to the second control signal;
after waiting for the third time, returning to the initialized step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310714237.5A CN116505938B (en) | 2023-06-16 | 2023-06-16 | Phase locked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310714237.5A CN116505938B (en) | 2023-06-16 | 2023-06-16 | Phase locked loop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116505938A CN116505938A (en) | 2023-07-28 |
| CN116505938B true CN116505938B (en) | 2023-09-08 |
Family
ID=87324934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310714237.5A Active CN116505938B (en) | 2023-06-16 | 2023-06-16 | Phase locked loop |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116505938B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5663991A (en) * | 1996-03-08 | 1997-09-02 | International Business Machines Corporation | Integrated circuit chip having built-in self measurement for PLL jitter and phase error |
| US6133797A (en) * | 1999-07-30 | 2000-10-17 | Motorola, Inc. | Self calibrating VCO correction circuit and method of operation |
| TW200402194A (en) * | 2002-07-17 | 2004-02-01 | Via Tech Inc | Charge-pump phase-locked loop circuit with charge calibration |
| CN1917372A (en) * | 2005-08-19 | 2007-02-21 | 英飞凌科技股份公司 | Circuit arrangement for detection of a locking condition for a phase locked loop, and a method |
| KR20090043639A (en) * | 2007-10-30 | 2009-05-07 | (주)카이로넷 | Adaptive frequency error compensation circuit and wide band frequency synthesizer including the same |
| CN101431331A (en) * | 2007-11-08 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | Self-calibration method and circuit for phase-locked loop |
| CN104038215A (en) * | 2014-06-13 | 2014-09-10 | 南京邮电大学 | Automatic frequency calibration circuit for sigma-delta fractional frequency synthesizer |
| CN104901686A (en) * | 2015-06-09 | 2015-09-09 | 中山大学 | Phase-locked loop with low phase noise |
| CN106656173A (en) * | 2016-12-26 | 2017-05-10 | 上海迦美信芯通讯技术有限公司 | Frequency calibration circuit and frequency calibration method for oscillator |
| CN113014254A (en) * | 2021-03-10 | 2021-06-22 | 苏州芯捷联电子有限公司 | Phase-locked loop circuit |
| CN114095017A (en) * | 2021-11-15 | 2022-02-25 | 深圳市闪芯微电子有限公司 | PLL chip and manufacturing method thereof |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2357381B (en) * | 1999-12-13 | 2003-12-24 | Sony Uk Ltd | Changing the output frequency of a phased-locked loop |
| US7023285B2 (en) * | 2003-07-15 | 2006-04-04 | Telefonaktiebolaget Lm Ericsson (Publ) | Self-calibrating controllable oscillator |
| US6879195B2 (en) * | 2003-07-17 | 2005-04-12 | Rambus, Inc. | PLL lock detection circuit using edge detection |
| US6952124B2 (en) * | 2003-09-15 | 2005-10-04 | Silicon Bridge, Inc. | Phase locked loop circuit with self adjusted tuning hiep the pham |
| TWI323560B (en) * | 2006-11-01 | 2010-04-11 | Princeton Technology Corp | Loop system capable of auto-calibrating oscillating frequency range and related method |
| CN104734696B (en) * | 2013-12-24 | 2017-11-03 | 上海东软载波微电子有限公司 | Phase-locked loop frequency calibrates circuit and method |
| EP3439180B1 (en) * | 2017-08-02 | 2023-03-15 | ams AG | Phase-locked loop circuit |
-
2023
- 2023-06-16 CN CN202310714237.5A patent/CN116505938B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5663991A (en) * | 1996-03-08 | 1997-09-02 | International Business Machines Corporation | Integrated circuit chip having built-in self measurement for PLL jitter and phase error |
| US6133797A (en) * | 1999-07-30 | 2000-10-17 | Motorola, Inc. | Self calibrating VCO correction circuit and method of operation |
| TW200402194A (en) * | 2002-07-17 | 2004-02-01 | Via Tech Inc | Charge-pump phase-locked loop circuit with charge calibration |
| CN1917372A (en) * | 2005-08-19 | 2007-02-21 | 英飞凌科技股份公司 | Circuit arrangement for detection of a locking condition for a phase locked loop, and a method |
| KR20090043639A (en) * | 2007-10-30 | 2009-05-07 | (주)카이로넷 | Adaptive frequency error compensation circuit and wide band frequency synthesizer including the same |
| CN101431331A (en) * | 2007-11-08 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | Self-calibration method and circuit for phase-locked loop |
| CN104038215A (en) * | 2014-06-13 | 2014-09-10 | 南京邮电大学 | Automatic frequency calibration circuit for sigma-delta fractional frequency synthesizer |
| CN104901686A (en) * | 2015-06-09 | 2015-09-09 | 中山大学 | Phase-locked loop with low phase noise |
| CN106656173A (en) * | 2016-12-26 | 2017-05-10 | 上海迦美信芯通讯技术有限公司 | Frequency calibration circuit and frequency calibration method for oscillator |
| CN113014254A (en) * | 2021-03-10 | 2021-06-22 | 苏州芯捷联电子有限公司 | Phase-locked loop circuit |
| CN114095017A (en) * | 2021-11-15 | 2022-02-25 | 深圳市闪芯微电子有限公司 | PLL chip and manufacturing method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 一种快速最优自适应频率校准电路;徐卫林;朱潮勇;于越;周茜;李海鸥;;微电子学与计算机(第04期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116505938A (en) | 2023-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7375593B2 (en) | Circuits and methods of generating and controlling signals on an integrated circuit | |
| US6297705B1 (en) | Circuit for locking an oscillator to a data stream | |
| US7583151B2 (en) | VCO amplitude control | |
| US7554413B2 (en) | Voltage controlled oscillator with compensation for power supply variation in phase-locked loop | |
| US7719329B1 (en) | Phase-locked loop fast lock circuit and method | |
| US8232822B2 (en) | Charge pump and phase-detecting apparatus, phase-locked loop and delay-locked loop using the same | |
| US8044724B2 (en) | Low jitter large frequency tuning LC PLL for multi-speed clocking applications | |
| US20030042985A1 (en) | Phase synchronizing circuit | |
| US20100214032A1 (en) | Symmetric load delay cell oscillator | |
| CN108173545B (en) | Phase-locked loop circuit, multi-phase-locked loop system and output phase synchronization method thereof | |
| US9762211B2 (en) | System and method for adjusting duty cycle in clock signals | |
| CN107294530B (en) | Calibration method and apparatus for high time To Digital Converter (TDC) resolution | |
| US10623005B2 (en) | PLL circuit and CDR apparatus | |
| JP2007116713A (en) | Radiation-hardened phase locked loop | |
| CN110138381B (en) | Charge pump circuit for phase locked loop | |
| KR20160066945A (en) | Digital Phase-Locked Loop and Operating Method thereof | |
| EP1421689B8 (en) | Differential ring oscillator stage | |
| CN109586714B (en) | Calibrating a voltage controlled oscillator to trim its gain using a phase locked loop and a frequency locked loop | |
| US7148758B1 (en) | Integrated circuit with digitally controlled phase-locked loop | |
| US9432028B2 (en) | Clock data recovery circuit and a method of operating the same | |
| CN116505938B (en) | Phase locked loop | |
| US9401720B2 (en) | Circuit arrangement and method for clock and/or data recovery | |
| US8604857B2 (en) | Power supply-insensitive buffer and oscillator circuit | |
| US6946920B1 (en) | Circuit for locking an oscillator to a data stream | |
| CN114244350A (en) | Charge-accelerated pump and phase-locked loop and method of operating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |