CN101431331A - Self-calibration method and circuit for phase-locked loop - Google Patents
Self-calibration method and circuit for phase-locked loop Download PDFInfo
- Publication number
- CN101431331A CN101431331A CNA2007100479976A CN200710047997A CN101431331A CN 101431331 A CN101431331 A CN 101431331A CN A2007100479976 A CNA2007100479976 A CN A2007100479976A CN 200710047997 A CN200710047997 A CN 200710047997A CN 101431331 A CN101431331 A CN 101431331A
- Authority
- CN
- China
- Prior art keywords
- signal
- phase
- output
- locked loop
- self
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention provides a self-calibration method and a self-calibration circuit of a phase-locked loop. The self-calibration method comprises the following steps: (1) when the phase-locked hoop is charged, the preset time of the charge time of a voltage controlled oscillator (VCO) is timed; (2) frequencies of a reference signal R of the phase-locked loop and an output feedback signal V of the VOC are compared; (3) according to the comparison result of step (2), if the frequency of the signal V is lower than the frequency of the signal R, step (4) is executed and step (2) is returned, and if the frequency of the signal V is higher than the frequency of the signal R, step (5) is executed; (4) the capacitance value of the VCO is reduced; and (5) the comparison of the frequencies of the signal R and the signal V is stopped. The self-calibration circuit based on the self-calibration method comprises a digital accumulator, a state machine and a control module. With the phase-locked loop acquiring a specified output signal, the method can effectively reduce the gain of the VOC, so as to reduce output signal jitter, shorten the ungated period of the self-calibration phase-locked loop, eliminate the influences of temperature on the output signal, and keep the operation stability of the phase-locked loop.
Description
Technical field
The present invention relates to phase-locked loop circuit, relate in particular to a kind of self-calibration of phase-locked loop method and circuit that reduces shake.
Background technology
Common electronics, computer system all have very strict sequential requirement to its assembly, so that electronics or computer are finished operation very accurately.So that the synchronous phase-locked loop circuit (PLL) of output signal and reference signal be exactly use in the electronic control system a kind of widely circuit very.The reference signal frequency that PLL can accurately control its output signal frequency and input realizes synchronously.
PLL circuit commonly used at present is the phase-locked loop circuit of charge pump.It generally includes frequency divider, phase frequency detector (PFD), charge pump (CP), low pass filter (LPF), voltage controlled oscillator (VCO).External reference signal produces the certain frequency-doubled signal identical with reference signal phase through this PLL circuit.The output signal of voltage controlled oscillator is sent in the phase frequency detector simultaneously and is compared behind signal behind the external reference signal process M frequency divider and the process Fractional-N frequency, generation charging signals (up) or discharge signal (down) control charge pump charge to low pass filter and discharge, thereby low pass filter produces control voltage Δ V
cControl voltage controlled oscillator output signal frequency.
In the above-mentioned phase-locked loop, especially the voltage controlled oscillator error that is subject to noise jamming or preposition device causes the given relatively phase-locked loop's reference signal of signal of the last output of voltage controlled oscillator to occur phase jitter easily.Because the phase jitter that voltage controlled oscillator output signal produces and the gain of voltage controlled oscillator and control voltage Δ V
cBe directly proportional, therefore more obvious for this phenomenon of voltage controlled oscillator of big gain.
Provide a kind of method of self-calibration of phase-locked loop in one piece of article that 2004 deliver on American I EEE circuit and device magazine, gained and reduce the shake of the voltage controlled oscillator output signal relative datum signal that preposition device sum of errors noise causes so that obtain suitable voltage controlled oscillator.By comparing the input voltage and the reference voltage V of voltage controlled oscillator
RefSize reduce the voltage controlled oscillator capacitance, again compare again after all need waiting 250us behind the capacitance of a controlled oscillator of every reduction, therefore the blocking time of this phase-locked loop is longer easily, secondly owing between voltage controlled oscillator and low pass filter and reference voltage, all be connected with switch, when the switching of switch, cause the instability of voltage controlled oscillator control voltage easily.What described reference voltage adopted is bandgap voltage reference, and this voltage versus temperature changes very responsive, also can cause the instability of whole phase-locked loop operation.
Summary of the invention
The object of the present invention is to provide a kind of method for self-calibrating and circuit of phase-locked loop, to solve the problem that pll output signal shake and blocking time are long and be subjected to temperature effect easily.
To achieve the above object, the method for self-calibrating of phase-locked loop of the present invention may further comprise the steps: step 1: the charging interval to described voltage controlled oscillator when phase-locked loop powers on is carried out the timing of Preset Time; Step 2: the frequency speed of the output feedback signal of more given phase-locked loop's reference signal and voltage controlled oscillator; Step 3: according to the comparative result of step 2, the execution in step 4 and turn back to the step 2 if output of voltage controlled oscillator is slower than the reference signal of given phase-locked loop is if the output feedback signal frequency of described voltage controlled oscillator is faster than described phase-locked loop's reference signal then execution in step 5; Step 4: the capacitance that reduces voltage controlled oscillator; Step 5: stop to the frequency ratio of the output feedback signal of given phase-locked loop's reference signal and voltage controlled oscillator.The Preset Time of voltage controlled oscillator is 220 delicate in the step 1.The output feedback signal of phase-locked loop's reference signal and voltage controlled oscillator comprises the reference signal and the feedback signal of passing through respectively behind the frequency divider in the step 2.The speed that compares two signal frequencies in the step 2 is whether to reach the anti-signal that overturns number of times of expectation earlier by the transition times of differentiating two signals under the identical start time to realize, the saltus step of described signal is the rising edge or the trailing edge of signal level, and described expectation upset number of times is 512 times.
The self-calibration circuit of phase-locked loop of the present invention, it comprises: digital accumulator, state machine, control module; The input of control module is connected with the output feedback signal of given phase-locked loop's reference signal and voltage controlled oscillator, and be connected with the output of digital accumulator, the output of control module links to each other with the input of digital accumulator, the output of digital accumulator links to each other with the input of state machine, and the output of state machine links to each other with the control end of voltage controlled oscillator capacitance.When the digital accumulator module is used for phase-locked loop and powers on the charging interval of voltage controlled oscillator is carried out the Preset Time timing and the frequency speed of the output feedback signal of the reference signal of phase-locked loop and voltage controlled oscillator relatively; State machine is used for reducing the voltage controlled oscillator capacitance during faster than the output feedback signal of described voltage controlled oscillator when described phase-locked loop's reference signal; Control module is used for starting the speed of digital accumulator comparison two signals and stops the comparison of digital accumulator to described two signals during faster than the reference signal of described phase-locked loop when described voltage controlled oscillator output feedback signal frequency when the voltage controlled oscillator charging interval arrives Preset Time.
Digital accumulator comprises two counters and a timer, and two counters are used for more described reference signal and feedback frequency signal speed, and timer is used for when phase-locked loop powers on the charging interval to voltage controlled oscillator and carries out the Preset Time timing.The timing of timer is 220 microseconds, and two counters are nine binary counter, is used for the transition times counting to described reference signal and feedback signal.The output of the counter that the transition times of reference signal is counted links to each other with the state machine input, and link to each other with the set/zero clearing input of two counters in the digital accumulator, timer starts and phase-locked loop powers on synchronously, and timer output end links to each other with the control module input.
State machine is made of state counter, and the output of the counter of in its input and the described digital accumulator reference signal being counted links to each other, and its output links to each other with voltage controlled oscillator electric capacity control end.
Control module is made up of some gates.Described gate comprises two and door and a not gate, output to the counter of feedback signal counting in not gate input and the digital accumulator links to each other, the output of not gate links to each other with the input of door with two simultaneously, two link to each other with feedback signal with described reference signal respectively with the door input, and link to each other with the output of timer in the digital accumulator, two link to each other with the input of two counters during numeral adds up respectively with gate output terminal.
The input of control module with comprise that reference signal and feedback signal are respectively by being connected with the input of control module behind the frequency divider being connected of described reference signal and feedback signal.
Self-calibration of phase-locked loop method of the present invention and circuit, by the counting that two signals carry out certain number of times being compared the speed of two signal frequencies and adopts state machine control voltage controlled oscillator capacitance size guaranteeing under certain output signal frequency with digital accumulator, obtain less voltage controlled oscillator gain, can effectively shorten the blocking time of phase-locked loop and the shake of reduction voltage controlled oscillator output signal like this, and the stable temperature influence that is difficult for of whole phase-locked loop operation.
Description of drawings
By following examples and in conjunction with the description of its accompanying drawing, can further understand purpose, specific structural features and the advantage of its invention.Wherein, accompanying drawing is:
Fig. 1 is the self-calibration of phase-locked loop method flow diagram.
Fig. 2 is the phase-locked loop circuit figure of self-calibration circuit.
Fig. 3 is self-calibration of phase-locked loop circuit inner structure figure.
Embodiment
Below will be described in further detail in conjunction with the accompanying drawings self-calibration of phase-locked loop method of the present invention and circuit.
Self-calibration of phase-locked loop method concrete steps of the present invention comprise: step 1: the charging interval to described voltage controlled oscillator when phase-locked loop powers on is carried out the timing of Preset Time; Step 2: the frequency speed of the output feedback signal V of more given phase-locked loop's reference signal R and voltage controlled oscillator; Step 3: according to the comparative result of step 2, the execution in step 5 and turn back to step 2 if signal V is slower than R is if described signal V frequency is faster than signal R then execution in step 6; Step 5: the capacitance that reduces VCO; The frequency ratio of step 6: stop signal R and signal V.
Preset Time is 220us in the step 1, for guaranteeing the frequency of comparison signal V and R when voltage controlled oscillator has stable output, waits for the frequency speed of voltage controlled oscillator through comparison signal R after the charging interval of 220us and signal V.Signal R and signal V compare through behind the frequency divider respectively again.Whether the number of times of comparison signal R and signal V saltus step reaches the number of times of expectation.The number of times of signal saltus step is meant that the number of times of rising edge or trailing edge appears in signal, is chosen for 512 times at the number of times of this expectation.Based on choosing of every step parameter, the flow process of method for self-calibrating of the present invention sees also Fig. 1.
The present invention realizes the self-calibration circuit of above-mentioned method for self-calibrating, sees also Fig. 2, and it comprises: digital accumulator, state machine and control module, and as shown in dashed rectangle among the figure.The input of control module is connected with output feedback signal V with signal R, and is connected with an output of digital accumulator; The output of control module links to each other with the input of digital accumulator, and another output of digital accumulator links to each other with the input of state machine; The output of state machine links to each other with the control end of voltage controlled oscillator capacitance.When the digital accumulator module is used for phase-locked loop and powers on the charging interval of voltage controlled oscillator is carried out Preset Time timing and the frequency speed of the output feedback signal V of the reference signal R of phase-locked loop and voltage controlled oscillator relatively; State machine is used to judge the comparative result of described two signals and reduces the voltage controlled oscillator capacitance during faster than described output feedback signal V as described signal R; Control module is used for starting the speed of digital accumulator comparison signal R and signal V and stops the comparison of digital accumulator to described two signals during faster than described reference signal R when described output feedback signal V frequency when the voltage controlled oscillator charging interval arrives Preset Time.The reference signal on-position of phase-locked loop is shown among Fig. 21, the output feedback signal of voltage controlled oscillator is shown among Fig. 22, and these two signals can be respectively sent into digital accumulator more simultaneously through respective signal R and signal V behind the frequency divider of the frequency divider of a M and N and compared.
The cut-away view of self-calibration circuit is as shown in Figure 3: digital accumulator is shown in frame of broken lines 9, and it comprises two counters and a timer; State machine is shown in frame of broken lines 10, and it is made up of a state counter; Control module is shown in frame of broken lines 11, and it comprises two and door and a not gate.
The input of state counter links to each other with the output of the counter that is connected signal R in the state machine, and output 7 links to each other with the capacitance control end of voltage controlled oscillator.When the transition times of reference signal R arrived 512 predetermined upset number of times earlier, state counter will subtract one on original output valve, and the voltage controlled oscillator capacitance that is connected with output 7 will further be reduced on original capacitance like this.
Two inputs with door position 5 and position 6 are connected signal R and signal V respectively in the control module, two are connected the output of timer simultaneously with separately another input of door, two outputs with door link to each other with the clock signal input terminal (Clk) of two counters respectively, when the charging interval of voltage controlled oscillator reaches 220us, two with goalkeeper simultaneously the enabling counting device begin counting; The input of the not gate in the control module links to each other with the output of the counter that is connected signal V, the output of not gate linked to each other with the input of door with two with the while, when signal V reached 512 saltus steps earlier, the output of not gate stopped two counter works by two with goalkeeper.
For the error of the preposition device that prevents VCO or ambient noise because the bigger gain of voltage controlled oscillator makes pll output signal have bigger shake, the present invention gains and reaches the purpose that reduces output jitter by reducing VCO.The gain of VCO and its capacitance are inversely proportional to, and the increase of electric capacity can effectively reduce its gain.Yet frequency and VCO capacitance are inversely proportional to.Satisfying under the output signal frequency like this, the capacitance that increases VCO can reach the purpose that reduces the VCO gain.The electric capacity of VCO has a plurality of electric capacity to be formed in parallel at present, and each electric capacity all connects a switching transistor, controls the size of voltage controlled oscillator capacitance by the through and off of controlling these switching transistors.
When phase-locked loop powered on, switching transistor was whole conductings among the output of the state counter control VCO, makes VCO have less gain so in the present invention.Timer begins the capacitor charging time of voltage controlled oscillator is picked up counting in the digital accumulator simultaneously, when arriving 220us, the counter that timer starts in the digital accumulator begins signal R and signal V counting, when signal R reaches 512 saltus steps earlier, connect signal R counter with outputs two counter set Rst will be simultaneously with two counter sets or zero clearing, make two counters restart counting simultaneously, meanwhile, another output of this counter makes the output of state counter subtract one on original value, thereby make that a capacitance switch transistor disconnects among the VCO, the VCO output frequency can increase like this, and R once compares again again with signal; When signal V reached 512 saltus steps earlier, the output that connects the counter of signal V linked to each other with control module, stops the work of two counters by control module.Under the frequency that obtains suitable pll output signal, can obtain less VCO gain like this.
Control module in the present embodiment; be used for when the voltage controlled oscillator charging interval arrives Preset Time, starting the speed of digital accumulator comparison signal R and signal V and stop the comparison of digital accumulator during faster than described reference signal R when described output feedback signal V frequency described two signals; the gate of control module can have multiple variation like this; the control module of not limiting to three gates enumerating herein, control figure accumulator are carried out the control module of work in a manner described all in the protection range of patent of the present invention.
Because this calibration steps needn't compare after all need waiting 250us after each reduction capacitance size more again, can effectively reduce the blocking time of phase-locked loop like this; Do not adopt thermally sensitive bandgap voltage reference in the calibration circuit, so this calibration circuit is difficult for temperature influence yet; Between VCO and preposition device, do not have the switching of switch, keep the stable of VCO input voltage easily.
Claims (14)
1, a kind of method for self-calibrating of phase-locked loop, described phase-locked loop comprise two frequency dividers, phase frequency detector, charge pump, low pass filter and voltage controlled oscillators, it is characterized in that method for self-calibrating may further comprise the steps:
Step 1: the charging interval to described voltage controlled oscillator when phase-locked loop powers on is carried out the timing of Preset Time;
Step 2: the frequency speed of the output feedback signal of more given phase-locked loop's reference signal and voltage controlled oscillator;
Step 3: according to the comparative result of step 2, if the output of voltage controlled oscillator is slower than the benchmark of given phase-locked loop
Signal is execution in step 4 and turn back to step 2 then, if the output feedback signal frequency of described voltage controlled oscillator is faster than described phase-locked loop's reference signal then execution in step 5;
Step 4: the capacitance that reduces voltage controlled oscillator;
Step 5: stop to the frequency ratio of the output feedback signal of given phase-locked loop's reference signal and voltage controlled oscillator.
2, method for self-calibrating as claimed in claim 1 is characterized in that, the Preset Time of voltage controlled oscillator is 220 microseconds in the described step 1.
3, method for self-calibrating as claimed in claim 1 is characterized in that, the output feedback signal of phase-locked loop's reference signal and voltage controlled oscillator comprises the reference signal and the feedback signal of passing through respectively behind the frequency divider in the described step 2.
4, method for self-calibrating as claimed in claim 1 is characterized in that, whether the speed that compares two signal frequencies in the described step 2 is to have the signal that arrives expectation upset number of times earlier to realize by the transition times of differentiating two signals under the identical start time.
5, method for self-calibrating as claimed in claim 4 is characterized in that, the saltus step of described signal is the rising edge or the trailing edge of signal level.
6, method for self-calibrating as claimed in claim 4 is characterized in that, described expectation upset number of times is 512 times.
7, a kind of self-calibration circuit of phase-locked loop, described phase-locked loop comprises the voltage controlled oscillator with variable capacitance, it is characterized in that, self-calibration circuit comprises: digital accumulator, state machine, control module; The input of described control module is connected with the output feedback signal of given phase-locked loop's reference signal and voltage controlled oscillator, and be connected with the output of digital accumulator, the output of described control module links to each other with the input of digital accumulator, the output of described digital accumulator links to each other with the input of state machine, and the output of described state machine links to each other with the control end of voltage controlled oscillator capacitance;
When described digital accumulator is used for phase-locked loop and powers on the charging interval of voltage controlled oscillator is carried out the Preset Time timing and the frequency speed of the output feedback signal of the reference signal of phase-locked loop and voltage controlled oscillator relatively, described state machine is used for reducing the voltage controlled oscillator capacitance during faster than described output feedback signal when described reference signal, and described control module is used for the speed of startup digital accumulator comparison two signals when the voltage controlled oscillator charging interval arrives Preset Time and stops the comparison of digital accumulator to described two signals during faster than described reference signal when described output feedback signal frequency.
8, self-calibration circuit as claimed in claim 7, it is characterized in that: described digital accumulator comprises two counters and a timer, two counters are used for more described reference signal and feedback frequency signal speed, and described timer is used for when phase-locked loop powers on the charging interval to voltage controlled oscillator and carries out the Preset Time timing.
9, self-calibration circuit as claimed in claim 8 is characterized in that: the timing of described timer is 220 microseconds, and described counter is nine binary counter, is used for the transition times counting to described reference signal and feedback signal.
10, self-calibration circuit as claimed in claim 9, it is characterized in that: the output of the described counter that the transition times of reference signal is counted links to each other with the state machine input, and link to each other with the set/zero clearing input of two counters in the digital accumulator, described timer starts and phase-locked loop powers on synchronously, and described timer output end links to each other with the control module input.
11, self-calibration circuit as claimed in claim 7, it is characterized in that: described state machine is made of state counter, the output of the counter of in its input and the described digital accumulator reference signal being counted links to each other, and its output links to each other with voltage controlled oscillator electric capacity control end.
12, self-calibration circuit as claimed in claim 7 is characterized in that: described control module is combined into by some gates.
13, self-calibration circuit as claimed in claim 12, it is characterized in that: described some gates comprise two and door and a not gate, output to the counter of described feedback signal counting in described not gate input and the digital accumulator links to each other, the output of described not gate links to each other with the input of door with two simultaneously, described two link to each other with feedback signal with described reference signal respectively with the door input, and link to each other with the output of timer in the digital accumulator, described two link to each other with the input of two counters during numeral adds up respectively with gate output terminal.
14, self-calibration circuit as claimed in claim 7 is characterized in that: the input of described control module with comprise that reference signal and feedback signal are respectively by being connected with the input of control module behind the frequency divider being connected of described reference signal and feedback signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100479976A CN101431331B (en) | 2007-11-08 | 2007-11-08 | Self-calibration method and circuit for phase-locked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100479976A CN101431331B (en) | 2007-11-08 | 2007-11-08 | Self-calibration method and circuit for phase-locked loop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101431331A true CN101431331A (en) | 2009-05-13 |
| CN101431331B CN101431331B (en) | 2011-03-23 |
Family
ID=40646529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100479976A Active CN101431331B (en) | 2007-11-08 | 2007-11-08 | Self-calibration method and circuit for phase-locked loop |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101431331B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104682956A (en) * | 2015-01-26 | 2015-06-03 | 电子科技大学 | Phase-locked loop with correction and correction method thereof |
| CN107094014A (en) * | 2017-06-28 | 2017-08-25 | 灿芯半导体(上海)有限公司 | A kind of interface circuit |
| CN107294529A (en) * | 2017-06-26 | 2017-10-24 | 珠海全志科技股份有限公司 | A kind of digital phase-locked loop for realizing infinite precision |
| CN107515566A (en) * | 2016-06-15 | 2017-12-26 | 施耐德电气工业公司 | Noise filter, noise filtering method and programmable logic controller (PLC) |
| CN116436459A (en) * | 2023-06-12 | 2023-07-14 | 牛芯半导体(深圳)有限公司 | Calibration circuit |
| CN116505938A (en) * | 2023-06-16 | 2023-07-28 | 核芯互联科技(青岛)有限公司 | Phase locked loop |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4502165B2 (en) * | 2001-04-10 | 2010-07-14 | ルネサスエレクトロニクス株式会社 | Lock detection circuit |
| JP2006180194A (en) * | 2004-12-22 | 2006-07-06 | Toshiba Corp | Frequency synthesizer |
-
2007
- 2007-11-08 CN CN2007100479976A patent/CN101431331B/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104682956A (en) * | 2015-01-26 | 2015-06-03 | 电子科技大学 | Phase-locked loop with correction and correction method thereof |
| CN107515566A (en) * | 2016-06-15 | 2017-12-26 | 施耐德电气工业公司 | Noise filter, noise filtering method and programmable logic controller (PLC) |
| CN107294529A (en) * | 2017-06-26 | 2017-10-24 | 珠海全志科技股份有限公司 | A kind of digital phase-locked loop for realizing infinite precision |
| CN107294529B (en) * | 2017-06-26 | 2020-08-25 | 珠海全志科技股份有限公司 | Digital phase-locked loop for realizing infinite precision |
| CN107094014A (en) * | 2017-06-28 | 2017-08-25 | 灿芯半导体(上海)有限公司 | A kind of interface circuit |
| CN107094014B (en) * | 2017-06-28 | 2023-10-03 | 灿芯半导体(上海)股份有限公司 | Interface circuit |
| CN116436459A (en) * | 2023-06-12 | 2023-07-14 | 牛芯半导体(深圳)有限公司 | Calibration circuit |
| CN116436459B (en) * | 2023-06-12 | 2024-03-01 | 牛芯半导体(深圳)有限公司 | Calibration circuit |
| CN116505938A (en) * | 2023-06-16 | 2023-07-28 | 核芯互联科技(青岛)有限公司 | Phase locked loop |
| CN116505938B (en) * | 2023-06-16 | 2023-09-08 | 核芯互联科技(青岛)有限公司 | Phase locked loop |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101431331B (en) | 2011-03-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101431331B (en) | Self-calibration method and circuit for phase-locked loop | |
| US7212051B1 (en) | Control signal generation for a low jitter switched-capacitor frequency synthesizer | |
| US10511312B1 (en) | Metastable-free output synchronization for multiple-chip systems and the like | |
| US6937075B2 (en) | Method and apparatus for reducing lock time in dual charge-pump phase-locked loops | |
| JP7417718B2 (en) | Phase-locked acceleration circuit and phase-locked loop system based on control signal pulse width extraction | |
| EP2291916B1 (en) | Automatic synchronization of an internal oscillator to an external frequency reference | |
| US8040156B2 (en) | Lock detection circuit and lock detecting method | |
| US7375563B1 (en) | Duty cycle correction using input clock and feedback clock of phase-locked-loop (PLL) | |
| US8432061B2 (en) | Digital frequency divider | |
| US8415998B2 (en) | PLL circuit | |
| CN102195641A (en) | Phase-locked loop start up circuit | |
| CN101640536A (en) | Locking detector of phase-locked loop (PLL) and detection method thereof | |
| US20070096840A1 (en) | Method and apparatus for rapid local oscillator frequency calibration | |
| US7859313B2 (en) | Edge-missing detector structure | |
| US8643402B2 (en) | Phase frequency detector circuit | |
| US8618851B2 (en) | Phase-locked loop apparatus and tuning voltage providing circuit thereof | |
| CN107026647B (en) | Time-to-digital system and frequency synthesizer | |
| EP0620651B1 (en) | Method and apparatus for standby recovery in a phase locked loop | |
| Chiu et al. | A 5.5-GHz 16-mW fast-locking frequency synthesizer in 0.18-μm CMOS | |
| JP4459923B2 (en) | PLL synthesizer | |
| EP1662663B1 (en) | PLL circuit | |
| CN102055443B (en) | Duty cycle detection circuit | |
| CN115459766A (en) | Fast locking frequency synthesizer based on frequency phase compensation | |
| CN107070449A (en) | Frequency Zoom method, circuit and associated all-digital phase-lock loop | |
| CN111835344B (en) | Phase-locked loop circuit and terminal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |