CN104038215A - Automatic frequency calibration circuit for sigma-delta fractional frequency synthesizer - Google Patents
Automatic frequency calibration circuit for sigma-delta fractional frequency synthesizer Download PDFInfo
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Abstract
The invention discloses an automatic frequency calibration circuit for a sigma-delta fractional frequency synthesizer. The automatic frequency calibration circuit mainly comprises a 2M-divided frequency divider, a controlled counter, a comparator and a state machine, wherein the 2M-divided frequency synthesizer is used for controlling the running of the counter, the comparator and the state machine and the valid counting duration of the controlled counter, providing a sampling or working clock for the comparator and the state machine, and coordinating the time sequence relation between the comparator and the state machine; the comparator is used for comparing the reference of a frequency clock fREF and a feedback clock fDIV. The automatic frequency calibration circuit is at a rough calibration stage at a low level, and is at a fine calibration stage at a high level. At the rough calibration stage, the phase-locked loop of the frequency synthesizer is switched off, and the analog control end of a VCO (Voltage Control Oscillator) is connected with a fixed level. At the rough calibration stage, a result signal is at a low level, thus a sigma-delta decimal modulator is switched off, and the frequency error generated on the count value of the feedback clock fDIV by a decimal frequency dividing ratio part generated by the sigma-delta decimal modulator is lowered. At the fine calibration stage, the circuit runs normally.
Description
Technical field
The present invention relates to a kind of ∑-△ (sigma-delta) fractional frequency synthesizer automatic frequency calibration circuit, belong to integrated circuit (IC) design field.
Background technology
∑-△ fractional frequency synthesizer is the key modules of transceiver radio frequency front end chip, can be for the transceiver of various criterion provides stable, programmable, low noise local oscillations clock, its performance determines or affects the performance of whole wireless transceiver system.Because its output clock has, spectral purity is high, operating frequency is high, and phase noise is low, low in energy consumption, be easy to, in the advantage such as sheet is integrated, therefore be widely used in academia and industrial circle.
As shown in Figure 1, it is the structured flowchart of typical ∑-△ fractional frequency synthesizer, mainly comprise following part: phase frequency detector, charge pump, loop filter, voltage controlled oscillator (VCO, VoltageControlOscillator), programmable frequency divider, except 2 frequency dividers, ∑-△ decimal modulator and automatic frequency calibration circuit (AFC, Automatic Frequency Calibration).
Briefly introduce the effect of the each main modular of charge pump phase lock loop frequency synthesizer below:
1) phase frequency detector
An input of phase frequency detector is reference clock f
rEF, another input is to output clock f
oUTcarry out the feedback clock f obtaining after frequency division
dIV, phase frequency detector carries out the comparison of frequency, phase difference value to reference clock and feedback clock, mirror the comparative result of frequency and phase place with the Pulse-width Anti of output signal, produces pulse control signal UP, DOWN.
2) charge pump
According to the phase place comparative result of phase frequency detector output, electric capacity is carried out to charge or discharge, convert pulse control signal UP, DOWN to current signal I
cp, to produce the voltage corresponding with difference on the frequency, the phase difference of reference clock and feedback clock.3) loop filter
The current signal I that charge pump produces
cpcontrol voltage V to the capacitor charge and discharge in loop filter with generation voltage controlled oscillator
ctrl.
4) voltage controlled oscillator
VCO is for generation of the output clock (f of frequency synthesizer
oUT).Conventionally, VCO has digital control end and simulation control end.Its frequency of oscillation is by digital control end and analog control voltage V
ctrlcontrol.
5) programmable frequency divider
For the output clock of voltage controlled oscillator is carried out to Fractional-N frequency, because two inputs of phase frequency detector are the feedback signals of reference signal and frequency divider output, therefore the output of phase frequency detector regulates the frequency of oscillation of voltage controlled oscillator after by low pass filter filtering, thus the frequency of the output signal of this table frequency divider indirectly.
6) except 2 frequency dividers
Using as frequency mixer to subsequent conditioning circuit except 2 frequency dividers are mainly used in forming orthogonal I/Q clock outside phase-locked loop.
7) ∑-△ decimal modulator
On the basis of integral frequency divisioil, add ∑-△ decimal modulator, change as basis taking a fixing integral multiple frequency division, exportable fractional frequency division ratio in some cycles, is well controlled spuious problem by randomization frequency dividing ratio.As shown in Figure 3, the reset termination result signal of ∑-△ decimal modulator, clock end clk meets feedback clock f
dIV, input K receives fractional frequency division value by spi bus.
8) automatic frequency calibration circuit
While adopting the voltage controlled oscillator output frequency of multiband, need the concrete output band of selecting, first carry out coarse adjustment process and then carry out thin tuning.The effect of automatic frequency calibration circuit is exactly the optimal control word of selecting voltage controlled oscillator, ensures that output frequency drops near the centre frequency of selected frequency band as far as possible.
Existing automatic frequency calibration circuit mostly is the automatic frequency calibration circuit of counter type based on the comparison.As shown in Figure 2, be a typical schematic diagram for the automatic frequency calibration circuit of counter type based on the comparison.It is enough large to guarantee to distinguish the number of reference clock and feedback clock that the count value of two counters should arrange.Result relatively produces UP, DN signal is exported to state machine, makes state machine saltus step to corresponding frequency band.
Count value N
cntdetermined by following formula:
f
VCO＝N.F·f
DIV (2)
f
REQ＝N.F·f
REF (3)
F in formula
rEFfor reference clock frequency, therefore be multiplied by the target frequency f that needs output after frequency dividing ratio N.F (N represents the integer part of frequency dividing ratio, and F represents the fractional part of frequency dividing ratio)
rEQ, and f
dIVfor feedback clock frequency, be the frequency f of voltage controlled oscillator output therefore be multiplied by after frequency dividing ratio N.F
vCO.F
tHfor the frequency f of voltage controlled oscillator output
vCOtarget frequency f with needs output
rEQpoor.N
cntbe a threshold value, while being greater than this threshold value through the difference of counter counting relatively afterwards, state machine will change its status word and repeat above-mentioned comparison procedure until determine optimal control word.The defect of this method is exactly because N
cntvalue is an approximation, thereby precision deficiency, not necessarily can choose best frequency adjustment curve in frequency calibration process.
Summary of the invention
Goal of the invention: the problem and shortage existing for above-mentioned prior art, the invention provides a kind of ∑-△ fractional frequency synthesizer automatic frequency calibration circuit.
Technical scheme: in order to realize foregoing invention object, the present invention openly proposes kind of ∑-△ fractional frequency synthesizer automatic frequency calibration (AFC, Automatic Frequency Calibration) circuit, belongs to integrated circuit (IC) design field.
∑-△ fractional frequency synthesizer of the present invention includes one except 2 with automatic frequency calibration circuit
mfrequency divider, a controlled counter, a comparator and a state machine, describedly remove 2
mthe running of frequency divider control counter, comparator and state machine; Except 2
mthe input end of clock clk of frequency divider connects the output of derived reference signal, except 2
mthe first output Qa of frequency divider meets the clock signal input terminal clk of comparator, except 2
mthe second output Qb of frequency divider meets the clock signal input terminal clk of state machine, except 2
mthe 3rd output Qbn of frequency divider accepts the input ctrl of control counter, the input D of controlled counter connects the output of programmable frequency divider, the output Q of controlled counter meets another input D of comparator, the output Q of comparator meets the input D of state machine, the output rslt output result signal of state machine, connect the reset input of ∑-△ modulator, another output Q output n position control word of state machine connects the input of voltage controlled oscillator simultaneously; The derived reference signal of frequency synthesizer, phase frequency detector, charge pump, loop filter, single-pole double-throw switch (SPDT) SW, voltage controlled oscillator, be connected in series except 2 frequency dividers orders; The output of voltage controlled oscillator is also connected with the input of programmable frequency divider, the input of the output termination programmable frequency divider of ∑-△ modulator.
Described single-pole double-throw switch (SPDT) SW, at thick calibration phase, disconnects frequency synthesizer phase-locked loop, and the simulation control end of voltage controlled oscillator is connected and fixed level VDD/2; And thin calibration phase, frequency synthesizer phase-locked loop closure, loop automatic calibration running.
Particularly, control effective counting duration of controlled counter, for comparator and state machine provide sampling or work clock, and coordinating the sequential relationship between them, comparator is used for reference clock f
rEFand feedback clock f
dIVcarry out frequency ratio, state machine module is on comparator frequency ratio basis, according to successive approximation algorithm, produce frequency control word and the result signal of n position: wherein, n bit digital control signal brings in by controlling the numerical control of multi-band voltage controlled oscillator (VCO) frequency band of selecting VCO work, result signal can identification circuit be in thick calibration phase or thin calibration phase, is thick calibration phase when low level, when high level, is thin calibration phase, simultaneously, result signal is also being controlled single-pole double-throw switch (SPDT): by controlling single-pole double-throw switch (SPDT), at thick calibration phase, frequency synthesizer phase-locked loop disconnects, the simulation control end of VCO is connected and fixed level (half of supply voltage), and thin calibration phase, frequency synthesizer phase-locked loop closure, loop automatic calibration running, result signal is also received the reset end of ∑-△ decimal modulator, reset end is reset terminal, need to there is a process from low level to high level could start ∑-△ decimal modulator, in the time of more accurate stage slightly, result signal is low level, thereby ∑-△ decimal modulator disconnects, reduce the frequency error of fractional frequency division count value generation to feedback clock fDIV than part of ∑-△ mark modulator generation, and at thin calibration phase, circuit normal operation.
Described removes 2
mfrequency divider is to input reference clock f
rEFcarry out 2
mtimes frequency division, produces three frequencies and is f
rEF/ 2
moutput clock Qa, Qb and Qbn, wherein, the clock cycle of the leading Qb1 of a Qa reference clock fREF, Qbn is the logic negate to Qb.
Described controlled counter controls end ctrl connects except 2
mthe Qbn end of frequency divider, data input pin D receives feedback clock f
dIV, output Q meets the data input pin D of comparator; When controlled counter controls end ctrl is low level, keep original count value; While being high level from low transition, controlled counter carries out the zero clearing New count of laying equal stress on.
Described comparator clock end clk connects except 2
mthe Qa end of frequency divider, data input pin D accepts the output Q of control counter, and output Q meets the data input pin D of state machine.
Described comparator with clk hold clock sampling, latch input terminal D receive data and with fixed value 2
m-1compare, comparative result is exported by output Q.
Described state machine clock end clk connects except 2
mthe Qb end of frequency divider, input D meets the output Q of comparator, and replacement port rst meets external reset signal reset, output rslt output signal result, output Q connects the digital control end of voltage controlled oscillator.
Described state machine meets the output Q of comparator with input D, on comparator frequency ratio basis according to successive approximation algorithm, the frequency control word and the result signal that produce n position, the frequency control word of n position is exported by output Q, and result signal is exported by output rslt.
Based on the basic structure of ∑-△ fractional frequency synthesizer, described removes 2
mthe input termination reference clock f of counter
rEF, its output Qa connects the clock end of comparator, and output Qb connects the clock end of state machine, and output Qbn accepts the modulus of control counter as its counting.The input termination feedback clock f of described controlled counter
dIV, the input of its output termination comparator.The input of the output termination state machine of described comparator.Reset signal is the control port of automatic frequency calibration circuit.The output output result signal of state machine, be used for controlling single-pole double-throw switch (SPDT) SW, and result signal is also received the reset end of ∑-△ decimal modulator, in more accurate stage slightly, disconnect ∑-△ decimal modulator, compare part to feedback clock f to reduce the fractional frequency division of ∑-△ decimal modulator generation
dIVthe frequency error that produces of count value, export in addition the voltage controlled oscillator of a multidigit frequency control word signal controlling multi-band.
∑-△ fractional frequency synthesizer experiences two processes altogether from tracking state to lock-out state.One, thick calibration phase.Automatically selected four control words of voltage controlled oscillator by automatic frequency calibration circuit according to the size of export target frequency, the standard of selecting is the center that target frequency should drop on selected subband as far as possible, control voltage and be in close proximity to the most at last the half of supply voltage VDD, i.e. VDD/2.Keep this control word until loop-locking.Two, thin calibration phase.When this process, voltage controlled oscillator changes the size of the variable capacitance on it, finally obtains target frequency, and its control voltage is fixed on certain determined value, is now usually said loop-locking.Experience these two processes until loop finally locks, the automatic frequency calibration circuit of a common excellent in design can shorten the loop-locking time greatly.Thick calibration phase and carefully can switch by single-pole double-throw switch (SPDT) SW the result signal controlling that the time point control signal of switching is exported by automatic frequency calibration circuit between the more accurate stage.
The present invention is based on comparison counter type, described removes 2
mcounter and controlled counter meet respectively reference clock f
rEFand feedback clock f
dIVreference clock and feedback clock are that automatic calibration frequency module is for two input clocks relatively, reset signal is the control port of automatic frequency calibration circuit, when reset signal becomes logic when high from logic low, automatic frequency calibration circuit is started working, when completing after calibration, can enter stable state, voltage controlled oscillator is humorous by one group of Optimal Control tone of Chinese characters, now single-pole double-throw switch (SPDT) SW connected ring path filter end, phase-locked loop carries out Frequency Locking process, and final loop is exported a certain target frequency value.
Beneficial effect: the automatic frequency calibration circuit of the counter type based on the comparison that a kind of ∑-△ fractional frequency synthesizer automatic frequency calibration circuit reliability that the present invention designs and ratio of precision are traditional is high, because simple in structure, be conducive to reduce circuit layout area and time cost simultaneously.
Brief description of the drawings
Fig. 1 is the structured flowchart of ∑-△ fractional frequency synthesizer,
Fig. 2 is a typical schematic diagram for the automatic frequency calibration circuit of counter type based on the comparison,
Fig. 3 is a kind of ∑-△ fractional frequency synthesizer automatic frequency calibration circuit that the present invention proposes,
Fig. 4 is the workflow of automatic frequency calibration circuit,
Fig. 5 is for process is except 2
moutput signal sequential chart after counter,
Fig. 6 is the successive approximation algorithm (4) that state machine adopts,
Fig. 7 is the Transient of automatic frequency calibration circuit,
Fig. 8 is the Transient of ∑-△ fractional frequency synthesizer.
Embodiment
For the technological means that further illustrates advantage of the present invention place and specifically take, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
Fig. 1-Fig. 2 is the introduction of existing background technology, repeats no more.
As shown in Figure 3, a kind of ∑-△ fractional frequency synthesizer provided by the present invention comprises with automatic frequency calibration circuit: one except 2
mcounter, a controlled counter, a comparator, a state machine.Wherein, described except 2
mthe input termination reference clock f of frequency divider
rEF, its output Qa connects the clock end of comparator, and output Qb connects the clock end of state machine, and output Qbn accepts the modulus of control counter as its counting.The input termination feedback clock f of described controlled counter
dIV, the input of its output termination comparator.The input of the output termination state machine of described comparator.Reset signal is the control port of automatic frequency calibration circuit.The output output result signal of state machine, for controlling single-pole double-throw switch (SPDT) SW, and result signal also receives the reset end of ∑-△ decimal modulator, exports in addition the voltage controlled oscillator of a multidigit frequency control word signal controlling multi-band.
Described removes 2
mfrequency divider is used for reference clock f
rEFcount, its output signal Qa adopts edging trigger, is the clock that count results is deposited, and deposits at the rising edge of clock; Its output signal Qb adopts edging trigger, is the clock of state machine work, and the half period that its output signal Qbn forms is effective counting duration of controlled counter.Described controlled counter is used for feedback clock f
dIVcount.Described comparator is for comparing reference clock f
rEFwith feedback clock f
dIV2
m-1individual reference clock f
rEFcomparative result in cycle, and change for the state of state of a control machine.Described state machine adopts successive approximation algorithm, for exporting the frequency control word of result signal and n position.
As shown in Figure 4, be the workflow of automatic frequency calibration circuit.After powering on, single-pole double-throw switch (SPDT) SW is communicated with fixed level VDD/2, namely voltage controlled oscillator access fixed level VDD/2, and the initial control word of voltage controlled oscillator is made as 0000 (taking 4 as example).Then reset signal is set to logic high, the highest order of voltage controlled oscillator is made as 1, and what now compare is two input clocks: reference clock f
rEF, feedback clock f
dIVsize, reference clock f
rEFfor fixed value, and value the unknown of feedback clock fDIV.With reference to clock f
rEFby removing 2
mfrequency divider, the clock cycle after frequency division is T=2
m(1/f
rEF), within half T cycle, feedback clock fDIV to be counted, ideal value should be M
dIV=(T/2)/(1/f
dIV)=2
m-1(f
dIV/ f
rEF), so within the same time to reference clock f
rEFcount, ideal value should be M
rEF=2
m-1.So work as M
dIV>M
rEFtime, can judge f
dIV>f
rEF, put this control bit is 0 simultaneously, and works as M
dIV<M
rEFtime, can judge f
dIV<f
rEF, put this control bit is 1 simultaneously.Finally judge whether this position is lowest order, if not, enter next bit and compare, if this position is lowest order, complete frequency calibration, enter the Frequency Locking stage.
If Fig. 5 is for process is except 2
moutput clock sequential chart after frequency divider.Reference clock f
rEFthrough removing 2
mafter frequency divider, export three signal: Qa, Qb and Qbn, their cycle is reference clock f
rEF2 of cycle
mdoubly.In figure, Qbn controls the operating state of controlled counter, and when it is converted to high level, controlled counter carries out the zero clearing New count of laying equal stress on; When low level, keep original count value.Qa provides the input sample clock of comparator, and rising edge sampling is deposited.Qb provides work clock for state machine.As seen from the figure, the t1 moment starts feedback clock f
dIVcounting, the t2 moment is got up controlled rolling counters forward result register, and the t3 moment is carried out data comparison, simultaneously by counter O reset.T1 and t2 time at intervals 2
m-1 reference clock f
rEFclock cycle, and 1 reference clock f of t2 and t3 time at intervals
rEFclock cycle.
Due to the randomization frequency dividing ratio that ∑-△ mark modulator is introduced, it may be M that the fractional part of frequency dividing ratio makes the count value of feedback clock fDIV within half T cycle
mIS=2
m-1(f
dIV/ f
rEF) ± 1.If f (M)=M
mIS-M
rEF, can obtain f (M)=2
m-1(f
dIV/ f
rEF) ± 1-2
m-1, suppose f (M) >0, can obtain fDIV>[1 ± (1/2
m-1)] f
rEF, now frequency error is f
rEF/ 2
m-1, the frequency dividing ratio of establishing programmable frequency divider is N, the output that frequency error is reflected into voltage controlled oscillator be exaggerated N doubly, even may cause the selection mistake of frequency control word when serious.In order to make frequency error not affect the selection of frequency control word, result signal is received to the reset end of ∑-△ decimal modulator, reset end is reset terminal, need to there is a process from low level to high level could start ∑-△ decimal modulator, in more accurate stage slightly, result signal is low level, and therefore ∑-△ mark modulator disconnects, and fractional frequency division can be to feedback clock f than part
dIVcount value exert an influence, reduced frequency error.
As shown in Figure 6, for the successive approximation algorithm of state machine employing, here taking 4 bit frequency control words as example.Compared with traditional binary logic method, can promptly obtain Optimal Control word, and the more important thing is, adopt and make in this way accuracy be greatly improved.
As shown in Figure 7, be the Transient of automatic frequency calibration circuit.In figure, be expressed as from top to bottom lowest order D1, order position D2, inferior high-order D3, the highest order D4 of the result signal of automatic frequency calibration circuit output and 4 bit frequency control words of output.As can be seen, the state variation of 4 control words is 1000 (to low level sequence, lower same by high-order), 1100,1010,1001, and be finally stabilized in 1001 state, through 4 comparisons, selected an Optimal Control word 1001, state transition process meets Fig. 6.
As shown in Figure 8, be the Transient of ∑-△ fractional frequency synthesizer.In figure, be expressed as from top to bottom the result signal of automatic frequency calibration circuit output and the control voltage Vctrl of voltage controlled oscillator.As seen from the figure, when loop starts in automatic frequency calibration phase, now result signal keeps logic low, control voltage on voltage controlled oscillator is precharged to the half (being 0.9V) of supply voltage, after optimal frequency control word is determined, now to become logic high for result signal, loop is in the Frequency Locking stage, now the control voltage on voltage controlled oscillator starts saltus step from 0.9V, until be finally stabilized in the position of the half VDD/2 (being 0.9V) that is in close proximity to supply voltage.
In sum, a kind of ∑-△ fractional frequency synthesizer provided by the invention passes through two counters respectively to reference clock f with automatic frequency calibration circuit
rEFand feedback clock f
dIVcount, result is relatively deposited to data register, and in the state conversion of state of a control machine, adopt successive approximation algorithm finally to export optimal control word to voltage controlled oscillator.
Below be only example of the present invention, do not form any limitation of the invention, obviously, under thought of the present invention, any those skilled in the art, are not departing within the scope of technical scheme of the present invention, can utilize the technology contents of above-mentioned announcement that circuit structure and components and parts size are suitably adjusted or optimized, refer to according to technology of the present invention any simple modification, equivalents and modification that above embodiment is done, all belong to the scope of technical solution of the present invention.
Claims (2)
1. ∑-△ fractional frequency synthesizer automatic frequency calibration circuit, is characterized in that: this circuit includes one except 2
mfrequency divider, a controlled counter, a comparator and a state machine, describedly remove 2
mthe running of frequency divider control counter, comparator and state machine; Except 2
mthe input end of clock clk of frequency divider connects the output of derived reference signal, except 2
mthe first output Qa of frequency divider meets the clock signal input terminal clk of comparator, except 2
mthe second output Qb of frequency divider meets the clock signal input terminal clk of state machine, except 2
mthe 3rd output Qbn of frequency divider accepts the input ctrl of control counter, the input D of controlled counter connects the output of programmable frequency divider, the output Q of controlled counter meets another input D of comparator, the output Q of comparator meets the input D of state machine, the output rslt output result signal of state machine, connect the reset input of ∑-△ modulator, another output Q output n position control word of state machine connects the input of voltage controlled oscillator simultaneously; The derived reference signal of frequency synthesizer, phase frequency detector, charge pump, loop filter, single-pole double-throw switch (SPDT) SW, voltage controlled oscillator, be connected in series except 2 frequency dividers orders; The output of voltage controlled oscillator is also connected with the input of programmable frequency divider, the input of the output termination programmable frequency divider of ∑-△ modulator.
2. a kind of ∑-△ fractional frequency synthesizer automatic frequency calibration circuit as claimed in claim 1, it is characterized in that: described single-pole double-throw switch (SPDT) SW is at thick calibration phase, disconnect frequency synthesizer phase-locked loop, the simulation control end of voltage controlled oscillator is connected and fixed level VDD/2; And thin calibration phase, frequency synthesizer phase-locked loop closure, loop automatic calibration running.
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| CN113541683B (en) * | 2021-06-08 | 2022-11-25 | 西安电子科技大学 | Phase-locked loop automatic frequency calibrator based on programmable three-frequency divider |
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