CN105187056A - Clock signal generation apparatus and clock signal generation method - Google Patents
Clock signal generation apparatus and clock signal generation method Download PDFInfo
- Publication number
- CN105187056A CN105187056A CN201510560159.3A CN201510560159A CN105187056A CN 105187056 A CN105187056 A CN 105187056A CN 201510560159 A CN201510560159 A CN 201510560159A CN 105187056 A CN105187056 A CN 105187056A
- Authority
- CN
- China
- Prior art keywords
- clock signal
- voltage
- time service
- generating device
- outside time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electric Clocks (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a clock signal generation apparatus and a clock signal generation method. The apparatus comprises an external time service module; an internal time service module; a detection module connected with the external time service module and the internal time service module; and a clock signal output module, wherein when the detection module determines that external time service signals input to the external time service module are at a normal state, the clock signal generation apparatus is controlled to be at an external time service mode, and the clock signal output module, based on the external time service signals, generates and outputs first clock signals; and when the detection module determines that the external time service signals are at an abnormal state, the clock signal generation apparatus is controlled to be at an internal time service mode, and the clock signal output module, based on the internal reference signals of the internal time service module, generates and outputs second clock signals.
Description
Technical field
The present invention relates to electronic technology field, particularly a kind of clock signal generating device and clock signal creating method.
Background technology
Phase noise directly has influence on the receiver sensitivity of radar system, the resolution of receiver bandwidth and radar, and the reference clock source of low phase noise is the basis realizing low phase noise radar system; Meanwhile, in order to improve the communication quality of built-in system and external system, the clock signal often requiring built-in system to use and the clock signal synchronization of external system; In addition, in order to the work ensureing that system can be steady in a long-term, we often need the outside reference clock of high accurate clock signal to internal system to calibrate.
At present, in order to realize this high-precision low phase noise synchronous clock source, traditional mode is as reference clock using the high precision clock of outside, this high precision clock generally selects GPS (GlobalPositioningSystem, global positioning system) time signal, or adopt high-precision atomic clock to produce, the crystal oscillator with higher short-term stability that locking is inner, its principle as shown in Figure 1.
But present inventor, in the process realizing invention technical scheme in the embodiment of the present application, finds that above-mentioned technology at least exists following technical problem:
If the high precision clock of outside selects GPS time signal, then because the position at radar system place does not receive gps signal, the clock source of radar system may be caused normally to work, whole radar system all cannot be worked; If the high precision clock of outside selects atomic clock, then can be high due to the cost of atomic clock, the factors such as volume is large, Heavy Weight can affect the realization of radar system.Visible, the technical problem existed in prior art is: when realizing high accuracy low phase noise clock source, reliability is low, and cost is higher.
Summary of the invention
The embodiment of the present invention provides a kind of clock signal generating device and clock signal creating method, and for solving the high accuracy low phase noise clock source existed in prior art, reliability is low, the technical problem that cost is higher.
On the one hand, the embodiment of the present application provides a kind of clock signal generating device, and described device comprises:
Outside time service module;
Inner time service module;
Detection module, is connected with described outside time service module and described inner time service module;
Clock signal output module;
Wherein, when the outside time signal that described detection module determines to input described outside time service module is in normal condition, control described clock signal generating device and be in outside time service pattern, described clock signal output module generates based on described outside time signal and exports the first clock signal;
When described detection module determines that described outside time signal is in abnormal state, control described clock signal generating device and be in inner time service pattern, described clock signal output module generates based on the internal reference signal of the described inner time service module of input and exports second clock signal.
Optionally, described detection module comprises:
First power splitter, for being divided into first via time signal and the second road time signal by described outside time signal;
Wave detector, is connected with described first power splitter, and described wave detector is used for generating according to described first via time signal and exporting the output voltage corresponding with the power of described outside time signal;
Comparator, is connected with described wave detector, the comparative voltage that described comparator is used for more described output voltage and pre-sets;
Single-pole double-throw switch (SPDT), the first end of described single-pole double-throw switch (SPDT) is connected with described comparator, and the cutter head of described single-pole double-throw switch (SPDT) is connected with described outside time service module or described inner time service module;
Wherein, when described output voltage is greater than or equal to described comparative voltage, the cutter head controlling described single-pole double-throw switch (SPDT) is connected with described outside time service module, is in described outside time service pattern to make described clock signal generating device; When described output voltage is less than described comparative voltage, the cutter head controlling described single-pole double-throw switch (SPDT) is connected with described inner time service module, is in described inner time service pattern to make described clock signal generating device.
Optionally, described outside time service module comprises:
Phase-locked loop circuit, is connected with described first power splitter; Described phase-locked loop circuit is used for exporting the first voltage-controlled voltage according to described second road time signal.
Optionally, described inner time service module comprises:
Bleeder circuit, described bleeder circuit is connected with the crystal oscillator in described clock signal output module, and described bleeder circuit is used for carrying out dividing potential drop to described internal reference signal, to export the second voltage-controlled voltage; Wherein, described internal reference signal is that described crystal oscillator produces according to inherent parameters and the reference voltage exported.
Optionally, clock signal output module comprises:
Crystal oscillator, is connected with the second end of described single-pole double-throw switch (SPDT), and described crystal oscillator for exporting an original clock signal under the control of described first voltage-controlled voltage or described second voltage-controlled voltage;
Second power splitter, is connected with described crystal oscillator, and described second power splitter is used for described original clock signal to be divided into first via original clock signal and the second road original clock signal;
Filtering and amplifying circuit, is connected with described second power splitter, and described filtering and amplifying circuit is used for amplifying and filtering process described first via original clock signal, exports described first clock signal or described second clock signal.
Optionally, described second power splitter is connected with described phase-locked loop circuit.
On the other hand, the embodiment of the present application also provides a kind of clock signal generation method, comprising:
The outside time signal that detection module in clock signal generating device detects the outside time service module of the described clock signal generating device of input is in normal condition or is in abnormal state;
When described outside time signal is in described normal condition, control described clock signal generating device and be in outside time service pattern, and to be generated based on described outside time signal by the clock signal output module in clock signal generating device and export the first clock signal;
When described outside time signal is in described abnormal state, control described clock signal generating device and be in inner time service pattern, and generate by the internal reference signal of described clock signal output module based on the described inner time service module of input and export second clock signal.
Optionally, the outside time signal that the detection module in clock signal generating device detects the outside time service module of the described clock signal generating device of input is in normal condition or is in abnormal state, comprising:
In described detection module, described outside time signal is divided into first via time signal and the second road time signal; The output voltage corresponding with the power of described outside time signal is exported according to described first via time signal; And more described output voltage and the comparative voltage pre-set;
Wherein, when described output voltage is greater than or equal to described comparative voltage, determine that described outside time signal is in normal condition; When described output voltage is less than described comparative voltage, determine that described outside time signal is in abnormal state.
Optionally, control described clock signal generating device and be in outside time service pattern, and to be generated based on described outside time signal by the clock signal output module in clock signal generating device and export the first clock signal, comprising:
The cutter head controlling the single-pole double-throw switch (SPDT) of described detection module is connected with described outside time service module, is in described outside time service pattern to make described clock signal generating device;
Described outside time service module generates the first voltage-controlled voltage based on described outside time signal;
Described clock signal output module generates and exports described first clock signal under the control of described first voltage-controlled voltage.
Optionally, control described clock signal generating device and be in inner time service pattern, and generate by the internal reference signal of described clock signal output module based on the described inner time service module of input and export second clock signal, comprising:
The cutter head controlling the single-pole double-throw switch (SPDT) of described detection module is connected with described inner time service module, is in described inner time service pattern to make described clock signal generating device;
The internal reference signal that described inner time service module exports based on the crystal oscillator in described clock signal output module generates and exports the second voltage-controlled voltage;
Described clock signal output module generates and exports described second clock signal under the control of described second voltage-controlled voltage.
Optionally, described clock signal output module generates and exports described second clock signal under the control of described second voltage-controlled voltage, comprising:
Described clock signal output module exports an original clock signal under the control of described second voltage-controlled voltage, amplifies and filtering process described original clock signal, exports described second clock signal.
Above-mentioned one or more technical scheme in the embodiment of the present application, at least has one or more technique effects following:
1, in the scheme of the embodiment of the present application, whether normal by automatically detecting outside time signal, when outside time signal is in normal condition, control clock signal generating device and be in outside time service pattern, when outside time signal is in abnormal state, control clock signal generating device and be in inner time service pattern, by the mode of operation of Automatic adjusument inside, compared to the high accuracy real-time clock that the outside time signal of traditional utilization realizes, when outside time signal is abnormal, still can clock signal, to realize the function of clock signal generating device place system, and then raising reliability.Compared to traditional high accuracy real-time clock realized with atomic clock, its cost is lower, and volume is less, and weight is lighter.
In the scheme of 2, the embodiment of the present application, utilize self-adaptation clock source, the clock signal generating device namely in the embodiment of the present application, synchronous with external GPS time signal, what can realize between whole communication link is synchronous, thus promotes communication quality.
Accompanying drawing explanation
Fig. 1 is the module diagram of clock source in prior art;
Fig. 2 is the module diagram of clock signal generating device in the embodiment of the present application one;
Fig. 3 is the circuit connection diagram of clock signal generating device in the embodiment of the present application one;
Fig. 4 is the flow chart of clock signal generation method in the embodiment of the present application two.
Embodiment
In the technical scheme that the embodiment of the present application provides, by the mode of operation of Automatic adjusument clock signal, compared to the high accuracy real-time clock that the outside time signal of traditional utilization realizes, when outside time signal is abnormal, still can clock signal, to realize the function of clock signal generating device place system, and then improve reliability.Compared to traditional high accuracy real-time clock realized with atomic clock, its cost is lower, and volume is less, and weight is lighter.
Technical scheme in the embodiment of the present application is solve above-mentioned technical problem, and general thought is as follows:
A kind of clock signal generating device, described device comprises:
Outside time service module;
Inner time service module;
Detection module, is connected with described outside time service module and described inner time service module;
Clock signal output module;
Wherein, when the outside time signal that described detection module determines to input described outside time service module is in normal condition, control described clock signal generating device and be in outside time service pattern, described clock signal output module generates based on described outside time signal and exports the first clock signal;
When described detection module determines that described outside time signal is in abnormal state, control described clock signal generating device and be in inner time service pattern, described clock signal output module generates based on the internal reference signal of the described inner time service module of input and exports second clock signal.
In such scheme, whether normal by automatically detecting outside time signal, when outside time signal is in normal condition, control clock signal generating device and be in outside time service pattern, when outside time signal is in abnormal state, control clock signal generating device and be in inner time service pattern, by the mode of operation of Automatic adjusument inside, compared to the high accuracy real-time clock that the outside time signal of traditional utilization realizes, when outside time signal is abnormal, still can clock signal, to realize the function of clock signal generating device place system, and then raising reliability.Compared to traditional high accuracy real-time clock realized with atomic clock, its cost is lower, and volume is less, and weight is lighter.
Below in conjunction with accompanying drawing, the main of the embodiment of the present application technical scheme is realized principle, embodiment and be explained in detail the beneficial effect that should be able to reach.
Embodiment one
The embodiment of the present application provides a kind of clock signal generating device, and this clock signal generating device can be applied in radar system, and for generating the clock signal with the clock signal synchronization of external system, as shown in Figure 2, described device comprises: outside time service module 1; Inner time service module 2; Detection module 3, is connected with described outside time service module 1 and described inner time service module 2; Clock signal output module 4;
Wherein, when the outside time signal that described detection module 3 determines to input described outside time service module 1 is in normal condition, control described clock signal generating device and be in outside time service pattern, described clock signal output module 4 generates based on described outside time signal and exports the first clock signal;
When described detection module 3 determines that described outside time signal is in abnormal state, control described clock signal generating device and be in inner time service pattern, described clock signal output module 4 generates based on the internal reference signal of the described inner time service module 2 of input and exports second clock signal.
In the embodiment of the present application, as shown in Figure 3, detection module 3 comprises: the first power splitter 31, for described outside time signal is divided into first via time signal and the second road time signal; Wave detector 32, is connected with described first power splitter 31, and described wave detector 32 is for generating according to described first via time signal and exporting the output voltage corresponding with the power of described outside time signal; Comparator 33, is connected with described wave detector 32, and described comparator 33 is for more described output voltage and the comparative voltage pre-set; Single-pole double-throw switch (SPDT) 34, the first end of described single-pole double-throw switch (SPDT) 34 is connected with described comparator 33, and the cutter head of described single-pole double-throw switch (SPDT) 34 is connected with described outside time service module 1 or described inner time service module 2.
Wherein, when described output voltage is greater than or equal to described comparative voltage, the cutter head controlling described single-pole double-throw switch (SPDT) 34 is connected with described outside time service module 1, is in described outside time service pattern to make described clock signal generating device; When described output voltage is less than described comparative voltage, the cutter head controlling described single-pole double-throw switch (SPDT) 34 is connected with described inner time service module 2, is in described inner time service pattern to make described clock signal generating device.
In the embodiment of the present application, outside time signal refers to outside GPS time signal, by the first power splitter 31, the external GPS time signal received is divided into two-way, wherein, first via time signal, by wave detector 32 detection, exports the magnitude of voltage corresponding with signal power, i.e. output voltage, and using the input of this magnitude of voltage as comparator 33, by comparing the comparative voltage size that output voltage and comparator 33 are preset, judge that whether the GPS time signal of outside is normal.Concrete, when output voltage is greater than or equal to comparative voltage, judge that outside GPS time signal is normal, when output voltage is less than comparative voltage, judge that outside GPS time signal is abnormal.Second road time signal, as the reference signal of outside time service module 1, encourages the first voltage-controlled voltage that outside time service module 1 clocking output module 4 needs;
Further, when the output voltage of wave detector 32 is greater than or equal to the comparative voltage that comparator 33 presets, start external GPS time service pattern, the cutter head being controlled single-pole double-throw switch (SPDT) 34 by switch control voltage is connected with outside time service module 1, namely selects the first voltage-controlled voltage as the control voltage of clock signal output module 4.When the output voltage of wave detector 32 is less than the comparative voltage that comparator 33 presets, start inner time service pattern, controlling single-pole double-throw switch (SPDT) 34 by switch control voltage selects the second voltage-controlled voltage as the control voltage of clock signal output module 4, wherein, the second voltage-controlled voltage is the voltage produced by clock signal generating device self.
In the embodiment of the present application, outside time service module 1 comprises: phase-locked loop circuit, is connected with described first power splitter 31; Described phase-locked loop circuit is used for exporting the first voltage-controlled voltage according to described second road time signal.Concrete, phase-locked loop circuit comprises: phase-locked loop chip 11 and loop filter 12, above-mentioned second road time signal is as the reference signal of outside time service module 1, the the first voltage-controlled voltage encouraging outside time service module 1 clocking output module 4 to need refers to: the second road time signal, as the reference signal of phase-locked loop chip 11, encourages the first voltage-controlled voltage that phase-locked loop chip 11 clocking output module 4 needs.
In the embodiment of the present application, inner time service module 2 comprises: bleeder circuit 21, bleeder circuit 21 is connected with the crystal oscillator 41 in described clock signal output module 4, described bleeder circuit 21 for carrying out dividing potential drop to described internal reference signal, to export the second voltage-controlled voltage; Wherein, described internal reference signal is that described crystal oscillator 41 produces according to inherent parameters and the reference voltage exported.
Wherein, the value of reference voltage is determined by crystal oscillator 41 inherent parameters, such as: the value of reference voltage can be 5V, 9V, 12V etc.Voltage-controlled voltage due to crystal oscillator 41 needs is generally less than the reference voltage that crystal oscillator 41 produces, therefore, the reference voltage needing bleeder circuit 21 pairs of crystal oscillators 41 to produce carries out dividing potential drop, such as: 1/2nd bleeder circuits can be divided into 1/2nd with reference to the value of voltage, then, using the magnitude of voltage after dividing potential drop as the second voltage-controlled voltage.In specific implementation process, bleeder circuit 21 can be resistance subnetwork.Because voltage-controlled voltage is for controlling the output frequency of crystal oscillator 41, the size changing voltage-controlled voltage can adjust the output frequency of crystal oscillator 41, and then controls the precision of clock signal.Therefore, under inner time service pattern, by the size regulating bleeder circuit 21 to adjust the second voltage-controlled voltage, and then the output accuracy of clock signal can be controlled.
In the embodiment of the present application, clock signal output module 4 comprises: crystal oscillator 41, be connected with the second end of described single-pole double-throw switch (SPDT) 34, described crystal oscillator 41 for exporting an original clock signal under the control of described first voltage-controlled voltage or described second voltage-controlled voltage; Second power splitter 42, is connected with described crystal oscillator 41, and described second power splitter 42 is for being divided into first via original clock signal and the second road original clock signal by described original clock signal; Filtering and amplifying circuit 43, is connected with described second power splitter 42, and described filtering and amplifying circuit 43, for amplifying and filtering process described first via original clock signal, exports described first clock signal or described second clock signal.
Specifically, when first voltage-controlled voltage refers to that outside time signal is normal, the voltage-controlled voltage that phase-locked loop circuit produces under outside time signal excitation, further, when outside time signal is normal, clock signal generating device is in outside time service pattern, and clock signal output module 4 exports above-mentioned original clock signal under the control of the first voltage-controlled voltage.Second voltage-controlled voltage refers to the voltage-controlled voltage that inner time service module 2 produces, further, when outside time signal is abnormal, clock signal generating device is in inner time service pattern, and clock signal output module 4 exports above-mentioned original clock signal under the control of the second voltage-controlled voltage.
Second power splitter 42 is connected with crystal oscillator 41, and the second power splitter 42 is divided into two-way for the original clock signal exported crystal oscillator 41, is respectively first via original clock signal and the second road original clock signal.Filtering and amplifying circuit 43 is connected with the second power splitter 42, for carrying out amplification process and filtering process to first via original clock information, and then exports the first clock signal or second clock signal.
Further, the second power splitter 42 is also connected with described phase-locked loop circuit, and when clock signal generating device is in outside time service pattern, by the effect of phase-locked loop, the clock signal precision that crystal oscillator 41 is exported is consistent with the precision of GPS time signal.
In the scheme of the embodiment of the present application, owing to adding detection module 3, by the automatic switchover between two kinds of different working modes, ensure that the clock signal needed for radar system under any circumstance can normally export.When detecting that outside GPS time signal is normal, clock signal generating device automatically switches to outside time service pattern.In this mode, utilize the high-precision GPS reference clock signal received, the low phase noise crystal oscillator of calibration clock signal generating device inside, by phase-locked mode, the clock signal of locking needed for output radar system.This clock signal, because there has been the calibration of GPS reference clock, makes it have high-precision characteristic.Meanwhile, the crystal oscillator 41 of clock signal generating device inside is low phase noise crystal oscillator, makes the clock signal exported have the characteristic of low phase noise.Further, because GPS reference clock signal can carry out time service to the other system of whole communication system, make radar system can be synchronous with whole communication system, improve communication quality.When detecting that outside GPS time signal is abnormal, clock signal generating device automatically switches to internal reference pattern, namely by the inner direct clock signal of low phase noise crystal oscillator, ensure that radar system is also can normal clock signal when outside time signal is abnormal, and then the reliability of raising radar system.
Embodiment two
Based on same inventive concept, the embodiment of the present application provides a kind of clock signal generation method, as shown in Figure 4, comprising:
S10: the outside time signal that the detection module in clock signal generating device detects the outside time service module of the described clock signal generating device of input is in normal condition or is in abnormal state;
S11: when described outside time signal is in described normal condition, control described clock signal generating device and be in outside time service pattern, and to be generated based on described outside time signal by the clock signal output module in clock signal generating device and export the first clock signal;
S12: when described outside time signal is in described abnormal state, control described clock signal generating device and be in inner time service pattern, and generate by the internal reference signal of described clock signal output module based on the described inner time service module of input and export second clock signal.
Optionally, the outside time signal that the detection module in clock signal generating device detects the outside time service module of the described clock signal generating device of input is in normal condition or is in abnormal state, comprising:
In described detection module, described outside time signal is divided into first via time signal and the second road time signal; The output voltage corresponding with the power of described outside time signal is exported according to described first via time signal; And more described output voltage and the comparative voltage pre-set;
Wherein, when described output voltage is greater than or equal to described comparative voltage, determine that described outside time signal is in normal condition; When described output voltage is less than described comparative voltage, determine that described outside time signal is in abnormal state.
Optionally, control described clock signal generating device and be in outside time service pattern, and to be generated based on described outside time signal by the clock signal output module in clock signal generating device and export the first clock signal, comprising:
The cutter head controlling the single-pole double-throw switch (SPDT) of described detection module is connected with described outside time service module, is in described outside time service pattern to make described clock signal generating device;
Described outside time service module generates the first voltage-controlled voltage based on described outside time signal;
Described clock signal output module generates and exports described first clock signal under the control of described first voltage-controlled voltage.
Optionally, control described clock signal generating device and be in inner time service pattern, and generate by the internal reference signal of described clock signal output module based on the described inner time service module of input and export second clock signal, comprising:
The cutter head controlling the single-pole double-throw switch (SPDT) of described detection module is connected with described inner time service module, is in described inner time service pattern to make described clock signal generating device;
The internal reference signal that described inner time service module exports based on the crystal oscillator in described clock signal output module generates and exports the second voltage-controlled voltage;
Described clock signal output module generates and exports described second clock signal under the control of described second voltage-controlled voltage.
Optionally, described clock signal output module generates and exports described second clock signal under the control of described second voltage-controlled voltage, comprising:
Described clock signal output module exports an original clock signal under the control of described second voltage-controlled voltage, amplifies and filtering process described original clock signal, exports described second clock signal.
By the one or more technical schemes in the embodiment of the present application, following one or more technique effect can be realized:
1, in the scheme of the embodiment of the present application, whether normal by automatically detecting outside time signal, when outside time signal is in normal condition, control clock signal generating device and be in outside time service pattern, when outside time signal is in abnormal state, control clock signal generating device and be in inner time service pattern, by the mode of operation of Automatic adjusument inside, compared to the high accuracy real-time clock that the outside time signal of traditional utilization realizes, when outside time signal is abnormal, still can clock signal, to realize the function of clock signal generating device place system, and then raising reliability.Compared to traditional high accuracy real-time clock realized with atomic clock, its cost is lower, and volume is less, and weight is lighter.
In the scheme of 2, the embodiment of the present application, utilize self-adaptation clock source, the clock signal generating device namely in the embodiment of the present application, synchronous with external GPS time signal, what can realize between whole communication link is synchronous, thus promotes communication quality.
Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (11)
1. a clock signal generating device, is characterized in that, described device comprises:
Outside time service module;
Inner time service module;
Detection module, is connected with described outside time service module and described inner time service module;
Clock signal output module;
Wherein, when the outside time signal that described detection module determines to input described outside time service module is in normal condition, control described clock signal generating device and be in outside time service pattern, described clock signal output module generates based on described outside time signal and exports the first clock signal;
When described detection module determines that described outside time signal is in abnormal state, control described clock signal generating device and be in inner time service pattern, described clock signal output module generates based on the internal reference signal of the described inner time service module of input and exports second clock signal.
2. device as claimed in claim 1, it is characterized in that, described detection module comprises:
First power splitter, for being divided into first via time signal and the second road time signal by described outside time signal;
Wave detector, is connected with described first power splitter, and described wave detector is used for generating according to described first via time signal and exporting the output voltage corresponding with the power of described outside time signal;
Comparator, is connected with described wave detector, the comparative voltage that described comparator is used for more described output voltage and pre-sets;
Single-pole double-throw switch (SPDT), the first end of described single-pole double-throw switch (SPDT) is connected with described comparator, and the cutter head of described single-pole double-throw switch (SPDT) is connected with described outside time service module or described inner time service module;
Wherein, when described output voltage is greater than or equal to described comparative voltage, the cutter head controlling described single-pole double-throw switch (SPDT) is connected with described outside time service module, is in described outside time service pattern to make described clock signal generating device; When described output voltage is less than described comparative voltage, the cutter head controlling described single-pole double-throw switch (SPDT) is connected with described inner time service module, is in described inner time service pattern to make described clock signal generating device.
3. device as claimed in claim 2, it is characterized in that, described outside time service module comprises:
Phase-locked loop circuit, is connected with described first power splitter; Described phase-locked loop circuit is used for exporting the first voltage-controlled voltage according to described second road time signal.
4. device as claimed in claim 3, it is characterized in that, described inner time service module comprises:
Bleeder circuit, described bleeder circuit is connected with the crystal oscillator in described clock signal output module, and described bleeder circuit is used for carrying out dividing potential drop to described internal reference signal, to export the second voltage-controlled voltage; Wherein, described internal reference signal is that described crystal oscillator produces according to inherent parameters and the reference voltage exported.
5. device as claimed in claim 4, it is characterized in that, clock signal output module comprises:
Crystal oscillator, is connected with the second end of described single-pole double-throw switch (SPDT), and described crystal oscillator for exporting an original clock signal under the control of described first voltage-controlled voltage or described second voltage-controlled voltage;
Second power splitter, is connected with described crystal oscillator, and described second power splitter is used for described original clock signal to be divided into first via original clock signal and the second road original clock signal;
Filtering and amplifying circuit, is connected with described second power splitter, and described filtering and amplifying circuit is used for amplifying and filtering process described first via original clock signal, exports described first clock signal or described second clock signal.
6. device as claimed in claim 5, it is characterized in that, described second power splitter is connected with described phase-locked loop circuit.
7. a clock signal generation method, is characterized in that, comprising:
The outside time signal that detection module in clock signal generating device detects the outside time service module of the described clock signal generating device of input is in normal condition or is in abnormal state;
When described outside time signal is in described normal condition, control described clock signal generating device and be in outside time service pattern, and to be generated based on described outside time signal by the clock signal output module in clock signal generating device and export the first clock signal;
When described outside time signal is in described abnormal state, control described clock signal generating device and be in inner time service pattern, and generate by the internal reference signal of described clock signal output module based on the described inner time service module of input and export second clock signal.
8. method as claimed in claim 7, is characterized in that, the outside time signal that the detection module in clock signal generating device detects the outside time service module of the described clock signal generating device of input is in normal condition or is in abnormal state, comprising:
In described detection module, described outside time signal is divided into first via time signal and the second road time signal; The output voltage corresponding with the power of described outside time signal is exported according to described first via time signal; And more described output voltage and the comparative voltage pre-set;
Wherein, when described output voltage is greater than or equal to described comparative voltage, determine that described outside time signal is in normal condition; When described output voltage is less than described comparative voltage, determine that described outside time signal is in abnormal state.
9. method as claimed in claim 8, it is characterized in that, control described clock signal generating device and be in outside time service pattern, and to be generated based on described outside time signal by the clock signal output module in clock signal generating device and export the first clock signal, comprising:
The cutter head controlling the single-pole double-throw switch (SPDT) of described detection module is connected with described outside time service module, is in described outside time service pattern to make described clock signal generating device;
Described outside time service module generates the first voltage-controlled voltage based on described outside time signal;
Described clock signal output module generates and exports described first clock signal under the control of described first voltage-controlled voltage.
10. method as claimed in claim 8, it is characterized in that, control described clock signal generating device and be in inner time service pattern, and generate by the internal reference signal of described clock signal output module based on the described inner time service module of input and export second clock signal, comprising:
The cutter head controlling the single-pole double-throw switch (SPDT) of described detection module is connected with described inner time service module, is in described inner time service pattern to make described clock signal generating device;
The internal reference signal that described inner time service module exports based on the crystal oscillator in described clock signal output module generates and exports the second voltage-controlled voltage;
Described clock signal output module generates and exports described second clock signal under the control of described second voltage-controlled voltage.
11. methods as claimed in claim 10, is characterized in that, described clock signal output module generates and exports described second clock signal under the control of described second voltage-controlled voltage, comprising:
Described clock signal output module exports an original clock signal under the control of described second voltage-controlled voltage, amplifies and filtering process described original clock signal, exports described second clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510560159.3A CN105187056B (en) | 2015-09-06 | 2015-09-06 | A kind of clock signal generating device and clock signal creating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510560159.3A CN105187056B (en) | 2015-09-06 | 2015-09-06 | A kind of clock signal generating device and clock signal creating method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105187056A true CN105187056A (en) | 2015-12-23 |
| CN105187056B CN105187056B (en) | 2019-02-26 |
Family
ID=54908945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510560159.3A Active CN105187056B (en) | 2015-09-06 | 2015-09-06 | A kind of clock signal generating device and clock signal creating method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105187056B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109254522A (en) * | 2018-09-26 | 2019-01-22 | 上海星秒光电科技有限公司 | Clock switching device, method and time-measurement device, method |
| CN112506776A (en) * | 2020-12-08 | 2021-03-16 | 上海市信息网络有限公司 | Processor chip debugging system |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1235424A (en) * | 1998-02-12 | 1999-11-17 | 日本电气株式会社 | Digital PLL circuit and clock generation method |
| WO2006029511A1 (en) * | 2004-09-13 | 2006-03-23 | Nortel Networks Limited | Method and apparatus for synchronizing internal state of frequency generators on a communications network |
| CN101783679A (en) * | 2008-12-29 | 2010-07-21 | 东部高科股份有限公司 | Phase locked loop circuit |
| CN102684478A (en) * | 2012-05-04 | 2012-09-19 | 上海艾为电子技术有限公司 | Charge pump circuit |
| CN102857201A (en) * | 2011-05-01 | 2013-01-02 | 英特赛尔美国有限公司 | Advanced clock synchronization circuit for switch mode power supplies |
| CN102938645A (en) * | 2011-09-08 | 2013-02-20 | 威盛电子股份有限公司 | Voltage controller, frequency-control circuit and signal generation device using the same |
| CN102970093A (en) * | 2012-11-02 | 2013-03-13 | 中国电子科技集团第四十一研究所 | Synchronizing system compatible with various clocks and synchronizing method thereof |
| CN104038215A (en) * | 2014-06-13 | 2014-09-10 | 南京邮电大学 | Automatic frequency calibration circuit for sigma-delta fractional frequency synthesizer |
| CN104702271A (en) * | 2013-12-10 | 2015-06-10 | 展讯通信（上海）有限公司 | Phase-locked loop circuit and calibration method for characteristic curves of voltage-controlled oscillator |
-
2015
- 2015-09-06 CN CN201510560159.3A patent/CN105187056B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1235424A (en) * | 1998-02-12 | 1999-11-17 | 日本电气株式会社 | Digital PLL circuit and clock generation method |
| WO2006029511A1 (en) * | 2004-09-13 | 2006-03-23 | Nortel Networks Limited | Method and apparatus for synchronizing internal state of frequency generators on a communications network |
| CN101783679A (en) * | 2008-12-29 | 2010-07-21 | 东部高科股份有限公司 | Phase locked loop circuit |
| CN102857201A (en) * | 2011-05-01 | 2013-01-02 | 英特赛尔美国有限公司 | Advanced clock synchronization circuit for switch mode power supplies |
| CN102938645A (en) * | 2011-09-08 | 2013-02-20 | 威盛电子股份有限公司 | Voltage controller, frequency-control circuit and signal generation device using the same |
| CN102684478A (en) * | 2012-05-04 | 2012-09-19 | 上海艾为电子技术有限公司 | Charge pump circuit |
| CN102970093A (en) * | 2012-11-02 | 2013-03-13 | 中国电子科技集团第四十一研究所 | Synchronizing system compatible with various clocks and synchronizing method thereof |
| CN104702271A (en) * | 2013-12-10 | 2015-06-10 | 展讯通信（上海）有限公司 | Phase-locked loop circuit and calibration method for characteristic curves of voltage-controlled oscillator |
| CN104038215A (en) * | 2014-06-13 | 2014-09-10 | 南京邮电大学 | Automatic frequency calibration circuit for sigma-delta fractional frequency synthesizer |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109254522A (en) * | 2018-09-26 | 2019-01-22 | 上海星秒光电科技有限公司 | Clock switching device, method and time-measurement device, method |
| CN112506776A (en) * | 2020-12-08 | 2021-03-16 | 上海市信息网络有限公司 | Processor chip debugging system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105187056B (en) | 2019-02-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20160074526A (en) | Frequency modulated radar level gauging | |
| US7777578B2 (en) | Oscillator circuit, in particular for mobile radio | |
| CN102195643B (en) | PLL apparatus | |
| CN105187056A (en) | Clock signal generation apparatus and clock signal generation method | |
| CN104485954A (en) | Control method for time equipment and time equipment | |
| CN102201811A (en) | Method and device for reducing microwave power frequency shift of atomic frequency standard | |
| CN101498761A (en) | Test method for step response performance of phase-locked loop system | |
| CN107181541B (en) | Electromagnetic spectrum monitoring receiver self-checking circuit and receiver | |
| CN103873049A (en) | Radio-frequency-signal measurement device and use method thereof | |
| EP3468041A1 (en) | Method of operating a phase locked loop and phase locked loop | |
| CN101826850A (en) | Method for controlling working frequency of quartz crystal and reference clock based on quartz crystal | |
| CN103326717B (en) | A kind of rubidium clock scan capture secondary locking method | |
| CN109474298A (en) | Wireless interspeaker radio circuit and frequency calibration system and method based on the circuit | |
| CN112290934B (en) | Controllable jitter clock generating device based on Bias-Tee signal synthesis | |
| CN103326719A (en) | Voltage controlled crystal oscillating device used in atomic frequency standard | |
| US10511313B1 (en) | Phase-detecting method and circuit for testing a delay locked loop/delay line | |
| CN109254522B (en) | Clock switching device and method and time measuring equipment and method | |
| CN210225403U (en) | Radio frequency circuit of wireless interphone | |
| US20220057480A1 (en) | Method and apparatus for generating frequency modulated continuous wave signal | |
| CN205070990U (en) | A crystal oscillator frequency dividing circuit that is used for radio general measuring instrument radio frequency local oscillator circuit | |
| US20190097642A1 (en) | Clock generation circuit and clock signal generation method | |
| CN210899137U (en) | High-overload short-distance ranging radio frequency circuit | |
| CN102025320A (en) | Device and method for improving frequency stability of WIFI (wireless fidelity) access point | |
| CN104330794A (en) | SAR echo simulator synchronization device and synchronization method | |
| CN218897214U (en) | Phase-locked loop, system, digital chip and radar sensor for quick locking |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |