CN101498761A - Test method for step response performance of phase-locked loop system - Google Patents

Test method for step response performance of phase-locked loop system Download PDF

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Publication number
CN101498761A
CN101498761A CNA2008100575427A CN200810057542A CN101498761A CN 101498761 A CN101498761 A CN 101498761A CN A2008100575427 A CNA2008100575427 A CN A2008100575427A CN 200810057542 A CN200810057542 A CN 200810057542A CN 101498761 A CN101498761 A CN 101498761A
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frequency
phase
locked loop
output voltage
voltage signal
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CN101498761B (en
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罗晋
段军辉
张现聚
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BEIJING VIVACE TONGYONG MICROELECTRONICS TECHNOLOGY Co Ltd
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BEIJING VIVACE TONGYONG MICROELECTRONICS TECHNOLOGY Co Ltd
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Abstract

The invention discloses a testing method for the step response performance of a phase-locked loop system, aiming at improving the testing precision of the step response performance. The testing method comprises the steps as follows: during the process that the phase-locked loop system steps from one stable oscillating frequency to another oscillating frequency, the waveform of an output voltage signal is recorded; the frequency information of the output voltage signal during the stepping process is obtained according to the waveform; and parameters of the step response performance are obtained according to the frequency information. The invention avoids leading testing parameters from a feedback loop, can not lead noise to an original system and improves the measuring precision.

Description

The method of testing of the step response performance of phase-locked loop systems
Technical field
The present invention relates to phase-locked loop systems, specifically, relate to a kind of method of testing of step response performance of phase-locked loop systems.
Background technology
In application such as data acquisition, phaselocked loop is a kind of very useful simultaneous techniques.Phaselocked loop is actually a kind of feedback circuit, and characteristics are to utilize the frequency and the phase place of the reference signal control loop internal oscillation signal of outside input, makes the phase-locking of loop clock internal and reference signal clock.Phaselocked loop work process in, when the frequency of output voltage signal equates with the frequency of reference signal, the phase difference value that output voltage and input voltage are maintained fixed, promptly the phase place of output voltage and input voltage is lockable, the origin of phaselocked loop title that Here it is.
Fig. 1 shows the basic composition of phaselocked loop at present commonly used, mainly comprises phase frequency detector 10, loop filter 20 and voltage controlled oscillator 30 etc., wherein:
Phase frequency detector 10 is phase comparison devices, is used for reference signal S iFeedback signal S with voltage controlled oscillator 30 o(also being the output voltage signal of phaselocked loop) carries out the phase bit comparison, detects the error voltage S corresponding to two signal phase differences e
Loop filter 20 links to each other with phase frequency detector 10, is used for error voltage S eCarrying out filtering and level and smooth, is a low-pass filter under most of situations, with the variation and other labile factors influence to whole phaselocked loop of filtering owing to data, such as error voltage S eIn radio-frequency component and noise or the like, to guarantee the desired performance of loop, increase the stability of system; Through the error voltage S after the sliding processing of filtering peace eForm control voltage S d, be transferred to voltage controlled oscillator 30;
Voltage controlled oscillator 30 links to each other with loop filter 20, at control voltage S dControl under, the output voltage signal frequency of voltage controlled oscillator 30 also is the output voltage signal S of phaselocked loop oFrequency, to reference signal S iFrequency draw close, lock until eliminating frequency difference.
Overshoot and loop stability time are two different technical indicators of tolerance phase-locked loop systems, but all are used for the characteristic of step response of quantization system.For different application, wherein a certain may be tended to or bias toward to its technical requirement.Wherein overshoot refers to phase-locked loop systems and jumps to the process of another oscillation frequency B from a stable oscillation frequency A, and first crest or the trough of control voltage recently quantize with crest value or the trough value percentage with the expection setting value usually.The loop stability time wherein refers to phase-locked loop systems and jumps to another oscillation frequency B and settle out the needed time from a stable oscillation frequency A.
General control voltage S in the middle of existing application by emulation voltage controlled oscillator 30 d, come overshoot and loop stability time are calculated, but variant with actual value.Because the control voltage S of voltage controlled oscillator 30 dAs a node in the whole loop of phaselocked loop, and inconvenient between loop filter 20 and voltage controlled oscillator 30, draw, strengthened the difficulty of direct test.And, even the control voltage of voltage controlled oscillator 30 is drawn between loop filter 20 and voltage controlled oscillator 30, control voltage S dAlso be subjected to the influence of outside noise easily, promptly brought measuring error, can not obtain accurate measured value.
Summary of the invention
Technical matters to be solved by this invention is the method that is to provide a kind of phase locked loop system overshoot parameter, to improve measuring accuracy.
In order to solve the problems of the technologies described above, the invention provides a kind of method of testing of step response performance of phase-locked loop systems, step comprises:
The saltus step process of described phase-locked loop systems, write down the waveform of the output voltage signal of described phase-locked loop systems from a stable oscillation frequency to another oscillation frequency;
Obtain the frequency information of output voltage signal in the described saltus step process according to described waveform, draw the parameter of described step response performance again according to this frequency information.
In the method for testing of the step response performance of aforesaid phase-locked loop systems, write down the waveform of the output voltage signal of described phase-locked loop systems, can realize by waveform acquisition equipment.
Further, described waveform acquisition equipment can comprise oscillograph.
In the method for testing of the step response performance of aforesaid phase-locked loop systems, the parameter of described step response performance can comprise overshoot and/or loop stability time.
Wherein, can be according to first peak value of frequency or the valley of described output voltage signal after the described phase-locked loop systems saltus step, and the frequency final value of described phase-locked loop systems described output voltage signal when entering steady state (SS), draw described overshoot.
Further, the expression formula that draws described overshoot is:
Overshoot=(first peak value of frequency-frequency final value)/frequency final value, perhaps:
Overshoot=(first valley of frequency-frequency final value)/frequency final value.
And the frequency that can be according to described phase-locked loop systems be carved into described output voltage signal during from described saltus step initial enters the difference of steady state (SS) between constantly, draws the described loop stability time.
Compared with prior art, the present invention has avoided drawing test volume owing to be the output voltage signal of system to be tested obtain overshoot and these two parameters of loop stability time from backfeed loop, can not introduce noise to original system, easy to operate, improved measuring accuracy.
Description of drawings
Fig. 1 is the basic composition synoptic diagram of phaselocked loop in the prior art.
Fig. 2 is the inventive method is drawn test volume from system's output voltage signal a synoptic diagram.
Embodiment
Describe embodiments of the present invention in detail below with reference to drawings and Examples, how the application technology means solve technical matters to the present invention whereby, and the implementation procedure of reaching technique effect can fully understand and implements according to this.
Basic thought of the present invention is the variation according to system's output voltage signal frequency, comes the overshoot and the loop stability time of indirect measurement systems.Because the oscillation frequency of voltage controlled oscillator 30 also is that system's output voltage signal frequency is followed control voltage S dVariation and change, and then realize the overshoot and the measurement of loop stability time of system.
As shown in Figure 2, with the output of voltage controlled oscillator 30, also be the output voltage S of phaselocked loop oSignal is input in the middle of the waveform acquisition equipment 40 as test signal, obtains the saltus step waveform of phase-locked loop systems output voltage signal frequency.It is oscillograph that the typical case of waveform acquisition equipment 40 uses.
Formula 1 has provided the principle of work of voltage controlled oscillator 30:
θ Out=∫ (ω 0+ K VcoV Control) dt (formula 1)
Wherein:
θ OutPhase place for the output voltage signal of voltage controlled oscillator 30;
ω 0Built-in oscillation angular frequency for circuit;
V ControlBe control voltage S dMagnitude of voltage;
K VcoGain for voltage controlled oscillator.
Can draw the phase theta of the output voltage signal of voltage controlled oscillator 30 thus OutControlled voltage S dControl.Because frequency is the differential of phase place, therefore formula 1 is differentiated and can be obtained:
ω Out=K VcoV Control(formula 2)
ω wherein OutBe output voltage signal frequency, K VcoBe constant, by formula 2 as can be seen, the output voltage signal frequency of system is with control voltage S dMagnitude of voltage V ControlChange and change.Therefore as control voltage S dWhen reaching peak value, the output voltage signal frequencies omega OutAlso reach peak value, as control voltage S dWhen stablizing, the output voltage signal frequencies omega OutAlso reach stable, and be linear relation between the two.Therefore by measuring the output voltage signal frequencies omega Out, the just effectively overshoot of computing system and loop stability time parameter are because these two parameters all can be directly according to the output voltage signal frequencies omega OutAnd obtain.
From the waveform of the output voltage signal frequency that waveform acquisition equipment write down, can obtain the peak value of output voltage signal frequency, and the output voltage signal frequency final value of system when entering steady state (SS), again according to system's overshoot computing formula, can obtain the overshoot parameter of system.Wherein system's overshoot computing formula is:
Overshoot=(first peak value of frequency-frequency final value)/frequency final value, perhaps:
Overshoot=(first valley of frequency final value-frequency)/frequency final value.
The waveform of the output voltage signal frequency that is write down by waveform acquisition equipment 40, and system enters the moment of steady state (SS), the system that can also obtain is carved into when initial from saltus step and enters the difference of steady state (SS) between constantly, and this difference is the loop stability time parameter.
Though the disclosed embodiment of the present invention as above, the embodiment that described content just adopts for the ease of understanding the present invention is not in order to limit the present invention.Technician in any the technical field of the invention; under the prerequisite that does not break away from the disclosed spirit and scope of the present invention; can do any modification and variation what implement in form and on the details; but scope of patent protection of the present invention still must be as the criterion with the scope that appending claims was defined.

Claims (7)

1, a kind of method of testing of step response performance of phase-locked loop systems is characterized in that:
The saltus step process of described phase-locked loop systems, write down the waveform of the output voltage signal of described phase-locked loop systems from a stable oscillation frequency to another oscillation frequency;
Obtain the frequency information of output voltage signal in the described saltus step process according to described waveform, draw the parameter of described step response performance again according to this frequency information.
2, the method for claim 1 is characterized in that:
Write down the waveform of the output voltage signal of described phase-locked loop systems, realize by a waveform acquisition equipment.
3, method as claimed in claim 2 is characterized in that:
Described waveform acquisition equipment comprises oscillograph.
4, the method for claim 1 is characterized in that:
The parameter of described step response performance comprises overshoot and/or loop stability time.
5, method as claimed in claim 4 is characterized in that:
According to first peak value of frequency or the valley of described output voltage signal after the described phase-locked loop systems saltus step, and described phase-locked loop systems enters the frequency final value of described output voltage signal after the steady state (SS), draws described overshoot.
6, method as claimed in claim 5 is characterized in that:
The expression formula that draws described overshoot is:
Overshoot=(first peak value of frequency-frequency final value)/frequency final value, perhaps:
Overshoot=(first valley of frequency-frequency final value)/frequency final value.
7, method as claimed in claim 4 is characterized in that:
The frequency that is carved into described output voltage signal according to described phase-locked loop systems during from described saltus step initial enters the difference of steady state (SS) between constantly, draws the described loop stability time.
CN2008100575427A 2008-02-02 2008-02-02 Test method for step response performance of phase-locked loop system Expired - Fee Related CN101498761B (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103441758A (en) * 2013-09-05 2013-12-11 中国电子科技集团公司第十研究所 Loop bandwidth test algorithm module for phase-locked loop
CN107528590A (en) * 2016-06-22 2017-12-29 中芯国际集成电路制造（天津）有限公司 The settling time method of testing and system of digital analog converter
CN109101008A (en) * 2017-06-21 2018-12-28 上海电气风电集团有限公司 The test method of delay is communicated and responded between main control PLC and current transformer
CN110190846A (en) * 2019-04-15 2019-08-30 上海酷芯微电子有限公司 The anti-frequency over shoot circuit of phaselocked loop
CN110971230A (en) * 2018-09-30 2020-04-07 苏州四方杰芯电子科技有限公司 High-performance phase-locked loop circuit control system
CN112904133A (en) * 2021-02-10 2021-06-04 南方电网科学研究院有限责任公司 Step performance testing method and system of direct current control protection system

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US5295079A (en) * 1991-07-18 1994-03-15 National Semiconductor Corporation Digital testing techniques for very high frequency phase-locked loops
US6320424B1 (en) * 2000-06-30 2001-11-20 Intel Corporation Method of providing and circuit for providing phase lock loop frequency overshoot control
JP4502165B2 (en) * 2001-04-10 2010-07-14 ルネサスエレクトロニクス株式会社 Lock detection circuit
GB2383697A (en) * 2001-12-27 2003-07-02 Zarlink Semiconductor Inc Method of speeding lock of PLL
CN100559200C (en) * 2004-02-13 2009-11-11 Nxp股份有限公司 The method and the device that are used for phase locked loop

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103441758A (en) * 2013-09-05 2013-12-11 中国电子科技集团公司第十研究所 Loop bandwidth test algorithm module for phase-locked loop
CN107528590A (en) * 2016-06-22 2017-12-29 中芯国际集成电路制造（天津）有限公司 The settling time method of testing and system of digital analog converter
CN107528590B (en) * 2016-06-22 2020-07-28 中芯国际集成电路制造（天津）有限公司 Method and system for testing establishment time of digital-to-analog converter
CN109101008A (en) * 2017-06-21 2018-12-28 上海电气风电集团有限公司 The test method of delay is communicated and responded between main control PLC and current transformer
CN110971230A (en) * 2018-09-30 2020-04-07 苏州四方杰芯电子科技有限公司 High-performance phase-locked loop circuit control system
CN110971230B (en) * 2018-09-30 2023-06-30 苏州四方杰芯电子科技有限公司 High-performance phase-locked loop circuit control system
CN110190846A (en) * 2019-04-15 2019-08-30 上海酷芯微电子有限公司 The anti-frequency over shoot circuit of phaselocked loop
CN112904133A (en) * 2021-02-10 2021-06-04 南方电网科学研究院有限责任公司 Step performance testing method and system of direct current control protection system
CN112904133B (en) * 2021-02-10 2022-02-25 南方电网科学研究院有限责任公司 Step performance testing method and system of direct current control protection system

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